From 00e31226cd78828080aea53addb208fc7e87f747 Mon Sep 17 00:00:00 2001 From: Julius Bairaktaris Date: Wed, 9 Sep 2026 15:55:14 +0200 Subject: [PATCH] qualcommax: qca_ppe: enable TX pause on an XGMAC port ppe_xgmac_link_up() masked PPE_XGMAC_TX_FLOW_ENABLE (bit 1) but wrote PPE_XGMAC_RX_FLOW_ENABLE (bit 0) as the value, so val & mask was always zero and TX pause never enabled on an XGMAC port regardless of what phylink negotiated. The receive side beside it is correct and is what makes the pair the evidence. Only ports muxed to their XGMAC are affected - the 10G AQR ports on other boards. Found by inspection; there is no XGMAC port on the bench to run it on. Fixes: 142104bb90b3 ("qualcommax: add PPE driver") Assisted-by: Claude:claude-opus-5 Signed-off-by: Julius Bairaktaris Link: https://github.com/openwrt/openwrt/pull/25084 Signed-off-by: Robert Marko --- .../files/drivers/net/ethernet/qualcomm/qca_ppe_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c b/target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c index d50badc1ea5..1f3e6086c04 100644 --- a/target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c +++ b/target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c @@ -149,7 +149,7 @@ static void ppe_xgmac_link_up(struct qca_ppe_priv *priv, int port, regmap_write_bits(priv->regmap, PPE_XGMAC_TX_FLOW_CTRL(xgmac), PPE_XGMAC_TX_FLOW_ENABLE, - tx_pause ? PPE_XGMAC_RX_FLOW_ENABLE : 0); + tx_pause ? PPE_XGMAC_TX_FLOW_ENABLE : 0); regmap_write_bits(priv->regmap, PPE_XGMAC_RX_FLOW_CTRL(xgmac), PPE_XGMAC_RX_FLOW_ENABLE,