From 07a2f397383799cc0acc73bec3a61eceff83262e Mon Sep 17 00:00:00 2001 From: Rustam Adilov Date: Sat, 12 Sep 2026 14:43:01 +0500 Subject: [PATCH] realtek: soc: add support for RTL9607C Tables The RTL9607C SoC is another Otto family member with very identical indirect table access as the rest of existing switch SoCs. It has two registers that control tables: TBL_ACCESS_CTRL for LUT, VLAN, ACL and Classification tables and NAT_TBL_ACCESS_CTRL for HWNAT related tables. Add these two main control registers to OTTO_REG_LIST and all of their tables to otto_table_maps and otto_table_id in header file. Signed-off-by: Rustam Adilov Link: https://github.com/openwrt/openwrt/pull/25136 Signed-off-by: Markus Stockhausen --- .../drivers/soc/realtek/otto_table.c | 42 +++++++++++++++++-- .../include/linux/soc/realtek/otto_table.h | 34 +++++++++++++++ 2 files changed, 73 insertions(+), 3 deletions(-) diff --git a/target/linux/realtek/files-6.18/drivers/soc/realtek/otto_table.c b/target/linux/realtek/files-6.18/drivers/soc/realtek/otto_table.c index d1efd879e70..d151281bd70 100644 --- a/target/linux/realtek/files-6.18/drivers/soc/realtek/otto_table.c +++ b/target/linux/realtek/files-6.18/drivers/soc/realtek/otto_table.c @@ -47,7 +47,7 @@ struct otto_table { * from here, so an entry cannot be described in one place and not in the others. */ -#define OTTO_REG_LIST(_) \ +#define OTTO_REG_LIST(_) \ _(OTTO_REG_8380_L2, 0x6900, 0x6900, 0x6908, 0x6908, 3, -1, 15, 13, 1, 0, 12, 16, 16, -1, -1) \ _(OTTO_REG_8380_0, 0x6914, 0x6914, 0x6918, 0x6918, 18, -1, 14, 12, 1, 0, 11, 15, 15, -1, -1) \ _(OTTO_REG_8380_1, 0xA4C8, 0xA4C8, 0xA4CC, 0xA4CC, 6, -1, 14, 12, 1, 0, 11, 15, 15, -1, -1) \ @@ -67,6 +67,8 @@ struct otto_table { _(OTTO_REG_9310_3, 0x0200, 0x0200, 0x0204, 0x0204, 9, -1, 15, 12, 0, 0, 11, 16, 16, -1, -1) \ _(OTTO_REG_9310_4, 0x20dc, 0x20dc, 0x20e0, 0x20e0, 29, -1, 7, 6, 0, 0, 5, 8, 8, -1, -1) \ _(OTTO_REG_9310_5, 0x7e1c, 0x7e1c, 0x7e20, 0x7e20, 53, -1, 8, 6, 0, 0, 5, 9, 9, -1, -1) \ + _(OTTO_REG_9607C_0, 0x12000, 0x12004, 0x12008, 0x1201c, 5, 13, 3, 0, 0, 12, 23, -1, -1, 5, 12) \ + _(OTTO_REG_9607C_NAT, 0x801100, 0x801100, 0x801180, 0x801110, 8, -1, -1, 16, 0, 0, 15, 25, 24, -1, -1) \ #define OTTO_REG_ENUM(name, ctrl_addr, sts_addr, wr_data, rd_data, max, \ busy_bit, cbit, tbit, rmode, addr_lsb, addr_msb, \ @@ -251,6 +253,40 @@ static const struct otto_table_map otto_table_maps[OTTO_TBL_COUNT] = { TBL_MAP(RTL9310_TBL_STAT_PORT_MIB_CNTR, OTTO_REG_9310_5, 0, 53, 57, 0), TBL_MAP(RTL9310_TBL_STAT_PORT_PRVTE_CNTR, OTTO_REG_9310_5, 1, 28, 57, 0), + + TBL_MAP(RTL9607C_TBL_L2_MC_DSL, OTTO_REG_9607C_0, 0, 3, 2112, 0), + TBL_MAP(RTL9607C_TBL_L2_UC, OTTO_REG_9607C_0, 0, 3, 2112, 0), + TBL_MAP(RTL9607C_TBL_L3_MC, OTTO_REG_9607C_0, 0, 3, 2112, 0), + TBL_MAP(RTL9607C_TBL_L3_MC_FID, OTTO_REG_9607C_0, 0, 3, 2112, 0), + TBL_MAP(RTL9607C_TBL_L3_MC_VID, OTTO_REG_9607C_0, 0, 3, 2112, 0), + TBL_MAP(RTL9607C_TBL_VLAN, OTTO_REG_9607C_0, 1, 1, 4096, 0), + TBL_MAP(RTL9607C_TBL_ACL_DATA, OTTO_REG_9607C_0, 2, 5, 128, 128), + TBL_MAP(RTL9607C_TBL_ACL_MASK, OTTO_REG_9607C_0, 2, 5, 128, 0), + TBL_MAP(RTL9607C_TBL_ACL_ACTION_TABLE, OTTO_REG_9607C_0, 3, 2, 128, 0), + TBL_MAP(RTL9607C_TBL_CF_MASK_T0, OTTO_REG_9607C_0, 4, 2, 256, 0), + TBL_MAP(RTL9607C_TBL_CF_MASK_T1, OTTO_REG_9607C_0, 4, 2, 256, 0), + TBL_MAP(RTL9607C_TBL_CF_MASK_T2, OTTO_REG_9607C_0, 4, 2, 256, 0), + TBL_MAP(RTL9607C_TBL_CF_RULE_T0, OTTO_REG_9607C_0, 4, 2, 256, 256), + TBL_MAP(RTL9607C_TBL_CF_RULE_T1, OTTO_REG_9607C_0, 4, 2, 256, 256), + TBL_MAP(RTL9607C_TBL_CF_RULE_T2, OTTO_REG_9607C_0, 4, 2, 256, 256), + TBL_MAP(RTL9607C_TBL_CF_ACTION_DS, OTTO_REG_9607C_0, 5, 2, 256, 0), + TBL_MAP(RTL9607C_TBL_CF_ACTION_US, OTTO_REG_9607C_0, 5, 2, 256, 0), + + TBL_MAP(RTL9607C_TBL_INTERFACE, OTTO_REG_9607C_NAT, 0, 5, 16, 0), + TBL_MAP(RTL9607C_TBL_ETHER_TYPE, OTTO_REG_9607C_NAT, 1, 1, 8, 0), + TBL_MAP(RTL9607C_TBL_CAM_TAG, OTTO_REG_9607C_NAT, 2, 1, 64, 0), + TBL_MAP(RTL9607C_TBL_FB_EXT_PORT, OTTO_REG_9607C_NAT, 3, 1, 32, 0), + TBL_MAP(RTL9607C_TBL_WAN_ACCESS_LIMIT, OTTO_REG_9607C_NAT, 4, 1, 32, 0), + TBL_MAP(RTL9607C_TBL_FLOW_TABLE_PATH1_2, OTTO_REG_9607C_NAT, 8, 8, 4096, 0), + TBL_MAP(RTL9607C_TBL_FLOW_TABLE_PATH3_4, OTTO_REG_9607C_NAT, 8, 8, 4096, 0), + TBL_MAP(RTL9607C_TBL_FLOW_TABLE_PATH5, OTTO_REG_9607C_NAT, 8, 8, 4096, 0), + TBL_MAP(RTL9607C_TBL_FLOW_TABLE_PATH6, OTTO_REG_9607C_NAT, 8, 8, 4096, 0), + TBL_MAP(RTL9607C_TBL_CAM, OTTO_REG_9607C_NAT, 9, 8, 64, 0), + TBL_MAP(RTL9607C_TBL_MAC_IDX, OTTO_REG_9607C_NAT, 10, 1, 256, 0), + TBL_MAP(RTL9607C_TBL_FLOW_TABLE_TAG, OTTO_REG_9607C_NAT, 11, 1, 4096, 0), + TBL_MAP(RTL9607C_TBL_TCAM, OTTO_REG_9607C_NAT, 12, 8, 64, 0), + TBL_MAP(RTL9607C_TBL_TCAM_RAW_TABLE_PATH1_2, OTTO_REG_9607C_NAT, 13, 5, 64, 0), + TBL_MAP(RTL9607C_TBL_TCAM_RAW_TABLE_PATH3_5, OTTO_REG_9607C_NAT, 13, 5, 64, 0), }; /* Whether the tables can be reached yet. A consumer that probes before this @@ -338,8 +374,8 @@ static struct otto_table *otto_table_reg(int handle) } /* The command register masks the index to the width of its index field, which - * cannot express the bound: it is wider than the table on 66 of the tables, - * exactly as wide on the other 38, and six tables do not have a power-of-two + * cannot express the bound: it is wider than the table on 95 of the tables, + * exactly as wide on the other 41, and 11 tables do not have a power-of-two * row count at all. */ static bool otto_table_index_ok(int handle, int idx) diff --git a/target/linux/realtek/files-6.18/include/linux/soc/realtek/otto_table.h b/target/linux/realtek/files-6.18/include/linux/soc/realtek/otto_table.h index b1b10b92d94..c7271a36821 100644 --- a/target/linux/realtek/files-6.18/include/linux/soc/realtek/otto_table.h +++ b/target/linux/realtek/files-6.18/include/linux/soc/realtek/otto_table.h @@ -144,6 +144,40 @@ enum otto_table_id { RTL9310_TBL_STAT_PORT_MIB_CNTR, RTL9310_TBL_STAT_PORT_PRVTE_CNTR, + RTL9607C_TBL_L2_MC_DSL, + RTL9607C_TBL_L2_UC, + RTL9607C_TBL_L3_MC, + RTL9607C_TBL_L3_MC_FID, + RTL9607C_TBL_L3_MC_VID, + RTL9607C_TBL_VLAN, + RTL9607C_TBL_ACL_DATA, + RTL9607C_TBL_ACL_MASK, + RTL9607C_TBL_ACL_ACTION_TABLE, + RTL9607C_TBL_CF_MASK_T0, + RTL9607C_TBL_CF_MASK_T1, + RTL9607C_TBL_CF_MASK_T2, + RTL9607C_TBL_CF_RULE_T0, + RTL9607C_TBL_CF_RULE_T1, + RTL9607C_TBL_CF_RULE_T2, + RTL9607C_TBL_CF_ACTION_DS, + RTL9607C_TBL_CF_ACTION_US, + + RTL9607C_TBL_INTERFACE, + RTL9607C_TBL_ETHER_TYPE, + RTL9607C_TBL_CAM_TAG, + RTL9607C_TBL_FB_EXT_PORT, + RTL9607C_TBL_WAN_ACCESS_LIMIT, + RTL9607C_TBL_FLOW_TABLE_PATH1_2, + RTL9607C_TBL_FLOW_TABLE_PATH3_4, + RTL9607C_TBL_FLOW_TABLE_PATH5, + RTL9607C_TBL_FLOW_TABLE_PATH6, + RTL9607C_TBL_CAM, + RTL9607C_TBL_MAC_IDX, + RTL9607C_TBL_FLOW_TABLE_TAG, + RTL9607C_TBL_TCAM, + RTL9607C_TBL_TCAM_RAW_TABLE_PATH1_2, + RTL9607C_TBL_TCAM_RAW_TABLE_PATH3_5, + OTTO_TBL_END };