diff --git a/target/linux/lantiq/ase/config-6.12 b/target/linux/lantiq/ase/config-6.12 deleted file mode 100644 index 3d8c15ad8cb..00000000000 --- a/target/linux/lantiq/ase/config-6.12 +++ /dev/null @@ -1,23 +0,0 @@ -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -CONFIG_CPU_MIPSR1=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_FIRMWARE_MEMMAP=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_HW_RANDOM=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_ETOP=y -# CONFIG_NET_SWITCHDEV is not set -CONFIG_NLS=y -CONFIG_SGL_ALLOC=y -CONFIG_SOC_AMAZON_SE=y -# CONFIG_SOC_XWAY is not set -CONFIG_TARGET_ISA_REV=1 -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/config-6.12 b/target/linux/lantiq/config-6.12 deleted file mode 100644 index 3bb81fe46f4..00000000000 --- a/target/linux/lantiq/config-6.12 +++ /dev/null @@ -1,188 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_CEVT_R4K=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MITIGATIONS=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_GF128MUL=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_INFO=y -CONFIG_DMA_NEED_SYNC=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DTC=y -# CONFIG_DT_EASY50712 is not set -CONFIG_EARLY_PRINTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FORCE_NR_CPUS=y -CONFIG_FS_IOMAP=y -CONFIG_FUNCTION_ALIGNMENT=0 -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_MM_LANTIQ=y -CONFIG_GPIO_STP_XWAY=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LANTIQ=y -CONFIG_LANTIQ_DT_NONE=y -# CONFIG_LANTIQ_ETOP is not set -CONFIG_LANTIQ_WDT=y -# CONFIG_LANTIQ_XRX200 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MMU_LAZY_TLB_REFCOUNT=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_LANTIQ=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_BRNIMAGE_FW=y -CONFIG_MTD_SPLIT_EVA_FW=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_EGRESS=y -CONFIG_NET_INGRESS=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_XGRESS=y -CONFIG_NO_EXCEPT_FILL=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_GPIO_MM_GPIOCHIP=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHY_LANTIQ_RCU_USB2=y -# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_LANTIQ=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_XWAY=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_LANTIQ=y -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_LANTIQ=y -CONFIG_SERIAL_LANTIQ_CONSOLE=y -# CONFIG_SOC_AMAZON_SE is not set -# CONFIG_SOC_FALCON is not set -CONFIG_SOC_TYPE_XWAY=y -CONFIG_SOC_XWAY=y -CONFIG_SPI=y -CONFIG_SPI_LANTIQ_SSC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_SYS_SUPPORTS_VPE_LOADER=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/lantiq/falcon/config-6.12 b/target/linux/lantiq/falcon/config-6.12 deleted file mode 100644 index b176d6e7678..00000000000 --- a/target/linux/lantiq/falcon/config-6.12 +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" -# CONFIG_NET_SWITCHDEV is not set -CONFIG_PINCTRL_FALCON=y -CONFIG_SOC_FALCON=y -# CONFIG_SOC_XWAY is not set -CONFIG_SPI_FALCON=y diff --git a/target/linux/lantiq/patches-6.12/001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-6.12/001-MIPS-lantiq-add-pcie-driver.patch deleted file mode 100644 index bdd851e2a9e..00000000000 --- a/target/linux/lantiq/patches-6.12/001-MIPS-lantiq-add-pcie-driver.patch +++ /dev/null @@ -1,148 +0,0 @@ -From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:12:28 +0200 -Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver - -Signed-off-by: John Crispin ---- - arch/mips/lantiq/Kconfig | 10 + - arch/mips/lantiq/xway/sysctrl.c | 2 + - arch/mips/pci/Makefile | 2 + - arch/mips/pci/fixup-lantiq.c | 5 +- - arch/mips/pci/pci-legacy.c | 25 + - drivers/pci/pcie/Kconfig | 2 +- - include/linux/pci.h | 2 + - include/linux/pci_ids.h | 6 + - 8 files changed, 52 insertions(+), 3 deletions(-) - ---- a/arch/mips/lantiq/Kconfig -+++ b/arch/mips/lantiq/Kconfig -@@ -20,6 +20,7 @@ config SOC_XWAY - bool "XWAY" - select SOC_TYPE_XWAY - select HAVE_PCI -+ select ARCH_SUPPORTS_MSI - select MFD_SYSCON - select MFD_CORE - -@@ -52,4 +53,13 @@ config PCI_LANTIQ - bool "PCI Support" - depends on SOC_XWAY && PCI - -+config PCIE_LANTIQ -+ bool "PCIE Support" -+ depends on SOC_XWAY && PCI -+ -+config PCIE_LANTIQ_MSI -+ bool -+ depends on PCIE_LANTIQ && PCI_MSI -+ default y -+ - endif ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -41,6 +41,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o - obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o - obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o - obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o -+obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie.o fixup-lantiq-pcie.o -+obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o - obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o - obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o - obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ---- a/arch/mips/pci/fixup-lantiq.c -+++ b/arch/mips/pci/fixup-lantiq.c -@@ -6,13 +6,24 @@ - - #include - #include -+#include -+#include "ifxmips_pci_common.h" - - int pcibios_plat_dev_init(struct pci_dev *dev) - { -+#ifdef CONFIG_PCIE_LANTIQ -+ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) -+ ifx_pcie_bios_plat_dev_init(dev); -+#endif - return 0; - } - - int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) - { -+#ifdef CONFIG_PCIE_LANTIQ -+ if (pci_find_capability((struct pci_dev *)dev, PCI_CAP_ID_EXP)) -+ return ifx_pcie_bios_map_irq(dev, slot, pin); -+#endif -+ - return of_irq_parse_and_map_pci(dev, slot, pin); - } ---- a/arch/mips/pci/pci-legacy.c -+++ b/arch/mips/pci/pci-legacy.c -@@ -312,3 +312,30 @@ char *__init pcibios_setup(char *str) - return pcibios_plat_setup(str); - return str; - } -+ -+int pcibios_host_nr(void) -+{ -+ int count = 0; -+ struct pci_controller *hose; -+ list_for_each_entry(hose, &controllers, list) { -+ count++; -+ } -+ return count; -+} -+EXPORT_SYMBOL(pcibios_host_nr); -+ -+int pcibios_1st_host_bus_nr(void) -+{ -+ int bus_nr = 0; -+ struct pci_controller *hose; -+ -+ hose = list_first_entry_or_null(&controllers, struct pci_controller, list); -+ -+ if (hose != NULL) { -+ if (hose->bus != NULL) { -+ bus_nr = hose->bus->number + 1; -+ } -+ } -+ return bus_nr; -+} -+EXPORT_SYMBOL(pcibios_1st_host_bus_nr); ---- a/drivers/pci/pcie/Kconfig -+++ b/drivers/pci/pcie/Kconfig -@@ -64,6 +64,7 @@ config PCIEAER_CXL - config PCIE_ECRC - bool "PCI Express ECRC settings control" - depends on PCIEAER -+ default n - help - Used to override firmware/bios settings for PCI Express ECRC - (transaction layer end-to-end CRC checking). ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -1652,6 +1652,8 @@ void pci_walk_bus_locked(struct pci_bus - void *userdata); - int pci_cfg_space_size(struct pci_dev *dev); - unsigned char pci_bus_max_busnr(struct pci_bus *bus); -+int pcibios_host_nr(void); -+int pcibios_1st_host_bus_nr(void); - void pci_setup_bridge(struct pci_bus *bus); - resource_size_t pcibios_window_alignment(struct pci_bus *bus, - unsigned long type); ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -1111,6 +1111,12 @@ - #define PCI_DEVICE_ID_SGI_IOC3 0x0003 - #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 - -+#define PCI_VENDOR_ID_INFINEON 0x15D1 -+#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F -+#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 -+#define PCI_VENDOR_ID_LANTIQ 0x1BEF -+#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 -+ - #define PCI_VENDOR_ID_WINBOND 0x10ad - #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 - #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 diff --git a/target/linux/lantiq/patches-6.12/004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-6.12/004-MIPS-lantiq-add-atm-hack.patch deleted file mode 100644 index 2e36b41beb8..00000000000 --- a/target/linux/lantiq/patches-6.12/004-MIPS-lantiq-add-atm-hack.patch +++ /dev/null @@ -1,482 +0,0 @@ -From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 3 Aug 2012 10:27:25 +0200 -Subject: [PATCH 04/36] MIPS: lantiq: add atm hack - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ - arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ - arch/mips/lantiq/irq.c | 2 + - arch/mips/mm/cache.c | 4 + - include/uapi/linux/atm.h | 6 + - net/atm/common.c | 6 + - net/atm/proc.c | 2 +- - 7 files changed, 416 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h -@@ -0,0 +1,196 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_atm.h -+** PROJECT : UEIP -+** MODULES : ATM -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global ATM driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_ATM_H -+#define IFX_ATM_H -+ -+ -+ -+/*! -+ \defgroup IFX_ATM UEIP Project - ATM driver module -+ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_ATM_IOCTL IOCTL Commands -+ \ingroup IFX_ATM -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_ATM_STRUCT Structures -+ \ingroup IFX_ATM -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_atm.h -+ \ingroup IFX_ATM -+ \brief ATM driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_ATM_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * ATM MIB -+ */ -+ -+/*! -+ \struct atm_cell_ifEntry_t -+ \brief Structure used for Cell Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". -+ */ -+typedef struct { -+ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ -+ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ -+ __u32 ifInErrors; /*!< counter of error ingress cells */ -+ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ -+ __u32 ifOutErrors; /*!< counter of error egress cells */ -+} atm_cell_ifEntry_t; -+ -+/*! -+ \struct atm_aal5_ifEntry_t -+ \brief Structure used for AAL5 Frame Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". -+ */ -+typedef struct { -+ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ -+ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ -+ __u32 ifInUcastPkts; /*!< counter of ingress packets */ -+ __u32 ifOutUcastPkts; /*!< counter of egress packets */ -+ __u32 ifInErrors; /*!< counter of error ingress packets */ -+ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ -+ __u32 ifOutErros; /*!< counter of error egress packets */ -+ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ -+} atm_aal5_ifEntry_t; -+ -+/*! -+ \struct atm_aal5_vcc_t -+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. -+ -+ This structure is a part of structure "atm_aal5_vcc_x_t". -+ */ -+typedef struct { -+ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ -+ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet -+ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ -+} atm_aal5_vcc_t; -+ -+/*! -+ \struct atm_aal5_vcc_x_t -+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". -+ */ -+typedef struct { -+ int vpi; /*!< VPI of the VCC to get MIB counters */ -+ int vci; /*!< VCI of the VCC to get MIB counters */ -+ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ -+} atm_aal5_vcc_x_t; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_ATM_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+/*! -+ \brief ATM IOCTL Magic Number -+ */ -+#define PPE_ATM_IOC_MAGIC 'o' -+/*! -+ \brief ATM IOCTL Command - Get Cell Level MIB Counters -+ -+ This command is obsolete. User can get cell level MIB from DSL API. -+ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. -+ */ -+#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) -+/*! -+ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters -+ -+ Get AAL5 packet counters. -+ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. -+ */ -+#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) -+/*! -+ \brief ATM IOCTL Command - Get Per PVC MIB Counters -+ -+ Get AAL5 packet counters for each PVC. -+ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. -+ */ -+#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) -+/*! -+ \brief Total Number of ATM IOCTL Commands -+ */ -+#define PPE_ATM_IOC_MAXNR 3 -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+struct port_cell_info { -+ unsigned int port_num; -+ unsigned int tx_link_rate[2]; -+}; -+#endif -+ -+ -+ -+#endif // IFX_ATM_H -+ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h -@@ -0,0 +1,203 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_ptm.h -+** PROJECT : UEIP -+** MODULES : PTM -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global PTM driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_PTM_H -+#define IFX_PTM_H -+ -+ -+ -+/*! -+ \defgroup IFX_PTM UEIP Project - PTM driver module -+ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_PTM_IOCTL IOCTL Commands -+ \ingroup IFX_PTM -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_PTM_STRUCT Structures -+ \ingroup IFX_PTM -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_ptm.h -+ \ingroup IFX_PTM -+ \brief PTM driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_PTM_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+/*! -+ \brief PTM IOCTL Command - Get codeword MIB counters. -+ -+ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. -+ */ -+#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 -+/*! -+ \brief PTM IOCTL Command - Get packet MIB counters. -+ -+ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. -+ */ -+#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 -+/*! -+ \brief PTM IOCTL Command - Get firmware configuration (CRC). -+ -+ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). -+ */ -+#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 -+/*! -+ \brief PTM IOCTL Command - Set firmware configuration (CRC). -+ -+ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). -+ */ -+#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 -+/*! -+ \brief PTM IOCTL Command - Program priority value to TX queue mapping. -+ -+ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. -+ */ -+#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 -+ -+/*@}*/ -+ -+ -+/*! -+ \addtogroup IFX_PTM_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Data Type -+ */ -+ -+/*! -+ \typedef PTM_CW_IF_ENTRY_T -+ \brief Wrapping of structure "ptm_cw_ifEntry_t". -+ */ -+/*! -+ \struct ptm_cw_ifEntry_t -+ \brief Structure used for CodeWord level MIB counters. -+ */ -+typedef struct ptm_cw_ifEntry_t { -+ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ -+ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ -+ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ -+ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ -+ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ -+} PTM_CW_IF_ENTRY_T; -+ -+/*! -+ \typedef PTM_FRAME_MIB_T -+ \brief Wrapping of structure "ptm_frame_mib_t". -+ */ -+/*! -+ \struct ptm_frame_mib_t -+ \brief Structure used for packet level MIB counters. -+ */ -+typedef struct ptm_frame_mib_t { -+ uint32_t RxCorrect; /*!< output, number of ingress packet */ -+ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ -+ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ -+ uint32_t TxSend; /*!< output, number of egress packet */ -+} PTM_FRAME_MIB_T; -+ -+/*! -+ \typedef IFX_PTM_CFG_T -+ \brief Wrapping of structure "ptm_cfg_t". -+ */ -+/*! -+ \struct ptm_cfg_t -+ \brief Structure used for ETH/TC CRC configuration. -+ */ -+typedef struct ptm_cfg_t { -+ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ -+ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ -+ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ -+ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ -+ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ -+ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ -+ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ -+} IFX_PTM_CFG_T; -+ -+/*! -+ \typedef IFX_PTM_PRIO_Q_MAP_T -+ \brief Wrapping of structure "ppe_prio_q_map". -+ */ -+/*! -+ \struct ppe_prio_q_map -+ \brief Structure used for Priority Value to TX Queue mapping. -+ */ -+typedef struct ppe_prio_q_map { -+ int pkt_prio; -+ int qid; -+ int vpi; // ignored in eth interface -+ int vci; // ignored in eth interface -+} IFX_PTM_PRIO_Q_MAP_T; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+struct port_cell_info { -+ unsigned int port_num; -+ unsigned int tx_link_rate[2]; -+}; -+#endif -+ -+ -+ -+#endif // IFX_PTM_H -+ ---- a/arch/mips/lantiq/irq.c -+++ b/arch/mips/lantiq/irq.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -92,6 +93,7 @@ void ltq_disable_irq(struct irq_data *d) - } - raw_spin_unlock_irqrestore(<q_icu_lock, flags); - } -+EXPORT_SYMBOL(ltq_mask_and_ack_irq); - - void ltq_mask_and_ack_irq(struct irq_data *d) - { ---- a/arch/mips/mm/cache.c -+++ b/arch/mips/mm/cache.c -@@ -80,6 +80,10 @@ void (*_dma_cache_wback_inv)(unsigned lo - void (*_dma_cache_wback)(unsigned long start, unsigned long size); - void (*_dma_cache_inv)(unsigned long start, unsigned long size); - -+EXPORT_SYMBOL(_dma_cache_wback_inv); -+EXPORT_SYMBOL(_dma_cache_wback); -+EXPORT_SYMBOL(_dma_cache_inv); -+ - #endif /* CONFIG_DMA_NONCOHERENT */ - - /* ---- a/include/uapi/linux/atm.h -+++ b/include/uapi/linux/atm.h -@@ -131,8 +131,14 @@ - #define ATM_ABR 4 - #define ATM_ANYCLASS 5 /* compatible with everything */ - -+#define ATM_VBR_NRT ATM_VBR -+#define ATM_VBR_RT 6 -+#define ATM_UBR_PLUS 7 -+#define ATM_GFR 8 -+ - #define ATM_MAX_PCR -1 /* maximum available PCR */ - -+ - struct atm_trafprm { - unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ - int max_pcr; /* maximum PCR in cells per second */ ---- a/net/atm/proc.c -+++ b/net/atm/proc.c -@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil - static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) - { - static const char *const class_name[] = { -- "off", "UBR", "CBR", "VBR", "ABR"}; -+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; - static const char *const aal_name[] = { - "---", "1", "2", "3/4", /* 0- 3 */ - "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/lantiq/patches-6.12/008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-6.12/008-MIPS-lantiq-backport-old-timer-code.patch deleted file mode 100644 index a976df93d7f..00000000000 --- a/target/linux/lantiq/patches-6.12/008-MIPS-lantiq-backport-old-timer-code.patch +++ /dev/null @@ -1,1079 +0,0 @@ -From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:30:56 +0200 -Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ - arch/mips/lantiq/xway/Makefile | 2 +- - arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ - 3 files changed, 1001 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h - create mode 100644 arch/mips/lantiq/xway/timer.c - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h -@@ -0,0 +1,155 @@ -+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -+ -+ -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/* -+ * Available Timer/Counter Index -+ */ -+#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) -+#define TIMER_ANY 0x00 -+#define TIMER1A TIMER(1, 0) -+#define TIMER1B TIMER(1, 1) -+#define TIMER2A TIMER(2, 0) -+#define TIMER2B TIMER(2, 1) -+#define TIMER3A TIMER(3, 0) -+#define TIMER3B TIMER(3, 1) -+ -+/* -+ * Flag of Timer/Counter -+ * These flags specify the way in which timer is configured. -+ */ -+/* Bit size of timer/counter. */ -+#define TIMER_FLAG_16BIT 0x0000 -+#define TIMER_FLAG_32BIT 0x0001 -+/* Switch between timer and counter. */ -+#define TIMER_FLAG_TIMER 0x0000 -+#define TIMER_FLAG_COUNTER 0x0002 -+/* Stop or continue when overflowing/underflowing. */ -+#define TIMER_FLAG_ONCE 0x0000 -+#define TIMER_FLAG_CYCLIC 0x0004 -+/* Count up or counter down. */ -+#define TIMER_FLAG_UP 0x0000 -+#define TIMER_FLAG_DOWN 0x0008 -+/* Count on specific level or edge. */ -+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 -+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 -+#define TIMER_FLAG_RISE_EDGE 0x0010 -+#define TIMER_FLAG_FALL_EDGE 0x0020 -+#define TIMER_FLAG_ANY_EDGE 0x0030 -+/* Signal is syncronous to module clock or not. */ -+#define TIMER_FLAG_UNSYNC 0x0000 -+#define TIMER_FLAG_SYNC 0x0080 -+/* Different interrupt handle type. */ -+#define TIMER_FLAG_NO_HANDLE 0x0000 -+#if defined(__KERNEL__) -+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 -+#endif // defined(__KERNEL__) -+#define TIMER_FLAG_SIGNAL 0x0300 -+/* Internal clock source or external clock source */ -+#define TIMER_FLAG_INT_SRC 0x0000 -+#define TIMER_FLAG_EXT_SRC 0x1000 -+ -+ -+/* -+ * ioctl Command -+ */ -+#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ -+#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ -+#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ -+#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ -+#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ -+#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ -+#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ -+#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ -+ -+/* -+ * Data Type Used to Call ioctl -+ */ -+struct gptu_ioctl_param { -+ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * -+ * GPTU_SET_COUNTER, this field is ID of expected * -+ * timer/counter. If it's zero, a timer/counter would * -+ * be dynamically allocated and ID would be stored in * -+ * this field. * -+ * In command GPTU_GET_COUNT_VALUE, this field is * -+ * ignored. * -+ * In other command, this field is ID of timer/counter * -+ * allocated. */ -+ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * -+ * GPTU_SET_COUNTER, this field contains flags to * -+ * specify how to configure timer/counter. * -+ * In command GPTU_START_TIMER, zero indicate start * -+ * and non-zero indicate resume timer/counter. * -+ * In other command, this field is ignored. */ -+ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * -+ * init/reload value. * -+ * In command GPTU_SET_TIMER, this field contains * -+ * frequency (0.001Hz) of timer. * -+ * In command GPTU_GET_COUNT_VALUE, current count * -+ * value would be stored in this field. * -+ * In command GPTU_CALCULATE_DIVIDER, this field * -+ * contains frequency wanted, and after calculation, * -+ * divider would be stored in this field to overwrite * -+ * the frequency. * -+ * In other command, this field is ignored. */ -+ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * -+ * if signal is required, this field contains process * -+ * ID to which signal would be sent. * -+ * In other command, this field is ignored. */ -+ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * -+ * if signal is required, this field contains signal * -+ * number which would be sent. * -+ * In other command, this field is ignored. */ -+}; -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+typedef void (*timer_callback)(unsigned long arg); -+ -+extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); -+extern int lq_free_timer(unsigned int); -+extern int lq_start_timer(unsigned int, int); -+extern int lq_stop_timer(unsigned int); -+extern int lq_reset_counter_flags(u32 timer, u32 flags); -+extern int lq_get_count_value(unsigned int, unsigned long *); -+extern u32 lq_cal_divider(unsigned long); -+extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); -+extern int lq_set_counter(unsigned int timer, unsigned int flag, -+ u32 reload, unsigned long arg1, unsigned long arg2); -+ -+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -1,4 +1,10 @@ - # SPDX-License-Identifier: GPL-2.0-only --obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o -+obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o -+ -+ifdef CONFIG_SOC_AMAZON_SE -+obj-y += gptu.o -+else -+obj-y += timer.o -+endif - - obj-y += vmmc.o ---- /dev/null -+++ b/arch/mips/lantiq/xway/timer.c -@@ -0,0 +1,890 @@ -+#ifndef CONFIG_SOC_AMAZON_SE -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include "../clk.h" -+ -+#include -+#include -+#include -+ -+#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 -+ -+#ifdef TIMER1A -+#define FIRST_TIMER TIMER1A -+#else -+#define FIRST_TIMER 2 -+#endif -+ -+/* -+ * GPTC divider is set or not. -+ */ -+#define GPTU_CLC_RMC_IS_SET 0 -+ -+/* -+ * Timer Interrupt (IRQ) -+ */ -+/* Must be adjusted when ICU driver is available */ -+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) -+ -+/* -+ * Bits Operation -+ */ -+#define GET_BITS(x, msb, lsb) \ -+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -+#define SET_BITS(x, msb, lsb, value) \ -+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ -+ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) -+ -+/* -+ * GPTU Register Mapping -+ */ -+#define LQ_GPTU (KSEG1 + 0x1E100A00) -+#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) -+#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) -+#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) -+#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) -+#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) -+ -+/* -+ * Clock Control Register -+ */ -+#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) -+#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) -+#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) -+#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) -+#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) -+#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) -+#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) -+ -+#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) -+#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) -+#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) -+#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) -+#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) -+#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) -+ -+/* -+ * ID Register -+ */ -+#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) -+#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) -+#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) -+ -+/* -+ * Control Register of Timer/Counter nX -+ * n is the index of block (1 based index) -+ * X is either A or B -+ */ -+#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) -+#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) -+#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) -+#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) -+#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) -+#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ -+#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) -+#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) -+#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) -+#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) -+ -+#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) -+#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) -+#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) -+#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) -+#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) -+#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) -+#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) -+#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) -+ -+#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) -+#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) -+ -+#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -+#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -+ -+#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) -+#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) -+#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) -+#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) -+#define TIMER_FLAG_NONE_EDGE 0x0000 -+#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) -+#define TIMER_FLAG_REAL 0x0000 -+#define TIMER_FLAG_INVERT 0x0040 -+#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) -+#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) -+#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) -+#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 -+#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) -+#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) -+ -+struct timer_dev_timer { -+ unsigned int f_irq_on; -+ unsigned int irq; -+ unsigned int flag; -+ unsigned long arg1; -+ unsigned long arg2; -+}; -+ -+struct timer_dev { -+ struct mutex gptu_mutex; -+ unsigned int number_of_timers; -+ unsigned int occupation; -+ unsigned int f_gptu_on; -+ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; -+}; -+ -+ -+static unsigned int ltq_get_fpi_bus_clock(int fpi) { -+ struct clk *clk = clk_get_fpi(); -+ return clk_get_rate(clk); -+} -+ -+ -+static long gptu_ioctl(struct file *, unsigned int, unsigned long); -+static int gptu_open(struct inode *, struct file *); -+static int gptu_release(struct inode *, struct file *); -+ -+static struct file_operations gptu_fops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = gptu_ioctl, -+ .open = gptu_open, -+ .release = gptu_release -+}; -+ -+static struct miscdevice gptu_miscdev = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = "gptu", -+ .fops = &gptu_fops, -+}; -+ -+static struct timer_dev timer_dev; -+ -+static irqreturn_t timer_irq_handler(int irq, void *p) -+{ -+ unsigned int timer; -+ unsigned int flag; -+ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; -+ -+ timer = irq - TIMER_INTERRUPT; -+ if (timer < timer_dev.number_of_timers -+ && dev_timer == &timer_dev.timer[timer]) { -+ /* Clear interrupt. */ -+ ltq_w32(1 << timer, LQ_GPTU_IRNCR); -+ -+ /* Call user hanler or signal. */ -+ flag = dev_timer->flag; -+ if (!(timer & 0x01) -+ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { -+ /* 16-bit timer or timer A of 32-bit timer */ -+ switch (TIMER_FLAG_MASK_HANDLE(flag)) { -+ case TIMER_FLAG_CALLBACK_IN_IRQ: -+ case TIMER_FLAG_CALLBACK_IN_HB: -+ if (dev_timer->arg1) -+ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); -+ break; -+ case TIMER_FLAG_SIGNAL: -+ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); -+ break; -+ } -+ } -+ } -+ return IRQ_HANDLED; -+} -+ -+static inline void lq_enable_gptu(void) -+{ -+ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); -+ clk_enable(clk); -+ -+ //ltq_pmu_enable(PMU_GPT); -+ -+ /* Set divider as 1, disable write protection for SPEN, enable module. */ -+ *LQ_GPTU_CLC = -+ GPTU_CLC_SMC_SET(0x00) | -+ GPTU_CLC_RMC_SET(0x01) | -+ GPTU_CLC_FSOE_SET(0) | -+ GPTU_CLC_SBWE_SET(1) | -+ GPTU_CLC_EDIS_SET(0) | -+ GPTU_CLC_SPEN_SET(0) | -+ GPTU_CLC_DISR_SET(0); -+} -+ -+static inline void lq_disable_gptu(void) -+{ -+ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); -+ ltq_w32(0x00, LQ_GPTU_IRNEN); -+ ltq_w32(0xfff, LQ_GPTU_IRNCR); -+ -+ /* Set divider as 0, enable write protection for SPEN, disable module. */ -+ *LQ_GPTU_CLC = -+ GPTU_CLC_SMC_SET(0x00) | -+ GPTU_CLC_RMC_SET(0x00) | -+ GPTU_CLC_FSOE_SET(0) | -+ GPTU_CLC_SBWE_SET(0) | -+ GPTU_CLC_EDIS_SET(0) | -+ GPTU_CLC_SPEN_SET(0) | -+ GPTU_CLC_DISR_SET(1); -+ -+ clk_enable(clk); -+} -+ -+int lq_request_timer(unsigned int timer, unsigned int flag, -+ unsigned long value, unsigned long arg1, unsigned long arg2) -+{ -+ int ret = 0; -+ unsigned int con_reg, irnen_reg; -+ int n, X; -+ -+ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", -+ timer, flag, value); -+ -+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) -+ value &= 0xFFFF; -+ else -+ timer &= ~0x01; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ /* -+ * Allocate timer. -+ */ -+ if (timer < FIRST_TIMER) { -+ unsigned int mask; -+ unsigned int shift; -+ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ -+ unsigned int offset = TIMER2A; -+ -+ /* -+ * Pick up a free timer. -+ */ -+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { -+ mask = 1 << offset; -+ shift = 1; -+ } else { -+ mask = 3 << offset; -+ shift = 2; -+ } -+ for (timer = offset; -+ timer < offset + timer_dev.number_of_timers; -+ timer += shift, mask <<= shift) -+ if (!(timer_dev.occupation & mask)) { -+ timer_dev.occupation |= mask; -+ break; -+ } -+ if (timer >= offset + timer_dev.number_of_timers) { -+ printk("failed![%d]\n", __LINE__); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } else -+ ret = timer; -+ } else { -+ register unsigned int mask; -+ -+ /* -+ * Check if the requested timer is free. -+ */ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if ((timer_dev.occupation & mask)) { -+ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", -+ __LINE__, mask, timer_dev.occupation); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EBUSY; -+ } else { -+ timer_dev.occupation |= mask; -+ ret = 0; -+ } -+ } -+ -+ /* -+ * Prepare control register value. -+ */ -+ switch (TIMER_FLAG_MASK_EDGE(flag)) { -+ default: -+ case TIMER_FLAG_NONE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x00); -+ break; -+ case TIMER_FLAG_RISE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x01); -+ break; -+ case TIMER_FLAG_FALL_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x02); -+ break; -+ case TIMER_FLAG_ANY_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x03); -+ break; -+ } -+ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) -+ con_reg |= -+ TIMER_FLAG_MASK_SRC(flag) == -+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : -+ GPTU_CON_SRC_EXT_SET(0); -+ else -+ con_reg |= -+ TIMER_FLAG_MASK_SRC(flag) == -+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : -+ GPTU_CON_SRC_EG_SET(0); -+ con_reg |= -+ TIMER_FLAG_MASK_SYNC(flag) == -+ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : -+ GPTU_CON_SYNC_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_INVERT(flag) == -+ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_SIZE(flag) == -+ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : -+ GPTU_CON_EXT_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_STOP(flag) == -+ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); -+ con_reg |= -+ TIMER_FLAG_MASK_TYPE(flag) == -+ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : -+ GPTU_CON_CNT_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_DIR(flag) == -+ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); -+ -+ /* -+ * Fill up running data. -+ */ -+ timer_dev.timer[timer - FIRST_TIMER].flag = flag; -+ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; -+ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; -+ -+ /* -+ * Enable GPTU module. -+ */ -+ if (!timer_dev.f_gptu_on) { -+ lq_enable_gptu(); -+ timer_dev.f_gptu_on = 1; -+ } -+ -+ /* -+ * Enable IRQ. -+ */ -+ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { -+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) -+ timer_dev.timer[timer - FIRST_TIMER].arg1 = -+ (unsigned long) find_task_by_vpid((int) arg1); -+ -+ irnen_reg = 1 << (timer - FIRST_TIMER); -+ -+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL -+ || (TIMER_FLAG_MASK_HANDLE(flag) == -+ TIMER_FLAG_CALLBACK_IN_IRQ -+ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { -+ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); -+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; -+ } -+ } else -+ irnen_reg = 0; -+ -+ /* -+ * Write config register, reload value and enable interrupt. -+ */ -+ n = timer >> 1; -+ X = timer & 0x01; -+ *LQ_GPTU_CON(n, X) = con_reg; -+ *LQ_GPTU_RELOAD(n, X) = value; -+ /* printk("reload value = %d\n", (u32)value); */ -+ *LQ_GPTU_IRNEN |= irnen_reg; -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ printk("successful!\n"); -+ return ret; -+} -+EXPORT_SYMBOL(lq_request_timer); -+ -+int lq_free_timer(unsigned int timer) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ if (GPTU_CON_EN(n, X)) -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); -+ -+ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); -+ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); -+ -+ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { -+ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); -+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; -+ } -+ -+ timer_dev.occupation &= ~mask; -+ if (!timer_dev.occupation && timer_dev.f_gptu_on) { -+ lq_disable_gptu(); -+ timer_dev.f_gptu_on = 0; -+ } -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_free_timer); -+ -+int lq_start_timer(unsigned int timer, int is_resume) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == -+ TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); -+ -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_start_timer); -+ -+int lq_stop_timer(unsigned int timer) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER -+ || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_stop_timer); -+ -+int lq_reset_counter_flags(u32 timer, u32 flags) -+{ -+ unsigned int oflag; -+ unsigned int mask, con_reg; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ switch (TIMER_FLAG_MASK_EDGE(flags)) { -+ default: -+ case TIMER_FLAG_NONE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x00); -+ break; -+ case TIMER_FLAG_RISE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x01); -+ break; -+ case TIMER_FLAG_FALL_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x02); -+ break; -+ case TIMER_FLAG_ANY_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x03); -+ break; -+ } -+ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) -+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); -+ else -+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); -+ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); -+ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); -+ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); -+ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); -+ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); -+ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); -+ -+ timer_dev.timer[timer - FIRST_TIMER].flag = flags; -+ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) -+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_CON(n, X) = con_reg; -+ smp_wmb(); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return 0; -+} -+EXPORT_SYMBOL(lq_reset_counter_flags); -+ -+int lq_get_count_value(unsigned int timer, unsigned long *value) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER -+ || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *value = *LQ_GPTU_COUNT(n, X); -+ -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_get_count_value); -+ -+u32 lq_cal_divider(unsigned long freq) -+{ -+ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); -+ u32 clock_divider = 1; -+ module_freq = fpi * 1000; -+ do_div(module_freq, clock_divider * freq); -+ return module_freq; -+} -+EXPORT_SYMBOL(lq_cal_divider); -+ -+int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, -+ int is_ext_src, unsigned int handle_flag, unsigned long arg1, -+ unsigned long arg2) -+{ -+ unsigned long divider; -+ unsigned int flag; -+ -+ divider = lq_cal_divider(freq); -+ if (divider == 0) -+ return -EINVAL; -+ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) -+ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) -+ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) -+ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN -+ | TIMER_FLAG_MASK_HANDLE(handle_flag); -+ -+ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", -+ timer, freq, divider); -+ return lq_request_timer(timer, flag, divider, arg1, arg2); -+} -+EXPORT_SYMBOL(lq_set_timer); -+ -+int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, -+ unsigned long arg1, unsigned long arg2) -+{ -+ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); -+ return lq_request_timer(timer, flag, reload, arg1, arg2); -+} -+EXPORT_SYMBOL(lq_set_counter); -+ -+static long gptu_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ int ret; -+ struct gptu_ioctl_param param; -+ -+ if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param))) -+ return -EFAULT; -+ if (copy_from_user(¶m, (void __user *)arg, sizeof(param))) -+ return -EFAULT; -+ -+ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER -+ || GPTU_SET_COUNTER) && param.timer < 2) -+ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) -+ && !access_ok((void __user *)arg, -+ sizeof(struct gptu_ioctl_param))) -+ return -EFAULT; -+ -+ switch (cmd) { -+ case GPTU_REQUEST_TIMER: -+ ret = lq_request_timer(param.timer, param.flag, param.value, -+ (unsigned long) param.pid, -+ (unsigned long) param.sig); -+ if (ret > 0) { -+ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret))) -+ ret = -EFAULT; -+ else -+ ret = 0; -+ } -+ break; -+ case GPTU_FREE_TIMER: -+ ret = lq_free_timer(param.timer); -+ break; -+ case GPTU_START_TIMER: -+ ret = lq_start_timer(param.timer, param.flag); -+ break; -+ case GPTU_STOP_TIMER: -+ ret = lq_stop_timer(param.timer); -+ break; -+ case GPTU_GET_COUNT_VALUE: -+ ret = lq_get_count_value(param.timer, ¶m.value); -+ if (!ret && copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value,sizeof(param.value))) -+ ret = -EFAULT; -+ break; -+ case GPTU_CALCULATE_DIVIDER: -+ param.value = lq_cal_divider(param.value); -+ if (param.value == 0) -+ ret = -EINVAL; -+ else if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value, -+ sizeof(param.value))) -+ ret = -EFAULT; -+ else -+ ret = 0; -+ break; -+ case GPTU_SET_TIMER: -+ ret = lq_set_timer(param.timer, param.value, -+ TIMER_FLAG_MASK_STOP(param.flag) != -+ TIMER_FLAG_ONCE ? 1 : 0, -+ TIMER_FLAG_MASK_SRC(param.flag) == -+ TIMER_FLAG_EXT_SRC ? 1 : 0, -+ TIMER_FLAG_MASK_HANDLE(param.flag) == -+ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : -+ TIMER_FLAG_NO_HANDLE, -+ (unsigned long) param.pid, -+ (unsigned long) param.sig); -+ if (ret > 0) { -+ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret))) -+ ret = -EFAULT; -+ else -+ ret = 0; -+ } -+ break; -+ case GPTU_SET_COUNTER: -+ lq_set_counter(param.timer, param.flag, param.value, 0, 0); -+ if (ret > 0) { -+ if (copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret))) -+ ret = -EFAULT; -+ else -+ ret = 0; -+ } -+ break; -+ default: -+ ret = -ENOTTY; -+ } -+ -+ return ret; -+} -+ -+static int gptu_open(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+static int gptu_release(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+static int gptu_probe(struct platform_device *pdev) -+{ -+ int ret; -+ int i; -+ -+ ltq_w32(0, LQ_GPTU_IRNEN); -+ ltq_w32(0xfff, LQ_GPTU_IRNCR); -+ -+ memset(&timer_dev, 0, sizeof(timer_dev)); -+ ret = devm_mutex_init(&pdev->dev, &timer_dev.gptu_mutex); -+ if (ret) -+ return ret; -+ -+ lq_enable_gptu(); -+ timer_dev.number_of_timers = GPTU_ID_CFG * 2; -+ lq_disable_gptu(); -+ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) -+ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; -+ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); -+ -+ ret = misc_register(&gptu_miscdev); -+ if (ret) { -+ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); -+ return ret; -+ } else { -+ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); -+ } -+ -+ for (i = 0; i < timer_dev.number_of_timers; i++) { -+ int irq = platform_get_irq(pdev, i); -+ if (irq < 0) { -+ printk(KERN_ERR "gptu: failed in getting irq (%d), get error %d\n", i, irq); -+ for (i--; i >= 0; i--) -+ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); -+ misc_deregister(&gptu_miscdev); -+ return irq; -+ } -+ -+ ret = request_irq(irq, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); -+ if (ret) { -+ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); -+ for (i--; i >= 0; i--) -+ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); -+ misc_deregister(&gptu_miscdev); -+ return ret; -+ } else { -+ timer_dev.timer[i].irq = irq; -+ disable_irq(timer_dev.timer[i].irq); -+ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); -+ } -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id gptu_match[] = { -+ { .compatible = "lantiq,gptu-xway" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, gptu_match); -+ -+static struct platform_driver gptu_driver = { -+ .probe = gptu_probe, -+ .driver = { -+ .name = "gptu-xway", -+ .of_match_table = gptu_match, -+ }, -+}; -+ -+static int __init lq_gptu_init(void) -+{ -+ int ret = platform_driver_register(&gptu_driver); -+ -+ if (ret) -+ pr_info("gptu: Error registering platform driver\n"); -+ return ret; -+} -+ -+static void __exit lq_gptu_exit(void) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < timer_dev.number_of_timers; i++) { -+ if (timer_dev.timer[i].f_irq_on) -+ disable_irq(timer_dev.timer[i].irq); -+ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); -+ } -+ lq_disable_gptu(); -+ misc_deregister(&gptu_miscdev); -+} -+ -+module_init(lq_gptu_init); -+module_exit(lq_gptu_exit); -+ -+#endif diff --git a/target/linux/lantiq/patches-6.12/018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-6.12/018-MTD-nand-lots-of-xrx200-fixes.patch deleted file mode 100644 index f420d8cde5f..00000000000 --- a/target/linux/lantiq/patches-6.12/018-MTD-nand-lots-of-xrx200-fixes.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 9 Sep 2014 23:12:15 +0200 -Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes - -Signed-off-by: John Crispin ---- - drivers/mtd/nand/raw/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 63 insertions(+) - ---- a/drivers/mtd/nand/raw/xway_nand.c -+++ b/drivers/mtd/nand/raw/xway_nand.c -@@ -61,6 +61,24 @@ - #define NAND_CON_CSMUX (1 << 1) - #define NAND_CON_NANDM 1 - -+#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr)) -+#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) -+#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080) -+ -+/* -+ * req_mask provides a mechanism to prevent interference between -+ * nand and pci (probably only relevant for the BT Home Hub 2B). -+ * Setting it causes the corresponding pci req pins to be masked -+ * during nand access, and also moves ebu locking from the read/write -+ * functions to the chip select function to ensure that the whole -+ * operation runs with interrupts disabled. -+ * In addition it switches on some extra waiting in xway_cmd_ctrl(). -+ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled, -+ * which in turn seems to be necessary for the nor chip to be recognised -+ * reliably, on a board (Home Hub 2B again) which has both nor and nand. -+ */ -+static __be32 req_mask = 0; -+ - struct xway_nand_data { - struct nand_controller controller; - struct nand_chip chip; -@@ -92,10 +110,22 @@ static void xway_select_chip(struct nand - case -1: - ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); - ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); -+ -+ if (req_mask) { -+ /* Unmask all external PCI request */ -+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16); -+ } -+ - spin_unlock_irqrestore(&ebu_lock, data->csflags); - break; - case 0: - spin_lock_irqsave(&ebu_lock, data->csflags); -+ -+ if (req_mask) { -+ /* Mask all external PCI request */ -+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16); -+ } -+ - ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); - ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); - break; -@@ -108,6 +138,11 @@ static void xway_cmd_ctrl(struct nand_ch - { - struct mtd_info *mtd = nand_to_mtd(chip); - -+ if (req_mask) { -+ if (cmd != NAND_CMD_STATUS) -+ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */ -+ } -+ - if (cmd == NAND_CMD_NONE) - return; - -@@ -118,6 +153,24 @@ static void xway_cmd_ctrl(struct nand_ch - - while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) - ; -+ -+ if (req_mask) { -+ /* -+ * program and erase have their own busy handlers -+ * status and sequential in needs no delay -+ */ -+ switch (cmd) { -+ case NAND_CMD_ERASE1: -+ case NAND_CMD_SEQIN: -+ case NAND_CMD_STATUS: -+ case NAND_CMD_READID: -+ return; -+ } -+ -+ /* wait until command is processed */ -+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) -+ ; -+ } - } - - static int xway_dev_ready(struct nand_chip *chip) -@@ -169,6 +222,7 @@ static int xway_nand_probe(struct platfo - int err; - u32 cs; - u32 cs_flag = 0; -+ const __be32 *req_mask_ptr; - - /* Allocate memory for the device structure (and zero it) */ - data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), -@@ -204,6 +258,15 @@ static int xway_nand_probe(struct platfo - if (!err && cs == 1) - cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; - -+ req_mask_ptr = of_get_property(pdev->dev.of_node, -+ "req-mask", NULL); -+ -+ /* -+ * Load the PCI req lines to mask from the device tree. If the -+ * property is not present, setting req_mask to 0 disables masking. -+ */ -+ req_mask = (req_mask_ptr ? *req_mask_ptr : 0); -+ - /* setup the EBU to run in NAND mode on our base addr */ - ltq_ebu_w32(CPHYSADDR(data->nandaddr) - | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); diff --git a/target/linux/lantiq/patches-6.12/020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-6.12/020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch deleted file mode 100644 index 847d54caadd..00000000000 --- a/target/linux/lantiq/patches-6.12/020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch +++ /dev/null @@ -1,25 +0,0 @@ -From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:18:00 +0200 -Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash - -Signed-off-by: John Crispin ---- - drivers/mtd/maps/lantiq-flash.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/maps/lantiq-flash.c -+++ b/drivers/mtd/maps/lantiq-flash.c -@@ -127,7 +127,11 @@ ltq_mtd_probe(struct platform_device *pd - if (!ltq_mtd->map) - return -ENOMEM; - -- ltq_mtd->map->phys = ltq_mtd->res->start; -+ if (of_property_present(pdev->dev.of_node, "lantiq,noxip")) -+ ltq_mtd->map->phys = NO_XIP; -+ else -+ ltq_mtd->map->phys = ltq_mtd->res->start; -+ ltq_mtd->res->start; - ltq_mtd->map->size = resource_size(ltq_mtd->res); - - ltq_mtd->map->name = ltq_map_name; diff --git a/target/linux/lantiq/patches-6.12/028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-6.12/028-NET-lantiq-various-etop-fixes.patch deleted file mode 100644 index 7987e87dffd..00000000000 --- a/target/linux/lantiq/patches-6.12/028-NET-lantiq-various-etop-fixes.patch +++ /dev/null @@ -1,896 +0,0 @@ -From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 9 Sep 2014 22:45:34 +0200 -Subject: [PATCH 28/36] NET: lantiq: various etop fixes - -Signed-off-by: John Crispin ---- - drivers/net/ethernet/lantiq_etop.c | 534 ++++++++++++++++++++--------- - 1 file changed, 379 insertions(+), 155 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -1,7 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* - * -- * Copyright (C) 2011 John Crispin -+ * Copyright (C) 2011-12 John Crispin - */ - - #include -@@ -20,12 +20,16 @@ - #include - #include - #include -+#include - #include - #include - #include - #include - #include - #include -+#include -+#include -+#include - - #include - -@@ -33,7 +37,7 @@ - #include - #include - --#define LTQ_ETOP_MDIO 0x11804 -+#define LTQ_ETOP_MDIO_ACC 0x11804 - #define MDIO_REQUEST 0x80000000 - #define MDIO_READ 0x40000000 - #define MDIO_ADDR_MASK 0x1f -@@ -42,44 +46,91 @@ - #define MDIO_REG_OFFSET 0x10 - #define MDIO_VAL_MASK 0xffff - --#define PPE32_CGEN 0x800 --#define LQ_PPE32_ENET_MAC_CFG 0x1840 -+#define LTQ_ETOP_MDIO_CFG 0x11800 -+#define MDIO_CFG_MASK 0x6 -+ -+#define LTQ_ETOP_CFG 0x11808 -+#define LTQ_ETOP_IGPLEN 0x11820 -+#define LTQ_ETOP_MAC_CFG 0x11840 - - #define LTQ_ETOP_ENETS0 0x11850 - #define LTQ_ETOP_MAC_DA0 0x1186C - #define LTQ_ETOP_MAC_DA1 0x11870 --#define LTQ_ETOP_CFG 0x16020 --#define LTQ_ETOP_IGPLEN 0x16080 -+ -+#define MAC_CFG_MASK 0xfff -+#define MAC_CFG_CGEN BIT(11) -+#define MAC_CFG_DUPLEX BIT(2) -+#define MAC_CFG_SPEED BIT(1) -+#define MAC_CFG_LINK BIT(0) - - #define MAX_DMA_CHAN 0x8 - #define MAX_DMA_CRC_LEN 0x4 - #define MAX_DMA_DATA_LEN 0x600 - - #define ETOP_FTCU BIT(28) --#define ETOP_MII_MASK 0xf --#define ETOP_MII_NORMAL 0xd --#define ETOP_MII_REVERSE 0xe - #define ETOP_PLEN_UNDER 0x40 --#define ETOP_CGEN 0x800 -+#define ETOP_CFG_MII0 0x01 - --/* use 2 static channels for TX/RX */ --#define LTQ_ETOP_TX_CHANNEL 1 --#define LTQ_ETOP_RX_CHANNEL 6 --#define IS_TX(x) ((x) == LTQ_ETOP_TX_CHANNEL) --#define IS_RX(x) ((x) == LTQ_ETOP_RX_CHANNEL) -+#define ETOP_CFG_MASK 0xfff -+#define ETOP_CFG_FEN0 BIT(8) -+#define ETOP_CFG_SEN0 BIT(6) -+#define ETOP_CFG_OFF1 BIT(3) -+#define ETOP_CFG_REMII0 BIT(1) -+#define ETOP_CFG_OFF0 BIT(0) -+ -+#define LTQ_GBIT_MDIO_CTL 0xCC -+#define LTQ_GBIT_MDIO_DATA 0xd0 -+#define LTQ_GBIT_GCTL0 0x68 -+#define LTQ_GBIT_PMAC_HD_CTL 0x8c -+#define LTQ_GBIT_P0_CTL 0x4 -+#define LTQ_GBIT_PMAC_RX_IPG 0xa8 -+#define LTQ_GBIT_RGMII_CTL 0x78 -+ -+#define PMAC_HD_CTL_AS BIT(19) -+#define PMAC_HD_CTL_RXSH BIT(22) -+ -+/* Switch Enable (0=disable, 1=enable) */ -+#define GCTL0_SE 0x80000000 -+/* Disable MDIO auto polling (0=disable, 1=enable) */ -+#define PX_CTL_DMDIO 0x00400000 -+ -+/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ -+#define MDC_CLOCK_MASK 0xff000000 -+#define MDC_CLOCK_OFFSET 24 -+ -+/* register information for the gbit's MDIO bus */ -+#define MDIO_XR9_REQUEST 0x00008000 -+#define MDIO_XR9_READ 0x00000800 -+#define MDIO_XR9_WRITE 0x00000400 -+#define MDIO_XR9_REG_MASK 0x1f -+#define MDIO_XR9_ADDR_MASK 0x1f -+#define MDIO_XR9_RD_MASK 0xffff -+#define MDIO_XR9_REG_OFFSET 0 -+#define MDIO_XR9_ADDR_OFFSET 5 -+#define MDIO_XR9_WR_OFFSET 16 - -+#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ -+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) -+ -+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ - #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) - #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) - #define ltq_etop_w32_mask(x, y, z) \ - ltq_w32_mask(x, y, ltq_etop_membase + (z)) - --#define DRV_VERSION "1.0" -+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) -+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) -+#define ltq_gbit_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) -+ -+#define DRV_VERSION "1.2" - - static void __iomem *ltq_etop_membase; -+static void __iomem *ltq_gbit_membase; - - struct ltq_etop_chan { -- int idx; - int tx_free; -+ int irq; - struct net_device *netdev; - struct napi_struct napi; - struct ltq_dma_channel dma; -@@ -89,25 +140,39 @@ struct ltq_etop_chan { - struct ltq_etop_priv { - struct net_device *netdev; - struct platform_device *pdev; -- struct ltq_eth_data *pldata; - struct resource *res; - - struct mii_bus *mii_bus; - -- struct ltq_etop_chan ch[MAX_DMA_CHAN]; -+ struct ltq_etop_chan txch; -+ struct ltq_etop_chan rxch; - - int tx_burst_len; - int rx_burst_len; - -+ int tx_irq; -+ int rx_irq; -+ -+ unsigned char mac[6]; -+ phy_interface_t mii_mode; -+ - spinlock_t lock; -+ -+ struct clk *clk_ppe; -+ struct clk *clk_switch; -+ struct clk *clk_ephy; -+ struct clk *clk_ephycgu; - }; - -+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data); -+ - static int - ltq_etop_alloc_skb(struct ltq_etop_chan *ch) - { - struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - -- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); -+ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); - if (!ch->skb[ch->dma.desc]) - return -ENOMEM; - ch->dma.desc_base[ch->dma.desc].addr = -@@ -142,8 +207,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan - spin_unlock_irqrestore(&priv->lock, flags); - - skb_put(skb, len); -+ skb->dev = ch->netdev; - skb->protocol = eth_type_trans(skb, ch->netdev); - netif_receive_skb(skb); -+ ch->netdev->stats.rx_packets++; -+ ch->netdev->stats.rx_bytes += len; - } - - static int -@@ -151,7 +219,9 @@ ltq_etop_poll_rx(struct napi_struct *nap - { - struct ltq_etop_chan *ch = container_of(napi, - struct ltq_etop_chan, napi); -+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - int work_done = 0; -+ unsigned long flags; - - while (work_done < budget) { - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -@@ -163,7 +233,9 @@ ltq_etop_poll_rx(struct napi_struct *nap - } - if (work_done < budget) { - napi_complete_done(&ch->napi, work_done); -+ spin_lock_irqsave(&priv->lock, flags); - ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - } - return work_done; - } -@@ -175,12 +247,14 @@ ltq_etop_poll_tx(struct napi_struct *nap - container_of(napi, struct ltq_etop_chan, napi); - struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - struct netdev_queue *txq = -- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); -+ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - while ((ch->dma.desc_base[ch->tx_free].ctl & - (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { -+ ch->netdev->stats.tx_packets++; -+ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; - dev_kfree_skb_any(ch->skb[ch->tx_free]); - ch->skb[ch->tx_free] = NULL; - memset(&ch->dma.desc_base[ch->tx_free], 0, -@@ -193,7 +267,9 @@ ltq_etop_poll_tx(struct napi_struct *nap - if (netif_tx_queue_stopped(txq)) - netif_tx_start_queue(txq); - napi_complete(&ch->napi); -+ spin_lock_irqsave(&priv->lock, flags); - ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - return 1; - } - -@@ -201,9 +277,11 @@ static irqreturn_t - ltq_etop_dma_irq(int irq, void *_priv) - { - struct ltq_etop_priv *priv = _priv; -- int ch = irq - LTQ_DMA_CH0_INT; - -- napi_schedule(&priv->ch[ch].napi); -+ if (irq == priv->txch.dma.irq) -+ napi_schedule(&priv->txch.napi); -+ else -+ napi_schedule(&priv->rxch.napi); - return IRQ_HANDLED; - } - -@@ -215,7 +293,7 @@ ltq_etop_free_channel(struct net_device - ltq_dma_free(&ch->dma); - if (ch->dma.irq) - free_irq(ch->dma.irq, priv); -- if (IS_RX(ch->idx)) { -+ if (ch == &priv->rxch) { - struct ltq_dma_channel *dma = &ch->dma; - - for (dma->desc = 0; dma->desc < LTQ_DESC_NUM; dma->desc++) -@@ -227,80 +305,137 @@ static void - ltq_etop_hw_exit(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; - -- ltq_pmu_disable(PMU_PPE); -- for (i = 0; i < MAX_DMA_CHAN; i++) -- if (IS_TX(i) || IS_RX(i)) -- ltq_etop_free_channel(dev, &priv->ch[i]); -+ clk_disable(priv->clk_ppe); -+ -+ if (of_machine_is_compatible("lantiq,ar9")) -+ clk_disable(priv->clk_switch); -+ -+ if (of_machine_is_compatible("lantiq,ase")) { -+ clk_disable(priv->clk_ephy); -+ clk_disable(priv->clk_ephycgu); -+ } -+ -+ ltq_etop_free_channel(dev, &priv->txch); -+ ltq_etop_free_channel(dev, &priv->rxch); -+} -+ -+static void -+ltq_etop_gbit_init(struct net_device *dev) -+{ -+ struct ltq_etop_priv *priv = netdev_priv(dev); -+ -+ clk_enable(priv->clk_switch); -+ -+ /* enable gbit port0 on the SoC */ -+ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); -+ -+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); -+ /* disable MDIO auto polling mode */ -+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); -+ /* set 1522 packet size */ -+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); -+ /* disable pmac & dmac headers */ -+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, -+ LTQ_GBIT_PMAC_HD_CTL); -+ /* Due to traffic halt when burst length 8, -+ *replace default IPG value with 0x3B -+ */ -+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); -+ /* set mdc clock to 2.5 MHz */ -+ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, -+ LTQ_GBIT_RGMII_CTL); - } - - static int - ltq_etop_hw_init(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -- int err; -+ phy_interface_t mii_mode = priv->mii_mode; -+ -+ clk_enable(priv->clk_ppe); - -- ltq_pmu_enable(PMU_PPE); -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ ltq_etop_gbit_init(dev); -+ /* force the etops link to the gbit to MII */ -+ mii_mode = PHY_INTERFACE_MODE_MII; -+ } -+ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); -+ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | -+ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); - -- switch (priv->pldata->mii_mode) { -+ switch (mii_mode) { - case PHY_INTERFACE_MODE_RMII: -- ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE, -- LTQ_ETOP_CFG); -+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | -+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); - break; - - case PHY_INTERFACE_MODE_MII: -- ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_NORMAL, -- LTQ_ETOP_CFG); -+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | -+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); - break; - - default: -+ if (of_machine_is_compatible("lantiq,ase")) { -+ clk_enable(priv->clk_ephy); -+ /* disable external MII */ -+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); -+ /* enable clock for internal PHY */ -+ clk_enable(priv->clk_ephycgu); -+ /* we need to write this magic to the internal phy to -+ * make it work -+ */ -+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); -+ pr_info("Selected EPHY mode\n"); -+ break; -+ } - netdev_err(dev, "unknown mii mode %d\n", -- priv->pldata->mii_mode); -+ mii_mode); - return -ENOTSUPP; - } - -- /* enable crc generation */ -- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); -+ return 0; -+} -+ -+static int -+ltq_etop_dma_init(struct net_device *dev) -+{ -+ struct ltq_etop_priv *priv = netdev_priv(dev); -+ int tx = priv->tx_irq - LTQ_DMA_ETOP; -+ int rx = priv->rx_irq - LTQ_DMA_ETOP; -+ int err; - - ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len); - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- int irq = LTQ_DMA_CH0_INT + i; -- struct ltq_etop_chan *ch = &priv->ch[i]; -- -- ch->dma.nr = i; -- ch->idx = ch->dma.nr; -- ch->dma.dev = &priv->pdev->dev; -- -- if (IS_TX(i)) { -- ltq_dma_alloc_tx(&ch->dma); -- err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); -- if (err) { -- netdev_err(dev, -- "Unable to get Tx DMA IRQ %d\n", -- irq); -- return err; -- } -- } else if (IS_RX(i)) { -- ltq_dma_alloc_rx(&ch->dma); -- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; -- ch->dma.desc++) -- if (ltq_etop_alloc_skb(ch)) -- return -ENOMEM; -- ch->dma.desc = 0; -- err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); -- if (err) { -- netdev_err(dev, -- "Unable to get Rx DMA IRQ %d\n", -- irq); -- return err; -- } -+ priv->txch.dma.nr = tx; -+ priv->txch.dma.dev = &priv->pdev->dev; -+ ltq_dma_alloc_tx(&priv->txch.dma); -+ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); -+ if (err) { -+ netdev_err(dev, "failed to allocate tx irq\n"); -+ goto err_out; -+ } -+ priv->txch.dma.irq = priv->tx_irq; -+ -+ priv->rxch.dma.nr = rx; -+ priv->rxch.dma.dev = &priv->pdev->dev; -+ ltq_dma_alloc_rx(&priv->rxch.dma); -+ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; -+ priv->rxch.dma.desc++) { -+ if (ltq_etop_alloc_skb(&priv->rxch)) { -+ netdev_err(dev, "failed to allocate skbs\n"); -+ err = -ENOMEM; -+ goto err_out; - } -- ch->dma.irq = irq; - } -- return 0; -+ priv->rxch.dma.desc = 0; -+ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); -+ if (err) -+ netdev_err(dev, "failed to allocate rx irq\n"); -+ else -+ priv->rxch.dma.irq = priv->rx_irq; -+err_out: -+ return err; - } - - static void -@@ -319,6 +454,39 @@ static const struct ethtool_ops ltq_etop - }; - - static int -+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data) -+{ -+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | -+ (phy_data << MDIO_XR9_WR_OFFSET) | -+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | -+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); -+ -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ return 0; -+} -+ -+static int -+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) -+{ -+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | -+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | -+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); -+ -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; -+ return val; -+} -+ -+static int - ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) - { - u32 val = MDIO_REQUEST | -@@ -326,9 +494,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in - ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | - phy_data; - -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- ltq_etop_w32(val, LTQ_ETOP_MDIO); -+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); - return 0; - } - -@@ -339,12 +507,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in - ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | - ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); - -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- ltq_etop_w32(val, LTQ_ETOP_MDIO); -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; -+ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; - return val; - } - -@@ -360,7 +528,10 @@ ltq_etop_mdio_probe(struct net_device *d - struct ltq_etop_priv *priv = netdev_priv(dev); - struct phy_device *phydev; - -- phydev = phy_find_first(priv->mii_bus); -+ if (of_machine_is_compatible("lantiq,ase")) -+ phydev = mdiobus_get_phy(priv->mii_bus, 8); -+ else -+ phydev = mdiobus_get_phy(priv->mii_bus, 0); - - if (!phydev) { - netdev_err(dev, "no PHY found\n"); -@@ -368,14 +539,17 @@ ltq_etop_mdio_probe(struct net_device *d - } - - phydev = phy_connect(dev, phydev_name(phydev), -- <q_etop_mdio_link, priv->pldata->mii_mode); -+ <q_etop_mdio_link, priv->mii_mode); - - if (IS_ERR(phydev)) { - netdev_err(dev, "Could not attach to PHY\n"); - return PTR_ERR(phydev); - } - -- phy_set_max_speed(phydev, SPEED_100); -+ if (of_machine_is_compatible("lantiq,ar9")) -+ phy_set_max_speed(phydev, SPEED_1000); -+ else -+ phy_set_max_speed(phydev, SPEED_100); - - phy_attached_info(phydev); - -@@ -396,8 +570,13 @@ ltq_etop_mdio_init(struct net_device *de - } - - priv->mii_bus->priv = dev; -- priv->mii_bus->read = ltq_etop_mdio_rd; -- priv->mii_bus->write = ltq_etop_mdio_wr; -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; -+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; -+ } else { -+ priv->mii_bus->read = ltq_etop_mdio_rd; -+ priv->mii_bus->write = ltq_etop_mdio_wr; -+ } - priv->mii_bus->name = "ltq_mii"; - snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", - priv->pdev->name, priv->pdev->id); -@@ -434,18 +613,21 @@ static int - ltq_etop_open(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ unsigned long flags; - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- struct ltq_etop_chan *ch = &priv->ch[i]; -+ napi_enable(&priv->txch.napi); -+ napi_enable(&priv->rxch.napi); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_open(&priv->txch.dma); -+ ltq_dma_enable_irq(&priv->txch.dma); -+ ltq_dma_open(&priv->rxch.dma); -+ ltq_dma_enable_irq(&priv->rxch.dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ if (dev->phydev) -+ phy_start(dev->phydev); - -- if (!IS_TX(i) && (!IS_RX(i))) -- continue; -- ltq_dma_open(&ch->dma); -- ltq_dma_enable_irq(&ch->dma); -- napi_enable(&ch->napi); -- } -- phy_start(dev->phydev); - netif_tx_start_all_queues(dev); - return 0; - } -@@ -454,18 +636,19 @@ static int - ltq_etop_stop(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ unsigned long flags; - - netif_tx_stop_all_queues(dev); -- phy_stop(dev->phydev); -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- struct ltq_etop_chan *ch = &priv->ch[i]; -- -- if (!IS_RX(i) && !IS_TX(i)) -- continue; -- napi_disable(&ch->napi); -- ltq_dma_close(&ch->dma); -- } -+ if (dev->phydev) -+ phy_stop(dev->phydev); -+ napi_disable(&priv->txch.napi); -+ napi_disable(&priv->rxch.napi); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_close(&priv->txch.dma); -+ ltq_dma_close(&priv->rxch.dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ - return 0; - } - -@@ -475,17 +658,21 @@ ltq_etop_tx(struct sk_buff *skb, struct - int queue = skb_get_queue_mapping(skb); - struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); - struct ltq_etop_priv *priv = netdev_priv(dev); -- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; -- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -- int len; -+ struct ltq_dma_desc *desc = -+ &priv->txch.dma.desc_base[priv->txch.dma.desc]; - unsigned long flags; - u32 byte_offset; -+ int len; - -- if (skb_put_padto(skb, ETH_ZLEN)) -+ if (skb_put_padto(skb, ETH_ZLEN)) { -+ dev->stats.tx_dropped++; - return NETDEV_TX_OK; -+ } -+ - len = skb->len; - -- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || -+ priv->txch.skb[priv->txch.dma.desc]) { - netdev_err(dev, "tx ring full\n"); - netif_tx_stop_queue(txq); - return NETDEV_TX_BUSY; -@@ -493,7 +680,7 @@ ltq_etop_tx(struct sk_buff *skb, struct - - /* dma needs to start on a burst length value aligned address */ - byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4); -- ch->skb[ch->dma.desc] = skb; -+ priv->txch.skb[priv->txch.dma.desc] = skb; - - netif_trans_update(dev); - -@@ -504,11 +691,11 @@ ltq_etop_tx(struct sk_buff *skb, struct - wmb(); - desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | - LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); -- ch->dma.desc++; -- ch->dma.desc %= LTQ_DESC_NUM; -+ priv->txch.dma.desc++; -+ priv->txch.dma.desc %= LTQ_DESC_NUM; - spin_unlock_irqrestore(&priv->lock, flags); - -- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) -+ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) - netif_tx_stop_queue(txq); - - return NETDEV_TX_OK; -@@ -519,11 +706,14 @@ ltq_etop_change_mtu(struct net_device *d - { - struct ltq_etop_priv *priv = netdev_priv(dev); - unsigned long flags; -+ int max; - - WRITE_ONCE(dev->mtu, new_mtu); - -+ max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; -+ - spin_lock_irqsave(&priv->lock, flags); -- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); -+ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN); - spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -@@ -576,6 +766,9 @@ ltq_etop_init(struct net_device *dev) - if (err) - goto err_hw; - ltq_etop_change_mtu(dev, 1500); -+ err = ltq_etop_dma_init(dev); -+ if (err) -+ goto err_hw; - - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); - if (!is_valid_ether_addr(mac.sa_data)) { -@@ -593,9 +786,10 @@ ltq_etop_init(struct net_device *dev) - dev->addr_assign_type = NET_ADDR_RANDOM; - - ltq_etop_set_multicast_list(dev); -- err = ltq_etop_mdio_init(dev); -- if (err) -- goto err_netdev; -+ if (!ltq_etop_mdio_init(dev)) -+ dev->ethtool_ops = <q_etop_ethtool_ops; -+ else -+ pr_warn("etop: mdio probe failed\n"); - return 0; - - err_netdev: -@@ -615,6 +809,9 @@ ltq_etop_tx_timeout(struct net_device *d - err = ltq_etop_hw_init(dev); - if (err) - goto err_hw; -+ err = ltq_etop_dma_init(dev); -+ if (err) -+ goto err_hw; - netif_trans_update(dev); - netif_wake_queue(dev); - return; -@@ -638,14 +835,18 @@ static const struct net_device_ops ltq_e - .ndo_tx_timeout = ltq_etop_tx_timeout, - }; - --static int __init --ltq_etop_probe(struct platform_device *pdev) -+static int ltq_etop_probe(struct platform_device *pdev) - { - struct net_device *dev; - struct ltq_etop_priv *priv; -- struct resource *res; -+ struct resource *res, *gbit_res, irqres[2]; - int err; -- int i; -+ -+ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); -+ if (err != 2) { -+ dev_err(&pdev->dev, "failed to get etop irqs\n"); -+ return -EINVAL; -+ } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { -@@ -671,18 +872,60 @@ ltq_etop_probe(struct platform_device *p - goto err_out; - } - -- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); -- if (!dev) { -- err = -ENOMEM; -- goto err_out; -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ if (!gbit_res) { -+ dev_err(&pdev->dev, "failed to get gbit resource\n"); -+ err = -ENOENT; -+ goto err_out; -+ } -+ ltq_gbit_membase = devm_ioremap(&pdev->dev, -+ gbit_res->start, resource_size(gbit_res)); -+ if (!ltq_gbit_membase) { -+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", -+ pdev->id); -+ err = -ENOMEM; -+ goto err_out; -+ } - } -+ -+ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); - dev->netdev_ops = <q_eth_netdev_ops; -- dev->ethtool_ops = <q_etop_ethtool_ops; - priv = netdev_priv(dev); - priv->res = res; - priv->pdev = pdev; -- priv->pldata = dev_get_platdata(&pdev->dev); - priv->netdev = dev; -+ priv->tx_irq = irqres[0].start; -+ priv->rx_irq = irqres[1].start; -+ err = of_get_phy_mode(pdev->dev.of_node, &priv->mii_mode); -+ if (err) -+ pr_err("Can't find phy-mode for port\n"); -+ -+ err = of_get_mac_address(pdev->dev.of_node, priv->mac); -+ if (err == -EPROBE_DEFER) -+ goto err_out; -+ if (err) { -+ eth_hw_addr_random(dev); -+ dev_err(&pdev->dev, "generated random MAC address %pM\n", priv->mac); -+ } -+ -+ priv->clk_ppe = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->clk_ppe)) -+ return PTR_ERR(priv->clk_ppe); -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ priv->clk_switch = clk_get(&pdev->dev, "switch"); -+ if (IS_ERR(priv->clk_switch)) -+ return PTR_ERR(priv->clk_switch); -+ } -+ if (of_machine_is_compatible("lantiq,ase")) { -+ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); -+ if (IS_ERR(priv->clk_ephy)) -+ return PTR_ERR(priv->clk_ephy); -+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); -+ if (IS_ERR(priv->clk_ephycgu)) -+ return PTR_ERR(priv->clk_ephycgu); -+ } -+ - spin_lock_init(&priv->lock); - SET_NETDEV_DEV(dev, &pdev->dev); - -@@ -698,15 +941,10 @@ ltq_etop_probe(struct platform_device *p - goto err_free; - } - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- if (IS_TX(i)) -- netif_napi_add_weight(dev, &priv->ch[i].napi, -- ltq_etop_poll_tx, 8); -- else if (IS_RX(i)) -- netif_napi_add_weight(dev, &priv->ch[i].napi, -- ltq_etop_poll_rx, 32); -- priv->ch[i].netdev = dev; -- } -+ netif_napi_add_weight(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); -+ netif_napi_add_weight(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); -+ priv->txch.netdev = dev; -+ priv->rxch.netdev = dev; - - err = register_netdev(dev); - if (err) -@@ -733,31 +971,22 @@ static void ltq_etop_remove(struct platf - } - } - -+static const struct of_device_id ltq_etop_match[] = { -+ { .compatible = "lantiq,etop-xway" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ltq_etop_match); -+ - static struct platform_driver ltq_mii_driver = { -+ .probe = ltq_etop_probe, - .remove_new = ltq_etop_remove, - .driver = { - .name = "ltq_etop", -+ .of_match_table = ltq_etop_match, - }, - }; - --static int __init --init_ltq_etop(void) --{ -- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); -- -- if (ret) -- pr_err("ltq_etop: Error registering platform driver!"); -- return ret; --} -- --static void __exit --exit_ltq_etop(void) --{ -- platform_driver_unregister(<q_mii_driver); --} -- --module_init(init_ltq_etop); --module_exit(exit_ltq_etop); -+module_platform_driver(ltq_mii_driver); - - MODULE_AUTHOR("John Crispin "); - MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-6.12/031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-6.12/031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch deleted file mode 100644 index 27159c7c50b..00000000000 --- a/target/linux/lantiq/patches-6.12/031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch +++ /dev/null @@ -1,1028 +0,0 @@ -From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:26:42 +0200 -Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master - -This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - drivers/i2c/busses/Kconfig | 10 + - drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ - drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ - 4 files changed, 992 insertions(+) - create mode 100644 drivers/i2c/busses/i2c-lantiq.c - create mode 100644 drivers/i2c/busses/i2c-lantiq.h - ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -857,6 +857,16 @@ config I2C_MICROCHIP_CORE - This driver can also be built as a module. If so, the module will be - called i2c-microchip-core. - -+config I2C_LANTIQ -+ tristate "Lantiq I2C interface" -+ depends on LANTIQ && SOC_FALCON -+ help -+ If you say yes to this option, support will be included for the -+ Lantiq I2C core. -+ -+ This driver can also be built as a module. If so, the module -+ will be called i2c-lantiq. -+ - config I2C_MPC - tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" - depends on PPC ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -78,6 +78,7 @@ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o - obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o - obj-$(CONFIG_I2C_KEBA) += i2c-keba.o - obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o -+obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o - obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o - obj-$(CONFIG_I2C_LS2X) += i2c-ls2x.o - obj-$(CONFIG_I2C_MESON) += i2c-meson.o ---- /dev/null -+++ b/drivers/i2c/busses/i2c-lantiq.c -@@ -0,0 +1,741 @@ -+ -+/* -+ * Lantiq I2C bus adapter -+ * -+ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * Copyright (C) 2012 Thomas Langer -+ */ -+ -+#include -+#include -+#include -+#include /* for kzalloc, kfree */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "i2c-lantiq.h" -+ -+/* -+ * CURRENT ISSUES: -+ * - no high speed support -+ * - ten bit mode is not tested (no slave devices) -+ */ -+ -+/* access macros */ -+#define i2c_r32(reg) \ -+ __raw_readl(&(priv->membase)->reg) -+#define i2c_w32(val, reg) \ -+ __raw_writel(val, &(priv->membase)->reg) -+#define i2c_w32_mask(clear, set, reg) \ -+ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) -+ -+#define DRV_NAME "i2c-lantiq" -+#define DRV_VERSION "1.00" -+ -+#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ -+ -+#ifdef DEBUG -+#define LTQ_I2C_XFER_TIMEOUT (25*HZ) -+#else -+#define LTQ_I2C_XFER_TIMEOUT HZ -+#endif -+ -+#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ -+ I2C_IMSC_I2C_ERR_INT_EN) -+ -+#define LTQ_I2C_ARB_LOST (1 << 0) -+#define LTQ_I2C_NACK (1 << 1) -+#define LTQ_I2C_RX_UFL (1 << 2) -+#define LTQ_I2C_RX_OFL (1 << 3) -+#define LTQ_I2C_TX_UFL (1 << 4) -+#define LTQ_I2C_TX_OFL (1 << 5) -+ -+struct ltq_i2c { -+ struct mutex mutex; -+ -+ -+ /* active clock settings */ -+ unsigned int input_clock; /* clock input for i2c hardware block */ -+ unsigned int i2c_clock; /* approximated bus clock in kHz */ -+ -+ struct clk *clk_gate; -+ struct clk *clk_input; -+ -+ -+ /* resources (memory and interrupts) */ -+ int irq_lb; /* last burst irq */ -+ -+ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ -+ -+ struct i2c_adapter adap; -+ struct device *dev; -+ -+ struct completion cmd_complete; -+ -+ -+ /* message transfer data */ -+ struct i2c_msg *current_msg; /* current message */ -+ int msgs_num; /* number of messages to handle */ -+ u8 *msg_buf; /* current buffer */ -+ u32 msg_buf_len; /* remaining length of current buffer */ -+ int msg_err; /* error status of the current transfer */ -+ -+ -+ /* master status codes */ -+ enum { -+ STATUS_IDLE, -+ STATUS_ADDR, /* address phase */ -+ STATUS_WRITE, -+ STATUS_READ, -+ STATUS_READ_END, -+ STATUS_STOP -+ } status; -+}; -+ -+static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); -+ -+static inline void enable_burst_irq(struct ltq_i2c *priv) -+{ -+ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); -+} -+static inline void disable_burst_irq(struct ltq_i2c *priv) -+{ -+ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); -+} -+ -+static void prepare_msg_send_addr(struct ltq_i2c *priv) -+{ -+ struct i2c_msg *msg = priv->current_msg; -+ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ -+ u16 addr = msg->addr; -+ -+ /* new i2c_msg */ -+ priv->msg_buf = msg->buf; -+ priv->msg_buf_len = msg->len; -+ if (rd) -+ priv->status = STATUS_READ; -+ else -+ priv->status = STATUS_WRITE; -+ -+ /* send slave address */ -+ if (msg->flags & I2C_M_TEN) { -+ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); -+ i2c_w32(addr & 0xff, txd); -+ } else { -+ i2c_w32((addr & 0x7f) << 1 | rd, txd); -+ } -+} -+ -+static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) -+{ -+ struct i2c_msg *msg = priv->current_msg; -+ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; -+ -+ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); -+ -+ priv->status = STATUS_ADDR; -+ -+ if (!(msg->flags & I2C_M_RD)) -+ len += msg->len; -+ else -+ /* set maximum received packet size (before rx int!) */ -+ i2c_w32(msg->len, mrps_ctrl); -+ i2c_w32(len, tps_ctrl); -+ enable_burst_irq(priv); -+} -+ -+static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) -+{ -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ unsigned int input_clock = clk_get_rate(priv->clk_input); -+ u32 dec, inc = 1; -+ -+ /* clock changed? */ -+ if (priv->input_clock == input_clock) -+ return 0; -+ -+ /* -+ * this formula is only an approximation, found by the recommended -+ * values in the "I2C Architecture Specification 1.7.1" -+ */ -+ dec = input_clock / (priv->i2c_clock * 2); -+ if (dec <= 6) -+ return -ENXIO; -+ -+ i2c_w32(0, fdiv_high_cfg); -+ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | -+ (dec << I2C_FDIV_CFG_DEC_OFFSET), -+ fdiv_cfg); -+ -+ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", -+ input_clock, priv->i2c_clock, dec); -+ -+ priv->input_clock = input_clock; -+ return 0; -+} -+ -+static int ltq_i2c_hw_init(struct i2c_adapter *adap) -+{ -+ int ret = 0; -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ -+ /* disable bus */ -+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); -+ -+#ifndef DEBUG -+ /* set normal operation clock divider */ -+ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); -+#else -+ /* for debugging a higher divider value! */ -+ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); -+#endif -+ -+ /* setup clock */ -+ ret = ltq_i2c_hw_set_clock(adap); -+ if (ret != 0) { -+ dev_warn(priv->dev, "invalid clock settings\n"); -+ return ret; -+ } -+ -+ /* configure fifo */ -+ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ -+ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ -+ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ -+ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ -+ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ -+ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ -+ fifo_cfg); -+ -+ /* configure address */ -+ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in -+ the fifo */ -+ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ -+ I2C_ADDR_CFG_MnS_EN | /* we are master device */ -+ 0, /* our slave address (not used!) */ -+ addr_cfg); -+ -+ /* enable bus */ -+ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); -+ -+ return 0; -+} -+ -+static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) -+{ -+ unsigned long timeout; -+ -+ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); -+ -+ do { -+ u32 stat = i2c_r32(bus_stat); -+ -+ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) -+ return 0; -+ -+ cond_resched(); -+ } while (!time_after_eq(jiffies, timeout)); -+ -+ dev_err(priv->dev, "timeout waiting for bus ready\n"); -+ return -ETIMEDOUT; -+} -+ -+static void ltq_i2c_tx(struct ltq_i2c *priv, int last) -+{ -+ if (priv->msg_buf_len && priv->msg_buf) { -+ i2c_w32(*priv->msg_buf, txd); -+ -+ if (--priv->msg_buf_len) -+ priv->msg_buf++; -+ else -+ priv->msg_buf = NULL; -+ } else { -+ last = 1; -+ } -+ -+ if (last) -+ disable_burst_irq(priv); -+} -+ -+static void ltq_i2c_rx(struct ltq_i2c *priv, int last) -+{ -+ u32 fifo_stat, timeout; -+ if (priv->msg_buf_len && priv->msg_buf) { -+ timeout = 5000000; -+ do { -+ fifo_stat = i2c_r32(ffs_stat); -+ } while (!fifo_stat && --timeout); -+ if (!timeout) { -+ last = 1; -+ pr_debug("\nrx timeout\n"); -+ goto err; -+ } -+ while (fifo_stat) { -+ *priv->msg_buf = i2c_r32(rxd); -+ if (--priv->msg_buf_len) { -+ priv->msg_buf++; -+ } else { -+ priv->msg_buf = NULL; -+ last = 1; -+ break; -+ } -+ /* -+ * do not read more than burst size, otherwise no "last -+ * burst" is generated and the transaction is blocked! -+ */ -+ fifo_stat = 0; -+ } -+ } else { -+ last = 1; -+ } -+err: -+ if (last) { -+ disable_burst_irq(priv); -+ -+ if (priv->status == STATUS_READ_END) { -+ /* -+ * do the STATUS_STOP and complete() here, as sometimes -+ * the tx_end is already seen before this is finished -+ */ -+ priv->status = STATUS_STOP; -+ complete(&priv->cmd_complete); -+ } else { -+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); -+ priv->status = STATUS_READ_END; -+ } -+ } -+} -+ -+static void ltq_i2c_xfer_init(struct ltq_i2c *priv) -+{ -+ /* enable interrupts */ -+ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); -+ -+ /* trigger transfer of first msg */ -+ ltq_i2c_set_tx_len(priv); -+} -+ -+static void dump_msgs(struct i2c_msg msgs[], int num, int rx) -+{ -+#if defined(DEBUG) -+ int i, j; -+ pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); -+ for (i = 0; i < num; i++) { -+ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, -+ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', -+ msgs[i].len, msgs[i].addr); -+ if (!(msgs[i].flags & I2C_M_RD) || rx) { -+ for (j = 0; j < msgs[i].len; j++) -+ pr_debug("%02X ", msgs[i].buf[j]); -+ } -+ pr_debug("\n"); -+ } -+#endif -+} -+ -+static void ltq_i2c_release_bus(struct ltq_i2c *priv) -+{ -+ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) -+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); -+} -+ -+static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], -+ int num) -+{ -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ int ret; -+ -+ dev_dbg(priv->dev, "xfer %u messages\n", num); -+ dump_msgs(msgs, num, 0); -+ -+ mutex_lock(&priv->mutex); -+ -+ init_completion(&priv->cmd_complete); -+ priv->current_msg = msgs; -+ priv->msgs_num = num; -+ priv->msg_err = 0; -+ priv->status = STATUS_IDLE; -+ -+ /* wait for the bus to become ready */ -+ ret = ltq_i2c_wait_bus_not_busy(priv); -+ if (ret) -+ goto done; -+ -+ while (priv->msgs_num) { -+ /* start the transfers */ -+ ltq_i2c_xfer_init(priv); -+ -+ /* wait for transfers to complete */ -+ ret = wait_for_completion_interruptible_timeout( -+ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); -+ if (ret == 0) { -+ dev_err(priv->dev, "controller timed out\n"); -+ ltq_i2c_hw_init(adap); -+ ret = -ETIMEDOUT; -+ goto done; -+ } else if (ret < 0) -+ goto done; -+ -+ if (priv->msg_err) { -+ if (priv->msg_err & LTQ_I2C_NACK) -+ ret = -ENXIO; -+ else -+ ret = -EREMOTEIO; -+ goto done; -+ } -+ if (--priv->msgs_num) -+ priv->current_msg++; -+ } -+ /* no error? */ -+ ret = num; -+ -+done: -+ ltq_i2c_release_bus(priv); -+ -+ mutex_unlock(&priv->mutex); -+ -+ if (ret >= 0) -+ dump_msgs(msgs, num, 1); -+ -+ pr_debug("XFER ret %d\n", ret); -+ return ret; -+} -+ -+static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) -+{ -+ struct ltq_i2c *priv = dev_id; -+ struct i2c_msg *msg = priv->current_msg; -+ int last = (irq == priv->irq_lb); -+ -+ if (last) -+ pr_debug("LB "); -+ else -+ pr_debug("B "); -+ -+ if (msg->flags & I2C_M_RD) { -+ switch (priv->status) { -+ case STATUS_ADDR: -+ pr_debug("X"); -+ prepare_msg_send_addr(priv); -+ disable_burst_irq(priv); -+ break; -+ case STATUS_READ: -+ case STATUS_READ_END: -+ pr_debug("R"); -+ ltq_i2c_rx(priv, last); -+ break; -+ default: -+ disable_burst_irq(priv); -+ pr_warn("Status R %d\n", priv->status); -+ break; -+ } -+ } else { -+ switch (priv->status) { -+ case STATUS_ADDR: -+ pr_debug("x"); -+ prepare_msg_send_addr(priv); -+ break; -+ case STATUS_WRITE: -+ pr_debug("w"); -+ ltq_i2c_tx(priv, last); -+ break; -+ default: -+ disable_burst_irq(priv); -+ pr_warn("Status W %d\n", priv->status); -+ break; -+ } -+ } -+ -+ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); -+ return IRQ_HANDLED; -+} -+ -+static void ltq_i2c_isr_prot(struct ltq_i2c *priv) -+{ -+ u32 i_pro = i2c_r32(p_irqss); -+ -+ pr_debug("i2c-p"); -+ -+ /* not acknowledge */ -+ if (i_pro & I2C_P_IRQSS_NACK) { -+ priv->msg_err |= LTQ_I2C_NACK; -+ pr_debug(" nack"); -+ } -+ -+ /* arbitration lost */ -+ if (i_pro & I2C_P_IRQSS_AL) { -+ priv->msg_err |= LTQ_I2C_ARB_LOST; -+ pr_debug(" arb-lost"); -+ } -+ /* tx -> rx switch */ -+ if (i_pro & I2C_P_IRQSS_RX) -+ pr_debug(" rx"); -+ -+ /* tx end */ -+ if (i_pro & I2C_P_IRQSS_TX_END) -+ pr_debug(" txend"); -+ pr_debug("\n"); -+ -+ if (!priv->msg_err) { -+ /* tx -> rx switch */ -+ if (i_pro & I2C_P_IRQSS_RX) { -+ priv->status = STATUS_READ; -+ enable_burst_irq(priv); -+ } -+ if (i_pro & I2C_P_IRQSS_TX_END) { -+ if (priv->status == STATUS_READ) -+ priv->status = STATUS_READ_END; -+ else { -+ disable_burst_irq(priv); -+ priv->status = STATUS_STOP; -+ } -+ } -+ } -+ -+ i2c_w32(i_pro, p_irqsc); -+} -+ -+static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) -+{ -+ u32 i_raw, i_err = 0; -+ struct ltq_i2c *priv = dev_id; -+ -+ i_raw = i2c_r32(mis); -+ pr_debug("i_raw 0x%08X\n", i_raw); -+ -+ /* error interrupt */ -+ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { -+ i_err = i2c_r32(err_irqss); -+ pr_debug("i_err 0x%08X bus_stat 0x%04X\n", -+ i_err, i2c_r32(bus_stat)); -+ -+ /* tx fifo overflow (8) */ -+ if (i_err & I2C_ERR_IRQSS_TXF_OFL) -+ priv->msg_err |= LTQ_I2C_TX_OFL; -+ -+ /* tx fifo underflow (4) */ -+ if (i_err & I2C_ERR_IRQSS_TXF_UFL) -+ priv->msg_err |= LTQ_I2C_TX_UFL; -+ -+ /* rx fifo overflow (2) */ -+ if (i_err & I2C_ERR_IRQSS_RXF_OFL) -+ priv->msg_err |= LTQ_I2C_RX_OFL; -+ -+ /* rx fifo underflow (1) */ -+ if (i_err & I2C_ERR_IRQSS_RXF_UFL) -+ priv->msg_err |= LTQ_I2C_RX_UFL; -+ -+ i2c_w32(i_err, err_irqsc); -+ } -+ -+ /* protocol interrupt */ -+ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) -+ ltq_i2c_isr_prot(priv); -+ -+ if ((priv->msg_err) || (priv->status == STATUS_STOP)) -+ complete(&priv->cmd_complete); -+ -+ return IRQ_HANDLED; -+} -+ -+static u32 ltq_i2c_functionality(struct i2c_adapter *adap) -+{ -+ return I2C_FUNC_I2C | -+ I2C_FUNC_10BIT_ADDR | -+ I2C_FUNC_SMBUS_EMUL; -+} -+ -+static struct i2c_algorithm ltq_i2c_algorithm = { -+ .master_xfer = ltq_i2c_xfer, -+ .functionality = ltq_i2c_functionality, -+}; -+ -+static int ltq_i2c_probe(struct platform_device *pdev) -+{ -+ struct device_node *node = pdev->dev.of_node; -+ struct ltq_i2c *priv; -+ struct i2c_adapter *adap; -+ struct resource irqres[4]; -+ int ret = 0; -+ -+ dev_dbg(&pdev->dev, "probing\n"); -+ -+ ret = of_irq_to_resource_table(node, irqres, 4); -+ if (ret != 4) { -+ dev_err(&pdev->dev, "no resources\n"); -+ return -ENODEV; -+ } -+ -+ /* allocate private data */ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) { -+ dev_err(&pdev->dev, "can't allocate private data\n"); -+ return -ENOMEM; -+ } -+ -+ adap = &priv->adap; -+ i2c_set_adapdata(adap, priv); -+ adap->owner = THIS_MODULE; -+ adap->class = I2C_CLASS_HWMON; -+ strscpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); -+ adap->algo = <q_i2c_algorithm; -+ adap->dev.parent = &pdev->dev; -+ adap->dev.of_node = pdev->dev.of_node; -+ -+ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { -+ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); -+ priv->i2c_clock = 100000; -+ } -+ -+ init_completion(&priv->cmd_complete); -+ ret = devm_mutex_init(&pdev->dev, &priv->mutex); -+ if (ret) -+ return ret; -+ -+ priv->membase = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(priv->membase)) -+ return PTR_ERR(priv->membase); -+ -+ priv->dev = &pdev->dev; -+ priv->irq_lb = irqres[0].start; -+ -+ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, -+ 0x0, "i2c lb", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", -+ irqres[0].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, -+ 0x0, "i2c b", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get burst IRQ %d\n", -+ irqres[1].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, -+ 0x0, "i2c err", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get error IRQ %d\n", -+ irqres[2].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, -+ 0x0, "i2c p", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", -+ irqres[3].start); -+ return -ENODEV; -+ } -+ -+ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); -+ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, -+ irqres[1].start, irqres[2].start, irqres[3].start); -+ -+ priv->clk_gate = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->clk_gate)) { -+ dev_err(&pdev->dev, "failed to get i2c clk\n"); -+ return -ENOENT; -+ } -+ -+ /* this is a static clock, which has no refcounting */ -+ priv->clk_input = clk_get_fpi(); -+ if (IS_ERR(priv->clk_input)) { -+ dev_err(&pdev->dev, "failed to get fpi clk\n"); -+ return -ENOENT; -+ } -+ -+ clk_activate(priv->clk_gate); -+ -+ /* add our adapter to the i2c stack */ -+ ret = devm_i2c_add_adapter(&pdev->dev, adap); -+ if (ret) { -+ dev_err(&pdev->dev, "can't register I2C adapter\n"); -+ goto out; -+ } -+ -+ platform_set_drvdata(pdev, priv); -+ i2c_set_adapdata(adap, priv); -+ -+ /* print module version information */ -+ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", -+ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, -+ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); -+ -+ /* initialize HW */ -+ ret = ltq_i2c_hw_init(adap); -+ if (ret) { -+ dev_err(&pdev->dev, "can't configure adapter\n"); -+ platform_set_drvdata(pdev, NULL); -+ goto out; -+ } else { -+ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); -+ } -+ -+out: -+ /* if init failed, we need to deactivate the clock gate */ -+ if (ret) -+ clk_deactivate(priv->clk_gate); -+ -+ return ret; -+} -+ -+static void ltq_i2c_remove(struct platform_device *pdev) -+{ -+ struct ltq_i2c *priv = platform_get_drvdata(pdev); -+ -+ /* disable bus */ -+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); -+ -+ /* power down the core */ -+ clk_deactivate(priv->clk_gate); -+ -+ dev_dbg(&pdev->dev, "removed\n"); -+ platform_set_drvdata(pdev, NULL); -+} -+ -+static const struct of_device_id ltq_i2c_match[] = { -+ { .compatible = "lantiq,lantiq-i2c" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ltq_i2c_match); -+ -+static struct platform_driver ltq_i2c_driver = { -+ .probe = ltq_i2c_probe, -+ .remove = ltq_i2c_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .of_match_table = ltq_i2c_match, -+ }, -+}; -+ -+module_platform_driver(ltq_i2c_driver); -+ -+MODULE_DESCRIPTION("Lantiq I2C bus adapter"); -+MODULE_AUTHOR("Thomas Langer "); -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION(DRV_VERSION); ---- /dev/null -+++ b/drivers/i2c/busses/i2c-lantiq.h -@@ -0,0 +1,234 @@ -+#ifndef I2C_LANTIQ_H -+#define I2C_LANTIQ_H -+ -+/* I2C register structure */ -+struct lantiq_reg_i2c { -+ /* I2C Kernel Clock Control Register */ -+ unsigned int clc; /* 0x00000000 */ -+ /* Reserved */ -+ unsigned int res_0; /* 0x00000004 */ -+ /* I2C Identification Register */ -+ unsigned int id; /* 0x00000008 */ -+ /* Reserved */ -+ unsigned int res_1; /* 0x0000000C */ -+ /* -+ * I2C RUN Control Register -+ * This register enables and disables the I2C peripheral. Before -+ * enabling, the I2C has to be configured properly. After enabling -+ * no configuration is possible -+ */ -+ unsigned int run_ctrl; /* 0x00000010 */ -+ /* -+ * I2C End Data Control Register -+ * This register is used to either turn around the data transmission -+ * direction or to address another slave without sending a stop -+ * condition. Also the software can stop the slave-transmitter by -+ * sending a not-accolade when working as master-receiver or even -+ * stop data transmission immediately when operating as -+ * master-transmitter. The writing to the bits of this control -+ * register is only effective when in MASTER RECEIVES BYTES, MASTER -+ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state -+ */ -+ unsigned int endd_ctrl; /* 0x00000014 */ -+ /* -+ * I2C Fractional Divider Configuration Register -+ * These register is used to program the fractional divider of the I2C -+ * bus. Before the peripheral is switched on by setting the RUN-bit the -+ * two (fixed) values for the two operating frequencies are programmed -+ * into these (configuration) registers. The Register FDIV_HIGH_CFG has -+ * the same layout as I2C_FDIV_CFG. -+ */ -+ unsigned int fdiv_cfg; /* 0x00000018 */ -+ /* -+ * I2C Fractional Divider (highspeed mode) Configuration Register -+ * These register is used to program the fractional divider of the I2C -+ * bus. Before the peripheral is switched on by setting the RUN-bit the -+ * two (fixed) values for the two operating frequencies are programmed -+ * into these (configuration) registers. The Register FDIV_CFG has the -+ * same layout as I2C_FDIV_CFG. -+ */ -+ unsigned int fdiv_high_cfg; /* 0x0000001C */ -+ /* I2C Address Configuration Register */ -+ unsigned int addr_cfg; /* 0x00000020 */ -+ /* I2C Bus Status Register -+ * This register gives a status information of the I2C. This additional -+ * information can be used by the software to start proper actions. -+ */ -+ unsigned int bus_stat; /* 0x00000024 */ -+ /* I2C FIFO Configuration Register */ -+ unsigned int fifo_cfg; /* 0x00000028 */ -+ /* I2C Maximum Received Packet Size Register */ -+ unsigned int mrps_ctrl; /* 0x0000002C */ -+ /* I2C Received Packet Size Status Register */ -+ unsigned int rps_stat; /* 0x00000030 */ -+ /* I2C Transmit Packet Size Register */ -+ unsigned int tps_ctrl; /* 0x00000034 */ -+ /* I2C Filled FIFO Stages Status Register */ -+ unsigned int ffs_stat; /* 0x00000038 */ -+ /* Reserved */ -+ unsigned int res_2; /* 0x0000003C */ -+ /* I2C Timing Configuration Register */ -+ unsigned int tim_cfg; /* 0x00000040 */ -+ /* Reserved */ -+ unsigned int res_3[7]; /* 0x00000044 */ -+ /* I2C Error Interrupt Request Source Mask Register */ -+ unsigned int err_irqsm; /* 0x00000060 */ -+ /* I2C Error Interrupt Request Source Status Register */ -+ unsigned int err_irqss; /* 0x00000064 */ -+ /* I2C Error Interrupt Request Source Clear Register */ -+ unsigned int err_irqsc; /* 0x00000068 */ -+ /* Reserved */ -+ unsigned int res_4; /* 0x0000006C */ -+ /* I2C Protocol Interrupt Request Source Mask Register */ -+ unsigned int p_irqsm; /* 0x00000070 */ -+ /* I2C Protocol Interrupt Request Source Status Register */ -+ unsigned int p_irqss; /* 0x00000074 */ -+ /* I2C Protocol Interrupt Request Source Clear Register */ -+ unsigned int p_irqsc; /* 0x00000078 */ -+ /* Reserved */ -+ unsigned int res_5; /* 0x0000007C */ -+ /* I2C Raw Interrupt Status Register */ -+ unsigned int ris; /* 0x00000080 */ -+ /* I2C Interrupt Mask Control Register */ -+ unsigned int imsc; /* 0x00000084 */ -+ /* I2C Masked Interrupt Status Register */ -+ unsigned int mis; /* 0x00000088 */ -+ /* I2C Interrupt Clear Register */ -+ unsigned int icr; /* 0x0000008C */ -+ /* I2C Interrupt Set Register */ -+ unsigned int isr; /* 0x00000090 */ -+ /* I2C DMA Enable Register */ -+ unsigned int dmae; /* 0x00000094 */ -+ /* Reserved */ -+ unsigned int res_6[8154]; /* 0x00000098 */ -+ /* I2C Transmit Data Register */ -+ unsigned int txd; /* 0x00008000 */ -+ /* Reserved */ -+ unsigned int res_7[4095]; /* 0x00008004 */ -+ /* I2C Receive Data Register */ -+ unsigned int rxd; /* 0x0000C000 */ -+ /* Reserved */ -+ unsigned int res_8[4095]; /* 0x0000C004 */ -+}; -+ -+/* -+ * Clock Divider for Normal Run Mode -+ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long -+ * as the new divider value RMC is not valid, the register returns 0x0000 00xx -+ * on reading. -+ */ -+#define I2C_CLC_RMC_MASK 0x0000FF00 -+/* field offset */ -+#define I2C_CLC_RMC_OFFSET 8 -+ -+/* Fields of "I2C Identification Register" */ -+/* Module ID */ -+#define I2C_ID_ID_MASK 0x0000FF00 -+/* field offset */ -+#define I2C_ID_ID_OFFSET 8 -+/* Revision */ -+#define I2C_ID_REV_MASK 0x000000FF -+/* field offset */ -+#define I2C_ID_REV_OFFSET 0 -+ -+/* Fields of "I2C Interrupt Mask Control Register" */ -+/* Enable */ -+#define I2C_IMSC_BREQ_INT_EN 0x00000008 -+/* Enable */ -+#define I2C_IMSC_LBREQ_INT_EN 0x00000004 -+ -+/* Fields of "I2C Fractional Divider Configuration Register" */ -+/* field offset */ -+#define I2C_FDIV_CFG_INC_OFFSET 16 -+ -+/* Fields of "I2C Interrupt Mask Control Register" */ -+/* Enable */ -+#define I2C_IMSC_I2C_P_INT_EN 0x00000020 -+/* Enable */ -+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 -+ -+/* Fields of "I2C Error Interrupt Request Source Status Register" */ -+/* TXF_OFL */ -+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 -+/* TXF_UFL */ -+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 -+/* RXF_OFL */ -+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 -+/* RXF_UFL */ -+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 -+ -+/* Fields of "I2C Raw Interrupt Status Register" */ -+/* Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 -+/* Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 -+ -+/* Fields of "I2C FIFO Configuration Register" */ -+/* TX FIFO Flow Control */ -+#define I2C_FIFO_CFG_TXFC 0x00020000 -+/* RX FIFO Flow Control */ -+#define I2C_FIFO_CFG_RXFC 0x00010000 -+/* Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 -+/* Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 -+/* 1 word */ -+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 -+ -+/* Fields of "I2C FIFO Configuration Register" */ -+/* 1 word */ -+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 -+/* Stop on Packet End Enable */ -+#define I2C_ADDR_CFG_SOPE_EN 0x00200000 -+/* Stop on Not Acknowledge Enable */ -+#define I2C_ADDR_CFG_SONA_EN 0x00100000 -+/* Enable */ -+#define I2C_ADDR_CFG_MnS_EN 0x00080000 -+ -+/* Fields of "I2C Interrupt Clear Register" */ -+/* Clear */ -+#define I2C_ICR_BREQ_INT_CLR 0x00000008 -+/* Clear */ -+#define I2C_ICR_LBREQ_INT_CLR 0x00000004 -+ -+/* Fields of "I2C Fractional Divider Configuration Register" */ -+/* field offset */ -+#define I2C_FDIV_CFG_DEC_OFFSET 0 -+ -+/* Fields of "I2C Bus Status Register" */ -+/* Bus Status */ -+#define I2C_BUS_STAT_BS_MASK 0x00000003 -+/* Read from I2C Bus. */ -+#define I2C_BUS_STAT_RNW_READ 0x00000004 -+/* I2C Bus is free. */ -+#define I2C_BUS_STAT_BS_FREE 0x00000000 -+/* -+ * The device is working as master and has claimed the control on the -+ * I2C-bus (busy master). -+ */ -+#define I2C_BUS_STAT_BS_BM 0x00000002 -+ -+/* Fields of "I2C RUN Control Register" */ -+/* Enable */ -+#define I2C_RUN_CTRL_RUN_EN 0x00000001 -+ -+/* Fields of "I2C End Data Control Register" */ -+/* -+ * Set End of Transmission -+ * Note:Do not write '1' to this bit when bus is free. This will cause an -+ * abort after the first byte when a new transfer is started. -+ */ -+#define I2C_ENDD_CTRL_SETEND 0x00000002 -+ -+/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ -+/* NACK */ -+#define I2C_P_IRQSS_NACK 0x00000010 -+/* AL */ -+#define I2C_P_IRQSS_AL 0x00000008 -+/* RX */ -+#define I2C_P_IRQSS_RX 0x00000040 -+/* TX_END */ -+#define I2C_P_IRQSS_TX_END 0x00000020 -+ -+ -+#endif /* I2C_LANTIQ_H */ diff --git a/target/linux/lantiq/patches-6.12/035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-6.12/035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch deleted file mode 100644 index 10f2d4086d3..00000000000 --- a/target/linux/lantiq/patches-6.12/035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch +++ /dev/null @@ -1,239 +0,0 @@ -From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 10 Sep 2014 22:42:14 +0200 -Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling - -Signed-off-by: John Crispin ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + - arch/mips/lantiq/xway/Makefile | 3 + - arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++ - arch/mips/lantiq/xway/eth_mac.c | 25 ++++ - drivers/net/ethernet/lantiq_etop.c | 6 +- - 5 files changed, 172 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c - create mode 100644 arch/mips/lantiq/xway/eth_mac.c - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -99,5 +99,8 @@ extern __iomem void *ltq_cgu_membase; - extern void ltq_pmu_enable(unsigned int module); - extern void ltq_pmu_disable(unsigned int module); - -+/* allow the ethernet driver to load a flash mapped mac addr */ -+const u8* ltq_get_eth_mac(void); -+ - #endif /* CONFIG_SOC_TYPE_XWAY */ - #endif /* _LTQ_XWAY_H__ */ ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -8,3 +8,6 @@ obj-y += timer.o - endif - - obj-y += vmmc.o -+ -+obj-y += eth_mac.o -+obj-$(CONFIG_PCI) += ath5k_eep.o ---- /dev/null -+++ b/arch/mips/lantiq/xway/ath5k_eep.c -@@ -0,0 +1,135 @@ -+/* -+ * Copyright (C) 2011 Luca Olivetti -+ * Copyright (C) 2011 John Crispin -+ * Copyright (C) 2011 Andrej Vlašić -+ * Copyright (C) 2013 Álvaro Fernández Rojas -+ * Copyright (C) 2013 Daniel Gimpelevich -+ * Copyright (C) 2015 Vittorio Gambaletta -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); -+struct ath5k_platform_data ath5k_pdata; -+static u8 athxk_eeprom_mac[6]; -+ -+static int ath5k_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ dev->dev.platform_data = &ath5k_pdata; -+ return 0; -+} -+ -+static int ath5k_eep_load; -+static int __init of_ath5k_eeprom_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL; -+ int mac_offset; -+ u32 mac_inc = 0; -+ int i; -+ struct mtd_info *the_mtd; -+ size_t flash_readlen; -+ const __be32 *list; -+ const char *part; -+ phandle phandle; -+ -+ list = of_get_property(np, "ath,eep-flash", &i); -+ if (!list || (i != (2 * sizeof(*list)))) -+ return -ENODEV; -+ -+ phandle = be32_to_cpup(list++); -+ if (phandle) -+ mtd_np = of_find_node_by_phandle(phandle); -+ -+ if (!mtd_np) -+ return -ENODEV; -+ -+ part = of_get_property(mtd_np, "label", NULL); -+ if (!part) -+ part = mtd_np->name; -+ -+ the_mtd = get_mtd_device_nm(part); -+ if (IS_ERR(the_mtd)) -+ return -ENODEV; -+ -+ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL); -+ -+ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1, -+ &flash_readlen, (void *) ath5k_pdata.eeprom_data); -+ -+ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { -+ size_t mac_readlen; -+ mtd_read(the_mtd, mac_offset, 6, &mac_readlen, -+ (void *) athxk_eeprom_mac); -+ } -+ put_mtd_device(the_mtd); -+ -+ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) { -+ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); -+ return -ENODEV; -+ } -+ -+ if (of_property_present(np, "ath,eep-swap")) -+ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++) -+ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]); -+ -+ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac()) -+ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac()); -+ -+ if (!is_valid_ether_addr(athxk_eeprom_mac)) { -+ dev_warn(&pdev->dev, "using random mac\n"); -+ eth_random_addr(athxk_eeprom_mac); -+ } -+ -+ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) -+ athxk_eeprom_mac[5] += mac_inc; -+ -+ ath5k_pdata.macaddr = athxk_eeprom_mac; -+ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init; -+ -+ dev_info(&pdev->dev, "loaded ath5k eeprom\n"); -+ -+ return 0; -+} -+ -+static const struct of_device_id ath5k_eeprom_ids[] = { -+ { .compatible = "ath5k,eeprom" }, -+ { } -+}; -+ -+static struct platform_driver ath5k_eeprom_driver = { -+ .driver = { -+ .name = "ath5k,eeprom", -+ .of_match_table = ath5k_eeprom_ids, -+ }, -+}; -+ -+static int __init of_ath5k_eeprom_init(void) -+{ -+ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); -+ -+ if (ret) -+ ath5k_eep_load = 1; -+ -+ return ret; -+} -+ -+static int __init of_ath5k_eeprom_init_late(void) -+{ -+ if (!ath5k_eep_load) -+ return 0; -+ -+ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); -+} -+late_initcall(of_ath5k_eeprom_init_late); -+subsys_initcall(of_ath5k_eeprom_init); ---- /dev/null -+++ b/arch/mips/lantiq/xway/eth_mac.c -@@ -0,0 +1,26 @@ -+/* -+ * Copyright (C) 2012 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+static u8 eth_mac[6]; -+static int eth_mac_set; -+ -+const u8* ltq_get_eth_mac(void) -+{ -+ return eth_mac; -+} -+ -+static int __init setup_ethaddr(char *str) -+{ -+ eth_mac_set = mac_pton(str, eth_mac); -+ return !eth_mac_set; -+} -+early_param("ethaddr", setup_ethaddr); ---- a/arch/mips/pci/fixup-lantiq.c -+++ b/arch/mips/pci/fixup-lantiq.c -@@ -9,12 +9,18 @@ - #include - #include "ifxmips_pci_common.h" - -+int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; -+ - int pcibios_plat_dev_init(struct pci_dev *dev) - { - #ifdef CONFIG_PCIE_LANTIQ - if (pci_find_capability(dev, PCI_CAP_ID_EXP)) - ifx_pcie_bios_plat_dev_init(dev); - #endif -+ -+ if (ltq_pci_plat_dev_init) -+ return ltq_pci_plat_dev_init(dev); -+ - return 0; - } - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -770,7 +770,11 @@ ltq_etop_init(struct net_device *dev) - if (err) - goto err_hw; - -- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); -+ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN); -+ -+ if (!is_valid_ether_addr(mac.sa_data)) -+ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); -+ - if (!is_valid_ether_addr(mac.sa_data)) { - pr_warn("etop: invalid MAC, using random\n"); - eth_random_addr(mac.sa_data); diff --git a/target/linux/lantiq/patches-6.12/042-arch-mips-increase-io_space_limit.patch b/target/linux/lantiq/patches-6.12/042-arch-mips-increase-io_space_limit.patch deleted file mode 100644 index c81222af578..00000000000 --- a/target/linux/lantiq/patches-6.12/042-arch-mips-increase-io_space_limit.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 3 Jun 2016 13:12:20 +0200 -Subject: [PATCH] arch: mips: increase io_space_limit - -this value comes from x86 and breaks some pci devices - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/spaces.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - create mode 100644 arch/mips/include/asm/mach-lantiq/spaces.h - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/spaces.h -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+#ifndef __ASM_MACH_LANTIQ_SPACES_H_ -+#define __ASM_MACH_LANTIQ_SPACES_H_ -+ -+#define IO_SPACE_LIMIT 0xffffffff -+ -+#include -+#endif diff --git a/target/linux/lantiq/patches-6.12/0801-net-ethernet-lantiq-xrx200-handle-EPROBE_DEFER-for-MAC-address.patch b/target/linux/lantiq/patches-6.12/0801-net-ethernet-lantiq-xrx200-handle-EPROBE_DEFER-for-MAC-address.patch deleted file mode 100644 index 0d7ecd9bf81..00000000000 --- a/target/linux/lantiq/patches-6.12/0801-net-ethernet-lantiq-xrx200-handle-EPROBE_DEFER-for-MAC-address.patch +++ /dev/null @@ -1,30 +0,0 @@ -From: Burak Aydos -Date: Mon, 03 Feb 2026 12:00:00 +0300 -Subject: [PATCH] net: ethernet: lantiq: xrx200: handle EPROBE_DEFER for MAC - address - -When the MAC address is provided by an nvmem layout driver (such as -u-boot-env), the nvmem cell may not be available yet when the ethernet -driver probes. In this case, of_get_ethdev_address() returns --EPROBE_DEFER to indicate the driver should be retried later. - -Currently the driver treats all errors equally and falls back to a -random MAC address. Fix this by propagating EPROBE_DEFER so the -driver probe is deferred until the nvmem cell becomes available. - -Signed-off-by: Burak Aydos ---- - drivers/net/ethernet/lantiq_xrx200.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -597,6 +597,8 @@ static int xrx200_probe(struct platform_ - } - - err = of_get_ethdev_address(np, net_dev); -+ if (err == -EPROBE_DEFER) -+ return err; - if (err) - eth_hw_addr_random(net_dev); - diff --git a/target/linux/lantiq/patches-6.12/101-find_active_root.patch b/target/linux/lantiq/patches-6.12/101-find_active_root.patch deleted file mode 100644 index 4741dfb6128..00000000000 --- a/target/linux/lantiq/patches-6.12/101-find_active_root.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 2c82524000cca691c89c9fda251b55ef04eabcb6 Mon Sep 17 00:00:00 2001 -From: Mathias Kresin -Date: Mon, 2 May 2016 18:50:00 +0000 -Subject: [PATCH] find active root - -Signed-off-by: Mathias Kresin ---- - drivers/mtd/parsers/ofpart_core.c | 53 +++++++++++++++++++++++++++++++ - 1 file changed, 53 insertions(+) - ---- a/drivers/mtd/parsers/ofpart_core.c -+++ b/drivers/mtd/parsers/ofpart_core.c -@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d - return of_get_property(pp, "compatible", NULL); - } - -+static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master, -+ loff_t offset) -+{ -+ static uint8_t root_id; -+ int err, len; -+ -+ err = mtd_read(master, offset, 0x01, &len, &root_id); -+ -+ if (mtd_is_bitflip(err) || !err) -+ return &root_id; -+ -+ return NULL; -+} -+ -+static void brnboot_set_active_root_part(struct mtd_partition *pparts, -+ struct device_node **part_nodes, -+ int nr_parts, -+ uint8_t *root_id) -+{ -+ int i; -+ -+ for (i = 0; i < nr_parts; i++) { -+ int part_root_id; -+ -+ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id) -+ && part_root_id == *root_id) { -+ pparts[i].name = "firmware"; -+ break; -+ } -+ } -+} -+ - static int parse_fixed_partitions(struct mtd_info *master, - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) -@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct - struct device_node *pp; - int nr_parts, i, ret = 0; - bool dedicated = true; -+ uint8_t *proot_id = NULL; -+ struct device_node **part_nodes; - - /* Pull of_node from the master device node */ - mtd_node = mtd_get_of_node(master); -@@ -105,6 +139,14 @@ static int parse_fixed_partitions(struct - return -ENOMEM; - } - -+ part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL); -+ if (!part_nodes) { -+ if (dedicated) -+ of_node_put(ofpart_node); -+ kfree(parts); -+ return -ENOMEM; -+ } -+ - i = 0; - for_each_child_of_node(ofpart_node, pp) { - const __be32 *reg; -@@ -173,6 +215,11 @@ static int parse_fixed_partitions(struct - if (of_property_read_bool(pp, "slc-mode")) - parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION; - -+ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector")) -+ proot_id = brnboot_get_selected_root_part(master, parts[i].offset); -+ -+ part_nodes[i] = pp; -+ - i++; - } - -@@ -185,6 +232,11 @@ static int parse_fixed_partitions(struct - if (dedicated) - of_node_put(ofpart_node); - -+ if (proot_id) -+ brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id); -+ -+ kfree(part_nodes); -+ - *pparts = parts; - return nr_parts; - -@@ -197,6 +249,7 @@ ofpart_none: - if (dedicated) - of_node_put(ofpart_node); - kfree(parts); -+ kfree(part_nodes); - return ret; - } - diff --git a/target/linux/lantiq/patches-6.12/102-01-v6.17-MIPS-lantiq-xway-mark-dma_init-as-static.patch b/target/linux/lantiq/patches-6.12/102-01-v6.17-MIPS-lantiq-xway-mark-dma_init-as-static.patch deleted file mode 100644 index e06eff24d10..00000000000 --- a/target/linux/lantiq/patches-6.12/102-01-v6.17-MIPS-lantiq-xway-mark-dma_init-as-static.patch +++ /dev/null @@ -1,28 +0,0 @@ -From cff836f0bb0c53fcf43c12e32ee499cdf7e4a584 Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:15 +0800 -Subject: [PATCH 01/11] MIPS: lantiq: xway: mark dma_init() as static - -Fix the following missing-prototypes build warning: - -arch/mips/lantiq/xway/dma.c:293:1: error: no previous prototype for 'dma_init' [-Werror=missing-prototypes] - 293 | dma_init(void) - | ^~~~~~~~ - -Signed-off-by: Shiji Yang -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/lantiq/xway/dma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/lantiq/xway/dma.c -+++ b/arch/mips/lantiq/xway/dma.c -@@ -289,7 +289,7 @@ static struct platform_driver dma_driver - }, - }; - --int __init -+static int __init - dma_init(void) - { - return platform_driver_register(&dma_driver); diff --git a/target/linux/lantiq/patches-6.12/102-02-v6.17-0002-MIPS-pci-lantiq-marks-pcibios_init-as-static.patch b/target/linux/lantiq/patches-6.12/102-02-v6.17-0002-MIPS-pci-lantiq-marks-pcibios_init-as-static.patch deleted file mode 100644 index b9cefb88fdb..00000000000 --- a/target/linux/lantiq/patches-6.12/102-02-v6.17-0002-MIPS-pci-lantiq-marks-pcibios_init-as-static.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 50162a0c6e014c4954ee4443109b7a4251b377fc Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:19 +0800 -Subject: [PATCH 02/11] MIPS: pci: lantiq: marks pcibios_init() as static - -Fix the following missing-prototypes build warning: - -arch/mips/pci/pci-lantiq.c:239:12: error: no previous prototype for 'pcibios_init' [-Werror=missing-prototypes] - 239 | int __init pcibios_init(void) - | ^~~~~~~~~~~~ - -Signed-off-by: Shiji Yang -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/pci/pci-lantiq.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/pci/pci-lantiq.c -+++ b/arch/mips/pci/pci-lantiq.c -@@ -234,7 +234,7 @@ static struct platform_driver ltq_pci_dr - }, - }; - --int __init pcibios_init(void) -+static int __init pcibios_init(void) - { - int ret = platform_driver_register(<q_pci_driver); - if (ret) diff --git a/target/linux/lantiq/patches-6.12/102-03-v6.17-MIPS-lantiq-xway-mark-dcdc_init-as-static.patch b/target/linux/lantiq/patches-6.12/102-03-v6.17-MIPS-lantiq-xway-mark-dcdc_init-as-static.patch deleted file mode 100644 index d25e0990884..00000000000 --- a/target/linux/lantiq/patches-6.12/102-03-v6.17-MIPS-lantiq-xway-mark-dcdc_init-as-static.patch +++ /dev/null @@ -1,28 +0,0 @@ -From c714186debb45fc88098b666d46cb29ff728e06d Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:16 +0800 -Subject: [PATCH 03/11] MIPS: lantiq: xway: mark dcdc_init() as static - -Fix the following missing-prototypes build warning: - -arch/mips/lantiq/xway/dcdc.c:49:12: error: no previous prototype for 'dcdc_init' [-Werror=missing-prototypes] - 49 | int __init dcdc_init(void) - | ^~~~~~~~~ - -Signed-off-by: Shiji Yang -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/lantiq/xway/dcdc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/lantiq/xway/dcdc.c -+++ b/arch/mips/lantiq/xway/dcdc.c -@@ -46,7 +46,7 @@ static struct platform_driver dcdc_drive - }, - }; - --int __init dcdc_init(void) -+static int __init dcdc_init(void) - { - int ret = platform_driver_register(&dcdc_driver); - diff --git a/target/linux/lantiq/patches-6.12/102-04-v6.17-MIPS-lantiq-irq-fix-misc-missing-prototypes-warnings.patch b/target/linux/lantiq/patches-6.12/102-04-v6.17-MIPS-lantiq-irq-fix-misc-missing-prototypes-warnings.patch deleted file mode 100644 index 2c282d28e22..00000000000 --- a/target/linux/lantiq/patches-6.12/102-04-v6.17-MIPS-lantiq-irq-fix-misc-missing-prototypes-warnings.patch +++ /dev/null @@ -1,43 +0,0 @@ -From d97394bf381eda85d04bec68b72dbc397744fcc3 Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:17 +0800 -Subject: [PATCH 04/11] MIPS: lantiq: irq: fix misc missing-prototypes warnings - -Fix the following build warnings: - -arch/mips/lantiq/irq.c:340:12: error: no previous prototype for 'icu_of_init' [-Werror=missing-prototypes] - 340 | int __init icu_of_init(struct device_node *node, struct device_node *parent) - | ^~~~~~~~~~~ -arch/mips/lantiq/irq.c:418:5: error: no previous prototype for 'get_c0_perfcount_int' [-Werror=missing-prototypes] - 418 | int get_c0_perfcount_int(void) - | ^~~~~~~~~~~~~~~~~~~~ -arch/mips/lantiq/irq.c:424:14: error: no previous prototype for 'get_c0_compare_int' [-Werror=missing-prototypes] - 424 | unsigned int get_c0_compare_int(void) - | ^~~~~~~~~~~~~~~~~~ - -Signed-off-by: Shiji Yang -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/lantiq/irq.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/arch/mips/lantiq/irq.c -+++ b/arch/mips/lantiq/irq.c -@@ -17,6 +17,7 @@ - - #include - #include -+#include - - #include - #include -@@ -337,7 +338,8 @@ static const struct irq_domain_ops irq_d - .map = icu_map, - }; - --int __init icu_of_init(struct device_node *node, struct device_node *parent) -+static int __init -+icu_of_init(struct device_node *node, struct device_node *parent) - { - struct device_node *eiu_node; - struct resource res; diff --git a/target/linux/lantiq/patches-6.12/102-05-v6.17-MIPS-lantiq-xway-mark-ltq_ar9_sys_hz-as-static.patch b/target/linux/lantiq/patches-6.12/102-05-v6.17-MIPS-lantiq-xway-mark-ltq_ar9_sys_hz-as-static.patch deleted file mode 100644 index 47e0a046dea..00000000000 --- a/target/linux/lantiq/patches-6.12/102-05-v6.17-MIPS-lantiq-xway-mark-ltq_ar9_sys_hz-as-static.patch +++ /dev/null @@ -1,28 +0,0 @@ -From de521c6d99d755bbdfa0f1f35299a3e2b02b0dfe Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:14 +0800 -Subject: [PATCH 05/11] MIPS: lantiq: xway: mark ltq_ar9_sys_hz() as static - -Fix the following missing-prototypes warning: - -arch/mips/lantiq/xway/clk.c:77:15: error: no previous prototype for 'ltq_ar9_sys_hz' [-Werror=missing-prototypes] - 77 | unsigned long ltq_ar9_sys_hz(void) - | ^~~~~~~~~~~~~~ - -Signed-off-by: Shiji Yang -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/lantiq/xway/clk.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/lantiq/xway/clk.c -+++ b/arch/mips/lantiq/xway/clk.c -@@ -74,7 +74,7 @@ unsigned long ltq_danube_pp32_hz(void) - return clk; - } - --unsigned long ltq_ar9_sys_hz(void) -+static unsigned long ltq_ar9_sys_hz(void) - { - if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2) - return CLOCK_393M; diff --git a/target/linux/lantiq/patches-6.12/102-06-v6.17-MIPS-lantiq-xway-gptu-mark-gptu_init-as-static.patch b/target/linux/lantiq/patches-6.12/102-06-v6.17-MIPS-lantiq-xway-gptu-mark-gptu_init-as-static.patch deleted file mode 100644 index d6925e55581..00000000000 --- a/target/linux/lantiq/patches-6.12/102-06-v6.17-MIPS-lantiq-xway-gptu-mark-gptu_init-as-static.patch +++ /dev/null @@ -1,28 +0,0 @@ -From e23bd7f95a86c4fc5da5499a3bdc95aa7518f7eb Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:24 +0800 -Subject: [PATCH 06/11] MIPS: lantiq: xway: gptu: mark gptu_init() as static - -Fix the following missing-prototypes warning: - -arch/mips/lantiq/xway/gptu.c:197:12: error: no previous prototype for 'gptu_init' [-Werror=missing-prototypes] - 197 | int __init gptu_init(void) - | ^~~~~~~~~ - -Signed-off-by: Shiji Yang -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/lantiq/xway/gptu.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/lantiq/xway/gptu.c -+++ b/arch/mips/lantiq/xway/gptu.c -@@ -194,7 +194,7 @@ static struct platform_driver dma_driver - }, - }; - --int __init gptu_init(void) -+static int __init gptu_init(void) - { - int ret = platform_driver_register(&dma_driver); - diff --git a/target/linux/lantiq/patches-6.12/102-07-v6.17-MIPS-lantiq-xway-add-prototype-for-ltq_get_cp1_base.patch b/target/linux/lantiq/patches-6.12/102-07-v6.17-MIPS-lantiq-xway-add-prototype-for-ltq_get_cp1_base.patch deleted file mode 100644 index cf75dbb7319..00000000000 --- a/target/linux/lantiq/patches-6.12/102-07-v6.17-MIPS-lantiq-xway-add-prototype-for-ltq_get_cp1_base.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 3f8565be1e848de86c1cc98285ac27a4a9bcb161 Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:18 +0800 -Subject: [PATCH 07/11] MIPS: lantiq: xway: add prototype for - ltq_get_cp1_base() - -ltq_get_cp1_base() is an exported function, we must define -its prototype on header file. Fix warning: - -arch/mips/lantiq/xway/vmmc.c:22:15: error: no previous prototype for 'ltq_get_cp1_base' [-Werror=missing-prototypes] - 22 | unsigned int *ltq_get_cp1_base(void) - | ^~~~~~~~~~~~~~~~ - -Signed-off-by: Shiji Yang -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -102,5 +102,8 @@ extern void ltq_pmu_disable(unsigned int - /* allow the ethernet driver to load a flash mapped mac addr */ - const u8* ltq_get_eth_mac(void); - -+/* VMMC */ -+extern unsigned int *ltq_get_cp1_base(void); -+ - #endif /* CONFIG_SOC_TYPE_XWAY */ - #endif /* _LTQ_XWAY_H__ */ diff --git a/target/linux/lantiq/patches-6.12/102-08-v6.17-MIPS-lantiq-falcon-fix-misc-missing-prototypes-warni.patch b/target/linux/lantiq/patches-6.12/102-08-v6.17-MIPS-lantiq-falcon-fix-misc-missing-prototypes-warni.patch deleted file mode 100644 index 0ef02dff57c..00000000000 --- a/target/linux/lantiq/patches-6.12/102-08-v6.17-MIPS-lantiq-falcon-fix-misc-missing-prototypes-warni.patch +++ /dev/null @@ -1,40 +0,0 @@ -From d97930fbf2d2aa00e7da9be7f128754920486953 Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:20 +0800 -Subject: [PATCH 08/11] MIPS: lantiq: falcon: fix misc missing-prototypes - warnings - -Fix the following build warnings: - -arch/mips/lantiq/falcon/prom.c:39:13: error: no previous prototype for 'ltq_soc_nmi_setup' [-Werror=missing-prototypes] - 39 | void __init ltq_soc_nmi_setup(void) - | ^~~~~~~~~~~~~~~~~ -arch/mips/lantiq/falcon/prom.c:46:13: error: no previous prototype for 'ltq_soc_ejtag_setup' [-Werror=missing-prototypes] - 46 | void __init ltq_soc_ejtag_setup(void) - | ^~~~~~~~~~~~~~~~~~~ - -Signed-off-by: Shiji Yang -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/lantiq/falcon/prom.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/lantiq/falcon/prom.c -+++ b/arch/mips/lantiq/falcon/prom.c -@@ -36,14 +36,14 @@ - #define BOOT_NVEC (BOOT_REG_BASE | 0x04) - #define BOOT_EVEC (BOOT_REG_BASE | 0x08) - --void __init ltq_soc_nmi_setup(void) -+static void __init ltq_soc_nmi_setup(void) - { - extern void (*nmi_handler)(void); - - ltq_w32((unsigned long)&nmi_handler, (void *)BOOT_NVEC); - } - --void __init ltq_soc_ejtag_setup(void) -+static void __init ltq_soc_ejtag_setup(void) - { - extern void (*ejtag_debug_handler)(void); - diff --git a/target/linux/lantiq/patches-6.12/102-09-v6.17-MIPS-lantiq-falcon-sysctrl-remove-unused-falcon_trig.patch b/target/linux/lantiq/patches-6.12/102-09-v6.17-MIPS-lantiq-falcon-sysctrl-remove-unused-falcon_trig.patch deleted file mode 100644 index abe35805134..00000000000 --- a/target/linux/lantiq/patches-6.12/102-09-v6.17-MIPS-lantiq-falcon-sysctrl-remove-unused-falcon_trig.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 01432b513638b0ffb080aa211b5b7f7ecf316f24 Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:21 +0800 -Subject: [PATCH 09/11] MIPS: lantiq: falcon: sysctrl: remove unused - falcon_trigger_hrst() - -This is a defined but unused function. Fix warning: - -arch/mips/lantiq/falcon/sysctrl.c:75:6: error: no previous prototype for 'falcon_trigger_hrst' [-Werror=missing-prototypes] - 75 | void falcon_trigger_hrst(int level) - | ^~~~~~~~~~~~~~~~~~~ - -Signed-off-by: Shiji Yang -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/lantiq/falcon/sysctrl.c | 5 ----- - 1 file changed, 5 deletions(-) - ---- a/arch/mips/lantiq/falcon/sysctrl.c -+++ b/arch/mips/lantiq/falcon/sysctrl.c -@@ -72,11 +72,6 @@ - static void __iomem *sysctl_membase[3], *status_membase; - void __iomem *ltq_sys1_membase, *ltq_ebu_membase; - --void falcon_trigger_hrst(int level) --{ -- sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC); --} -- - static inline void sysctl_wait(struct clk *clk, - unsigned int test, unsigned int reg) - { diff --git a/target/linux/lantiq/patches-6.12/102-10-v6.17-MIPS-lantiq-falcon-sysctrl-add-missing-header-prom.h.patch b/target/linux/lantiq/patches-6.12/102-10-v6.17-MIPS-lantiq-falcon-sysctrl-add-missing-header-prom.h.patch deleted file mode 100644 index 5b137a25ac2..00000000000 --- a/target/linux/lantiq/patches-6.12/102-10-v6.17-MIPS-lantiq-falcon-sysctrl-add-missing-header-prom.h.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 8a6156bd26240177e710fd8623bc2eb0ef0092cf Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:22 +0800 -Subject: [PATCH 10/11] MIPS: lantiq: falcon: sysctrl: add missing header - prom.h - -"prom.h" includes the prototype of ltq_soc_init(). Fix warning: - -arch/mips/lantiq/falcon/sysctrl.c:185:13: error: no previous prototype for 'ltq_soc_init' [-Werror=missing-prototypes] - 185 | void __init ltq_soc_init(void) - | ^~~~~~~~~~~~ - -Signed-off-by: Shiji Yang -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/lantiq/falcon/sysctrl.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/mips/lantiq/falcon/sysctrl.c -+++ b/arch/mips/lantiq/falcon/sysctrl.c -@@ -14,6 +14,7 @@ - #include - - #include "../clk.h" -+#include "../prom.h" - - /* infrastructure control register */ - #define SYS1_INFRAC 0x00bc diff --git a/target/linux/lantiq/patches-6.12/102-14-v6.17-pinctrl-xway-statify-xway_pinconf_group_set.patch b/target/linux/lantiq/patches-6.12/102-14-v6.17-pinctrl-xway-statify-xway_pinconf_group_set.patch deleted file mode 100644 index 5e1113b8796..00000000000 --- a/target/linux/lantiq/patches-6.12/102-14-v6.17-pinctrl-xway-statify-xway_pinconf_group_set.patch +++ /dev/null @@ -1,31 +0,0 @@ -From e62acaef5d3b67648a7161b329ae8a5afce8c682 Mon Sep 17 00:00:00 2001 -From: Bartosz Golaszewski -Date: Thu, 12 Jun 2025 15:15:16 +0200 -Subject: [PATCH] pinctrl: xway: statify xway_pinconf_group_set() - -This function is not exported and is only used locally. Make it static. - -Signed-off-by: Bartosz Golaszewski -Link: https://lore.kernel.org/20250612-gpiochip-set-rv-pinctrl-remaining-v1-7-556b0a530cd4@linaro.org -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-xway.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/pinctrl/pinctrl-xway.c -+++ b/drivers/pinctrl/pinctrl-xway.c -@@ -1228,10 +1228,10 @@ static int xway_pinconf_set(struct pinct - return 0; - } - --int xway_pinconf_group_set(struct pinctrl_dev *pctldev, -- unsigned selector, -- unsigned long *configs, -- unsigned num_configs) -+static int xway_pinconf_group_set(struct pinctrl_dev *pctldev, -+ unsigned int selector, -+ unsigned long *configs, -+ unsigned int num_configs) - { - struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); - int i, ret = 0; diff --git a/target/linux/lantiq/patches-6.12/102-15-v6.17-pinctrl-falcon-mark-pinctrl_falcon_init-as-static.patch b/target/linux/lantiq/patches-6.12/102-15-v6.17-pinctrl-falcon-mark-pinctrl_falcon_init-as-static.patch deleted file mode 100644 index 74586c6096d..00000000000 --- a/target/linux/lantiq/patches-6.12/102-15-v6.17-pinctrl-falcon-mark-pinctrl_falcon_init-as-static.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 4b443bbcd113cad6ec041a4f9f09179e2342ad60 Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:28 +0800 -Subject: [PATCH] pinctrl: falcon: mark pinctrl_falcon_init() as static - -Fix the following missing-prototypes build warning: - -drivers/pinctrl/pinctrl-falcon.c:508:12: error: no previous prototype for 'pinctrl_falcon_init' [-Werror=missing-prototypes] - 508 | int __init pinctrl_falcon_init(void) - | ^~~~~~~~~~~~~~~~~~~ - -Signed-off-by: Shiji Yang -Link: https://lore.kernel.org/OSBPR01MB167014AF54EF9818CB98C83BBC72A@OSBPR01MB1670.jpnprd01.prod.outlook.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-falcon.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/pinctrl/pinctrl-falcon.c -+++ b/drivers/pinctrl/pinctrl-falcon.c -@@ -505,7 +505,7 @@ static struct platform_driver pinctrl_fa - }, - }; - --int __init pinctrl_falcon_init(void) -+static int __init pinctrl_falcon_init(void) - { - return platform_driver_register(&pinctrl_falcon_driver); - } diff --git a/target/linux/lantiq/patches-6.12/102-16-v6.17-spi-falcon-mark-falcon_sflash_xfer-as-static.patch b/target/linux/lantiq/patches-6.12/102-16-v6.17-spi-falcon-mark-falcon_sflash_xfer-as-static.patch deleted file mode 100644 index f9b643b79dc..00000000000 --- a/target/linux/lantiq/patches-6.12/102-16-v6.17-spi-falcon-mark-falcon_sflash_xfer-as-static.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 5fc2c383125c2b4b6037e02ad8796b776b25e6d0 Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Wed, 18 Jun 2025 22:53:29 +0800 -Subject: [PATCH] spi: falcon: mark falcon_sflash_xfer() as static - -Fix the following missing-prototypes build warning: - -drivers/spi/spi-falcon.c:97:5: error: no previous prototype for 'falcon_sflash_xfer' [-Werror=missing-prototypes] - 97 | int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t, - | ^~~~~~~~~~~~~~~~~~ - -Signed-off-by: Shiji Yang -Link: https://patch.msgid.link/OSBPR01MB16705BE87E549B6210CD6BCABC72A@OSBPR01MB1670.jpnprd01.prod.outlook.com -Signed-off-by: Mark Brown ---- - drivers/spi/spi-falcon.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/spi/spi-falcon.c -+++ b/drivers/spi/spi-falcon.c -@@ -94,8 +94,9 @@ struct falcon_sflash { - struct spi_controller *host; - }; - --int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t, -- unsigned long flags) -+static int -+falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t, -+ unsigned long flags) - { - struct device *dev = &spi->dev; - struct falcon_sflash *priv = spi_controller_get_devdata(spi->controller); diff --git a/target/linux/lantiq/patches-6.12/152-lantiq-VPE.patch b/target/linux/lantiq/patches-6.12/152-lantiq-VPE.patch deleted file mode 100644 index 66e1cd8ea71..00000000000 --- a/target/linux/lantiq/patches-6.12/152-lantiq-VPE.patch +++ /dev/null @@ -1,187 +0,0 @@ -From 4d48a3d1ef6f8d036bd926e3c1f70b56fcc679b2 Mon Sep 17 00:00:00 2001 -From: Stefan Koch -Date: Thu, 20 Oct 2016 21:32:00 +0200 -Subject: [PATCH] lantiq: vpe - -Signed-off-by: Stefan Koch ---- - arch/mips/Kconfig | 6 ++++ - arch/mips/include/asm/mipsmtregs.h | 5 ++++ - arch/mips/include/asm/vpe.h | 9 ++++++ - arch/mips/kernel/vpe-mt.c | 47 ++++++++++++++++++++++++++++++ - arch/mips/kernel/vpe.c | 35 ++++++++++++++++++++++ - arch/mips/lantiq/prom.c | 4 +++ - 6 files changed, 106 insertions(+) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -2251,6 +2251,12 @@ config MIPS_VPE_LOADER - Includes a loader for loading an elf relocatable object - onto another VPE and running it. - -+config IFX_VPE_EXT -+ bool "IFX APRP Extensions" -+ depends on MIPS_VPE_LOADER -+ help -+ IFX included extensions in APRP -+ - config MIPS_VPE_LOADER_MT - bool - default "y" ---- a/arch/mips/include/asm/mipsmtregs.h -+++ b/arch/mips/include/asm/mipsmtregs.h -@@ -31,6 +31,9 @@ - #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) - #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) - -+#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) -+#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) -+ - #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) - #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) - -@@ -429,6 +432,8 @@ do { \ - #define write_vpe_c0_vpeconf0(val) mttc0($1, 2, val) - #define read_vpe_c0_vpeconf1() mftc0($1, 3) - #define write_vpe_c0_vpeconf1(val) mttc0($1, 3, val) -+#define read_vpe_c0_vpeopt() mftc0($1, 7) -+#define write_vpe_c0_vpeopt(val) mttc0($1, 7, val) - #define read_vpe_c0_count() mftc0($9, 0) - #define write_vpe_c0_count(val) mttc0($9, 0, val) - #define read_vpe_c0_status() mftc0($12, 0) ---- a/arch/mips/include/asm/vpe.h -+++ b/arch/mips/include/asm/vpe.h -@@ -126,5 +126,13 @@ int vpe_start(void *vpe, unsigned long s - int vpe_stop(void *vpe); - int vpe_free(void *vpe); - #endif /* CONFIG_MIPS_VPE_LOADER_MT */ -+ -+/* For the explanation of the APIs please refer the section "MT APRP Kernel -+ * Programming" in AR9 SW Architecture Specification -+ */ -+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags); -+int32_t vpe1_sw_stop(uint32_t flags); -+uint32_t vpe1_get_load_addr(uint32_t flags); -+uint32_t vpe1_get_max_mem(uint32_t flags); - - #endif /* _ASM_VPE_H */ ---- a/arch/mips/kernel/vpe-mt.c -+++ b/arch/mips/kernel/vpe-mt.c -@@ -414,6 +414,8 @@ int __init vpe_module_init(void) - } - - v->ntcs = hw_tcs - aprp_cpu_index(); -+ write_tc_c0_tcbind((read_tc_c0_tcbind() & -+ ~TCBIND_CURVPE) | 1); - - /* add the tc to the list of this vpe's tc's. */ - list_add(&t->tc, &v->tc); -@@ -517,3 +519,47 @@ void __exit vpe_module_exit(void) - release_vpe(v); - } - } -+ -+#ifdef CONFIG_IFX_VPE_EXT -+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags) -+{ -+ enum vpe_state state; -+ struct vpe *v = get_vpe(tclimit); -+ struct vpe_notifications *not; -+ -+ if (tcmask || flags) { -+ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n"); -+ return -1; -+ } -+ -+ state = xchg(&v->state, VPE_STATE_INUSE); -+ if (state != VPE_STATE_UNUSED) { -+ vpe_stop(v); -+ -+ list_for_each_entry(not, &v->notify, list) { -+ not->stop(tclimit); -+ } -+ } -+ -+ v->__start = (unsigned long)sw_start_addr; -+ -+ if (!vpe_run(v)) { -+ pr_debug("VPE loader: VPE1 running successfully\n"); -+ return 0; -+ } -+ return -1; -+} -+EXPORT_SYMBOL(vpe1_sw_start); -+ -+int32_t vpe1_sw_stop(uint32_t flags) -+{ -+ struct vpe *v = get_vpe(tclimit); -+ -+ if (!vpe_free(v)) { -+ pr_debug("RP Stopped\n"); -+ return 0; -+ } else -+ return -1; -+} -+EXPORT_SYMBOL(vpe1_sw_stop); -+#endif ---- a/arch/mips/kernel/vpe.c -+++ b/arch/mips/kernel/vpe.c -@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = { - .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) - }; - -+#ifdef CONFIG_IFX_VPE_EXT -+unsigned int vpe1_load_addr; -+ -+static int __init load_address(char *str) -+{ -+ get_option(&str, &vpe1_load_addr); -+ return 1; -+} -+__setup("vpe1_load_addr=", load_address); -+ -+static unsigned int vpe1_mem; -+static int __init vpe1mem(char *str) -+{ -+ vpe1_mem = memparse(str, &str); -+ return 1; -+} -+__setup("vpe1_mem=", vpe1mem); -+ -+uint32_t vpe1_get_load_addr(uint32_t flags) -+{ -+ return vpe1_load_addr; -+} -+EXPORT_SYMBOL(vpe1_get_load_addr); -+ -+uint32_t vpe1_get_max_mem(uint32_t flags) -+{ -+ if (!vpe1_mem) -+ return P_SIZE; -+ else -+ return vpe1_mem; -+} -+EXPORT_SYMBOL(vpe1_get_max_mem); -+ -+#endif -+ - /* get the vpe associated with this minor */ - struct vpe *get_vpe(int minor) - { ---- a/arch/mips/lantiq/prom.c -+++ b/arch/mips/lantiq/prom.c -@@ -36,10 +36,14 @@ extern const struct plat_smp_ops vsmp_sm - static struct plat_smp_ops lantiq_smp_ops; - #endif - -+/* for Multithreading (APRP), vpe.c will use it */ -+unsigned long cp0_memsize; -+ - const char *get_system_type(void) - { - return soc_info.sys_type; - } -+EXPORT_SYMBOL(ltq_soc_type); - - int ltq_soc_type(void) - { diff --git a/target/linux/lantiq/patches-6.12/154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-6.12/154-lantiq-pci-bar11mask-fix.patch deleted file mode 100644 index 9214f786d7b..00000000000 --- a/target/linux/lantiq/patches-6.12/154-lantiq-pci-bar11mask-fix.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 3c92a781de062064e36b867c0ab22f9aba48f3d3 Mon Sep 17 00:00:00 2001 -From: Eddi De Pieri -Date: Tue, 8 Nov 2016 17:38:00 +0100 -Subject: [PATCH] lantiq: pci: bar11mask fix - -Signed-off-by: Eddi De Pieri ---- - arch/mips/pci/pci-lantiq.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/arch/mips/pci/pci-lantiq.c -+++ b/arch/mips/pci/pci-lantiq.c -@@ -59,6 +59,8 @@ - #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) - #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) - -+extern u32 max_low_pfn; -+ - __iomem void *ltq_pci_mapped_cfg; - static __iomem void *ltq_pci_membase; - -@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi - u32 mem, bar11mask; - - /* BAR11MASK value depends on available memory on system. */ -- mem = get_num_physpages() * PAGE_SIZE; -- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; -+ mem = max_low_pfn << PAGE_SHIFT; -+ bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8; - - return bar11mask; - } diff --git a/target/linux/lantiq/patches-6.12/155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-6.12/155-lantiq-VPE-nosmp.patch deleted file mode 100644 index 6426ee717ba..00000000000 --- a/target/linux/lantiq/patches-6.12/155-lantiq-VPE-nosmp.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 07ce9e9bc4dcd5ac4728e587901112eef95bbe7b Mon Sep 17 00:00:00 2001 -From: Stefan Koch -Date: Mon, 13 Mar 2017 23:42:00 +0100 -Subject: [PATCH] lantiq: vpe nosmp - -Signed-off-by: Stefan Koch ---- - arch/mips/kernel/vpe-mt.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/arch/mips/kernel/vpe-mt.c -+++ b/arch/mips/kernel/vpe-mt.c -@@ -130,7 +130,10 @@ int vpe_run(struct vpe *v) - * kernels need to turn it on, even if that wasn't the pre-dvpe() state. - */ - #ifdef CONFIG_SMP -- evpe(vpeflags); -+ if (!setup_max_cpus) /* nosmp is set */ -+ evpe(EVPE_ENABLE); -+ else -+ evpe(vpeflags); - #else - evpe(EVPE_ENABLE); - #endif diff --git a/target/linux/lantiq/patches-6.12/160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-6.12/160-owrt-lantiq-multiple-flash.patch deleted file mode 100644 index 652be939fdb..00000000000 --- a/target/linux/lantiq/patches-6.12/160-owrt-lantiq-multiple-flash.patch +++ /dev/null @@ -1,224 +0,0 @@ -From ebaae1cd68cd79c7eee67c9c5c0fa45809e84525 Mon Sep 17 00:00:00 2001 -From: Maikel Bloemendal -Date: Fri, 14 Nov 2014 17:06:00 +0000 -Subject: [PATCH] owrt: lantiq: multiple flash - -Concatenate multiple flash chips for lantiq-flash. - -Signed-off-by: Maikel Bloemendal ---- - drivers/mtd/maps/lantiq-flash.c | 168 +++++++++++++++++++++----------- - 1 file changed, 109 insertions(+), 59 deletions(-) - ---- a/drivers/mtd/maps/lantiq-flash.c -+++ b/drivers/mtd/maps/lantiq-flash.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -36,13 +37,16 @@ enum { - LTQ_NOR_NORMAL - }; - -+#define MAX_RESOURCES 4 -+ - struct ltq_mtd { -- struct resource *res; -- struct mtd_info *mtd; -- struct map_info *map; -+ struct mtd_info *mtd[MAX_RESOURCES]; -+ struct mtd_info *cmtd; -+ struct map_info map[MAX_RESOURCES]; - }; - - static const char ltq_map_name[] = "ltq_nor"; -+static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL }; - - static map_word - ltq_read16(struct map_info *map, unsigned long adr) -@@ -105,12 +109,41 @@ ltq_copy_to(struct map_info *map, unsign - spin_unlock_irqrestore(&ebu_lock, flags); - } - -+static void ltq_mtd_remove(struct platform_device *pdev) -+{ -+ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); -+ int i; -+ -+ if (ltq_mtd == NULL) -+ return; -+ -+ if (ltq_mtd->cmtd) { -+ mtd_device_unregister(ltq_mtd->cmtd); -+ if (ltq_mtd->cmtd != ltq_mtd->mtd[0]) -+ mtd_concat_destroy(ltq_mtd->cmtd); -+ } -+ -+ for (i = 0; i < MAX_RESOURCES; i++) { -+ if (ltq_mtd->mtd[i] != NULL) -+ map_destroy(ltq_mtd->mtd[i]); -+ } -+ -+ kfree(ltq_mtd); -+} -+ - static int - ltq_mtd_probe(struct platform_device *pdev) - { - struct ltq_mtd *ltq_mtd; - struct cfi_private *cfi; -- int err; -+ int err = 0; -+ int i; -+ int devices_found = 0; -+ -+ static const char *rom_probe_types[] = { -+ "cfi_probe", "jedec_probe", NULL -+ }; -+ const char **type; - - ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL); - if (!ltq_mtd) -@@ -118,68 +151,89 @@ ltq_mtd_probe(struct platform_device *pd - - platform_set_drvdata(pdev, ltq_mtd); - -- ltq_mtd->map->virt = devm_platform_get_and_ioremap_resource(pdev, 0, <q_mtd->res); -- if (IS_ERR(ltq_mtd->map->virt)) -- return PTR_ERR(ltq_mtd->map->virt); -- -- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), -- GFP_KERNEL); -- if (!ltq_mtd->map) -- return -ENOMEM; -- -- if (of_property_present(pdev->dev.of_node, "lantiq,noxip")) -- ltq_mtd->map->phys = NO_XIP; -- else -- ltq_mtd->map->phys = ltq_mtd->res->start; -- ltq_mtd->res->start; -- ltq_mtd->map->size = resource_size(ltq_mtd->res); -- -- ltq_mtd->map->name = ltq_map_name; -- ltq_mtd->map->bankwidth = 2; -- ltq_mtd->map->read = ltq_read16; -- ltq_mtd->map->write = ltq_write16; -- ltq_mtd->map->copy_from = ltq_copy_from; -- ltq_mtd->map->copy_to = ltq_copy_to; -- -- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; -- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); -- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; -- -- if (!ltq_mtd->mtd) { -- dev_err(&pdev->dev, "probing failed\n"); -- return -ENXIO; -+ for (i = 0; i < pdev->num_resources; i++) { -+ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n", -+ (unsigned long long)resource_size(&pdev->resource[i]), -+ (unsigned long long)pdev->resource[i].start); -+ -+ if (!devm_request_mem_region(&pdev->dev, -+ pdev->resource[i].start, -+ resource_size(&pdev->resource[i]), -+ dev_name(&pdev->dev))) { -+ dev_err(&pdev->dev, "Could not reserve memory region\n"); -+ return -ENOMEM; -+ } -+ -+ ltq_mtd->map[i].name = ltq_map_name; -+ ltq_mtd->map[i].bankwidth = 2; -+ ltq_mtd->map[i].read = ltq_read16; -+ ltq_mtd->map[i].write = ltq_write16; -+ ltq_mtd->map[i].copy_from = ltq_copy_from; -+ ltq_mtd->map[i].copy_to = ltq_copy_to; -+ -+ if (of_property_present(pdev->dev.of_node, "lantiq,noxip")) -+ ltq_mtd->map[i].phys = NO_XIP; -+ else -+ ltq_mtd->map[i].phys = pdev->resource[i].start; -+ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]); -+ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start, -+ ltq_mtd->map[i].size); -+ if (IS_ERR(ltq_mtd->map[i].virt)) -+ return PTR_ERR(ltq_mtd->map[i].virt); -+ -+ if (ltq_mtd->map[i].virt == NULL) { -+ dev_err(&pdev->dev, "Failed to ioremap flash region\n"); -+ err = PTR_ERR(ltq_mtd->map[i].virt); -+ goto err_out; -+ } -+ -+ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING; -+ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++) -+ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]); -+ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL; -+ -+ if (!ltq_mtd->mtd[i]) { -+ dev_err(&pdev->dev, "probing failed\n"); -+ return -ENXIO; -+ } else { -+ devices_found++; -+ } -+ -+ ltq_mtd->mtd[i]->owner = THIS_MODULE; -+ ltq_mtd->mtd[i]->dev.parent = &pdev->dev; -+ -+ cfi = ltq_mtd->map[i].fldrv_priv; -+ cfi->addr_unlock1 ^= 1; -+ cfi->addr_unlock2 ^= 1; - } - -- ltq_mtd->mtd->dev.parent = &pdev->dev; -- mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node); -+ if (devices_found == 1) { -+ ltq_mtd->cmtd = ltq_mtd->mtd[0]; -+ } else if (devices_found > 1) { -+ /* -+ * We detected multiple devices. Concatenate them together. -+ */ -+ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev)); -+ if (ltq_mtd->cmtd == NULL) -+ err = -ENXIO; -+ } - -- cfi = ltq_mtd->map->fldrv_priv; -- cfi->addr_unlock1 ^= 1; -- cfi->addr_unlock2 ^= 1; -+ ltq_mtd->cmtd->dev.parent = &pdev->dev; -+ mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node); - -- err = mtd_device_register(ltq_mtd->mtd, NULL, 0); -+ err = mtd_device_register(ltq_mtd->cmtd, NULL, 0); - if (err) { - dev_err(&pdev->dev, "failed to add partitions\n"); -- goto err_destroy; -+ goto err_out; - } - - return 0; - --err_destroy: -- map_destroy(ltq_mtd->mtd); -+err_out: -+ ltq_mtd_remove(pdev); - return err; - } - --static void ltq_mtd_remove(struct platform_device *pdev) --{ -- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); -- -- if (ltq_mtd && ltq_mtd->mtd) { -- mtd_device_unregister(ltq_mtd->mtd); -- map_destroy(ltq_mtd->mtd); -- } --} -- - static const struct of_device_id ltq_mtd_match[] = { - { .compatible = "lantiq,nor" }, - {}, diff --git a/target/linux/lantiq/patches-6.12/200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch b/target/linux/lantiq/patches-6.12/200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch deleted file mode 100644 index 65164f6ac2e..00000000000 --- a/target/linux/lantiq/patches-6.12/200-MIPS-lantiq-xway-vmmc-use-platform_get_irq-to-get-ir.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 2b873c59fd313aee57864f96d64a228f2ea7c208 Mon Sep 17 00:00:00 2001 -From: Martin Schiller -Date: Mon, 13 May 2024 10:42:24 +0200 -Subject: [PATCH] MIPS: lantiq: xway: vmmc: use platform_get_irq to get irqs - from dts - -Let's fetch the irqs from the dts here and expose them to the voice -driver like it is done for the cp1 base memory. - -ToDo: -Maybe it is possible to drop this driver completely and merge this -handling to the voice driver. - -Signed-off-by: Martin Schiller ---- - arch/mips/lantiq/xway/vmmc.c | 53 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 53 insertions(+) - ---- a/arch/mips/lantiq/xway/vmmc.c -+++ b/arch/mips/lantiq/xway/vmmc.c -@@ -15,6 +15,10 @@ - - static unsigned int *cp1_base; - -+static int ad0_irq; -+static int ad1_irq; -+static int vc_irq[4]; -+ - unsigned int *ltq_get_cp1_base(void) - { - if (!cp1_base) -@@ -24,6 +28,33 @@ unsigned int *ltq_get_cp1_base(void) - } - EXPORT_SYMBOL(ltq_get_cp1_base); - -+unsigned int ltq_get_mps_ad0_irq(void) -+{ -+ if (!ad0_irq) -+ panic("no ad0 irq was set\n"); -+ -+ return ad0_irq; -+} -+EXPORT_SYMBOL(ltq_get_mps_ad0_irq); -+ -+unsigned int ltq_get_mps_ad1_irq(void) -+{ -+ if (!ad1_irq) -+ panic("no ad1 irq was set\n"); -+ -+ return ad1_irq; -+} -+EXPORT_SYMBOL(ltq_get_mps_ad1_irq); -+ -+unsigned int ltq_get_mps_vc_irq(int idx) -+{ -+ if (!vc_irq[idx]) -+ panic("no vc%d irq was set\n", idx); -+ -+ return vc_irq[idx]; -+} -+EXPORT_SYMBOL(ltq_get_mps_vc_irq); -+ - static int vmmc_probe(struct platform_device *pdev) - { - #define CP1_SIZE (1 << 20) -@@ -31,11 +62,33 @@ static int vmmc_probe(struct platform_de - int gpio_count; - dma_addr_t dma; - int error; -+ int i; - - cp1_base = - (void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE, - &dma, GFP_KERNEL)); - -+ ad0_irq = platform_get_irq(pdev, 4); -+ if (ad0_irq < 0) { -+ dev_err(&pdev->dev, "failed to get MPS AD0 irq: %d\n", ad0_irq); -+ return ad0_irq; -+ } -+ -+ ad1_irq = platform_get_irq(pdev, 5); -+ if (ad1_irq < 0) { -+ dev_err(&pdev->dev, "failed to get MPS AD1 irq: %d\n", ad1_irq); -+ return ad1_irq; -+ } -+ -+ for (i = 0; i < 4; i++) { -+ vc_irq[i] = platform_get_irq(pdev, i); -+ if (vc_irq[i] < 0) { -+ dev_err(&pdev->dev, "failed to get MPS VC%d irq: %d\n", -+ i, vc_irq[i]); -+ return vc_irq[i]; -+ } -+ } -+ - gpio_count = gpiod_count(&pdev->dev, NULL); - while (gpio_count > 0) { - gpio = devm_gpiod_get_index(&pdev->dev, ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -104,6 +104,9 @@ const u8* ltq_get_eth_mac(void); - - /* VMMC */ - extern unsigned int *ltq_get_cp1_base(void); -+extern unsigned int ltq_get_mps_ad0_irq(void); -+extern unsigned int ltq_get_mps_ad1_irq(void); -+extern unsigned int ltq_get_mps_vc_irq(int idx); - - #endif /* CONFIG_SOC_TYPE_XWAY */ - #endif /* _LTQ_XWAY_H__ */ diff --git a/target/linux/lantiq/patches-6.12/300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-6.12/300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch deleted file mode 100644 index 7abe1fbbeb3..00000000000 --- a/target/linux/lantiq/patches-6.12/300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 5e93c85ac3e5626d1aa7e7f9c0a008b2a4224f04 Mon Sep 17 00:00:00 2001 -From: Matti Laakso -Date: Sat, 14 Feb 2015 20:48:00 +0000 -Subject: [PATCH] MTD: cfi_cmdset_0001: disable buffered writes - -Signed-off-by: Matti Laakso ---- - drivers/mtd/chips/cfi_cmdset_0001.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/chips/cfi_cmdset_0001.c -+++ b/drivers/mtd/chips/cfi_cmdset_0001.c -@@ -40,7 +40,7 @@ - /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ - - // debugging, turns off buffer write mode if set to 1 --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - /* Intel chips */ - #define I82802AB 0x00ad diff --git a/target/linux/lantiq/patches-6.12/301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-6.12/301-xrx200-add-gphy-clk-src-device-tree-binding.patch deleted file mode 100644 index 459e415e1bc..00000000000 --- a/target/linux/lantiq/patches-6.12/301-xrx200-add-gphy-clk-src-device-tree-binding.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 5502ef9d40ab20b2ac683660d1565a7c4968bcc8 Mon Sep 17 00:00:00 2001 -From: Mathias Kresin -Date: Mon, 2 May 2016 18:50:00 +0000 -Subject: [PATCH] xrx200: add gphy clk src device tree binding - -Signed-off-by: Mathias Kresin ---- - arch/mips/lantiq/xway/sysctrl.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -439,6 +439,20 @@ static void clkdev_add_clkout(void) - } - } - -+static void set_phy_clock_source(struct device_node *np_cgu) -+{ -+ u32 phy_clk_src, ifcc; -+ -+ if (!np_cgu) -+ return; -+ -+ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) -+ return; -+ -+ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); -+ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); -+} -+ - /* bring up all register ranges that we need for basic system control */ - void __init ltq_soc_init(void) - { -@@ -608,4 +622,6 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); - } - usb_set_clock(); -+ -+ set_phy_clock_source(np_cgu); - } diff --git a/target/linux/lantiq/patches-6.12/302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch b/target/linux/lantiq/patches-6.12/302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch deleted file mode 100644 index 1eadb56dd8b..00000000000 --- a/target/linux/lantiq/patches-6.12/302-mtd-cfi_cmdset_0001-Disable-write-buffer-functions-i.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 118fe2c88b35482711adeee0d8758bddfe958701 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Sat, 6 May 2023 14:32:00 +0200 -Subject: [PATCH] mtd: cfi_cmdset_0001: Disable write buffer functions if - FORCE_WORD_WRITE is 1 - -Some write buffer functions are not used when FORCE_WORD_WRITE is set to 1. -So the compile warning messages are output if FORCE_WORD_WRITE is 1. To -resolve this disable the write buffer functions if FORCE_WORD_WRITE is 1. - -This is similar fix to: 557c759036fc3976a5358cef23e65a263853b93f. - -Signed-off-by: Aleksander Jan Bajkowski ---- - drivers/mtd/chips/cfi_cmdset_0001.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/mtd/chips/cfi_cmdset_0001.c -+++ b/drivers/mtd/chips/cfi_cmdset_0001.c -@@ -62,8 +62,10 @@ - - static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); - static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); -+#if !FORCE_WORD_WRITE - static int cfi_intelext_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); - static int cfi_intelext_writev(struct mtd_info *, const struct kvec *, unsigned long, loff_t, size_t *); -+#endif - static int cfi_intelext_erase_varsize(struct mtd_info *, struct erase_info *); - static void cfi_intelext_sync (struct mtd_info *); - static int cfi_intelext_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); -@@ -305,6 +307,7 @@ static void fixup_use_point(struct mtd_i - } - } - -+#if !FORCE_WORD_WRITE - static void fixup_use_write_buffers(struct mtd_info *mtd) - { - struct map_info *map = mtd->priv; -@@ -315,6 +318,7 @@ static void fixup_use_write_buffers(stru - mtd->_writev = cfi_intelext_writev; - } - } -+#endif /* !FORCE_WORD_WRITE */ - - /* - * Some chips power-up with all sectors locked by default. -@@ -1720,6 +1724,7 @@ static int cfi_intelext_write_words (str - } - - -+#if !FORCE_WORD_WRITE - static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, - unsigned long adr, const struct kvec **pvec, - unsigned long *pvec_seek, int len) -@@ -1948,6 +1953,7 @@ static int cfi_intelext_write_buffers (s - - return cfi_intelext_writev(mtd, &vec, 1, to, retlen); - } -+#endif /* !FORCE_WORD_WRITE */ - - static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, - unsigned long adr, int len, void *thunk) diff --git a/target/linux/lantiq/patches-6.12/400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch b/target/linux/lantiq/patches-6.12/400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch deleted file mode 100644 index edf06268609..00000000000 --- a/target/linux/lantiq/patches-6.12/400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 416f25a948d11ef15733f2e31658d31b5cc7bef6 Mon Sep 17 00:00:00 2001 -From: Thomas Nixon -Date: Sun, 26 Mar 2023 11:08:49 +0100 -Subject: [PATCH] mtd: rawnand: xway: don't yield while holding spinlock - -The nand driver normally while waiting for the device to become ready; -this is normally fine, but xway_nand holds the ebu_lock spinlock, and -this can cause lockups if other threads which use ebu_lock are -interleaved. Fix this by waiting instead of polling. - -This mainly showed up as crashes in ath9k_pci_owl_loader (see -https://github.com/openwrt/openwrt/issues/9829 ), but turning on -spinlock debugging shows this happening in other places too. - -This doesn't seem to measurably impact boot time. - -Signed-off-by: Thomas Nixon ---- - drivers/mtd/nand/raw/xway_nand.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/raw/xway_nand.c -+++ b/drivers/mtd/nand/raw/xway_nand.c -@@ -175,7 +175,13 @@ static void xway_cmd_ctrl(struct nand_ch - - static int xway_dev_ready(struct nand_chip *chip) - { -- return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD; -+ /* -+ * wait until ready, as otherwise the driver will yield in nand_wait or -+ * nand_wait_ready, which is a bad idea when we're holding ebu_lock -+ */ -+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) -+ cpu_relax(); -+ return 1; - } - - static unsigned char xway_read_byte(struct nand_chip *chip) diff --git a/target/linux/lantiq/patches-6.12/701-NET-lantiq-etop-of-mido.patch b/target/linux/lantiq/patches-6.12/701-NET-lantiq-etop-of-mido.patch deleted file mode 100644 index d4c7b4ff23f..00000000000 --- a/target/linux/lantiq/patches-6.12/701-NET-lantiq-etop-of-mido.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 -From: Johann Neuhauser -Date: Thu, 17 May 2018 19:12:35 +0200 -Subject: [PATCH] net: lantiq_etop: of mdio - -Signed-off-by: Johann Neuhauser ---- - drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- - 1 file changed, 389 insertions(+), 166 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -30,6 +30,7 @@ - #include - #include - #include -+#include - - #include - -@@ -560,7 +561,8 @@ static int - ltq_etop_mdio_init(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int err; -+ struct device_node *mdio_np = NULL; -+ int err, ret; - - priv->mii_bus = mdiobus_alloc(); - if (!priv->mii_bus) { -@@ -580,7 +582,15 @@ ltq_etop_mdio_init(struct net_device *de - priv->mii_bus->name = "ltq_mii"; - snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", - priv->pdev->name, priv->pdev->id); -- if (mdiobus_register(priv->mii_bus)) { -+ -+ mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus"); -+ -+ if (mdio_np) -+ ret = of_mdiobus_register(priv->mii_bus, mdio_np); -+ else -+ ret = mdiobus_register(priv->mii_bus); -+ -+ if (ret) { - err = -ENXIO; - goto err_out_free_mdiobus; - } diff --git a/target/linux/lantiq/xrx200/config-6.12 b/target/linux/lantiq/xrx200/config-6.12 deleted file mode 100644 index ad8a4544cec..00000000000 --- a/target/linux/lantiq/xrx200/config-6.12 +++ /dev/null @@ -1,93 +0,0 @@ -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GRO_CELLS=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_ICPLUS_PHY=y -CONFIG_IFX_VPE_EXT=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INTEL_XWAY_PHY=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_XRX200=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MIPS_MT=y -# CONFIG_MIPS_MT_FPAFF is not set -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_NR_CPU_NR_MAP=2 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MIPS_VPE_APSP_API=y -CONFIG_MIPS_VPE_APSP_API_MT=y -CONFIG_MIPS_VPE_LOADER=y -CONFIG_MIPS_VPE_LOADER_MT=y -CONFIG_MIPS_VPE_LOADER_TOM=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_MTD_NAND_XWAY=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_NVMEM=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NEED_SRCU_NMI_SAFE=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NR_CPUS=2 -CONFIG_PADATA=y -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_LANTIQ=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_PHYLINK=y -CONFIG_PHY_LANTIQ_VRX200_PCIE=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_QCOM_NET_PHYLIB=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_SENSORS_LTQ_CPUTEMP=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SYNC_R4K=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/lantiq/xrx200_legacy/config-6.12 b/target/linux/lantiq/xrx200_legacy/config-6.12 deleted file mode 100644 index ee883b6aa9b..00000000000 --- a/target/linux/lantiq/xrx200_legacy/config-6.12 +++ /dev/null @@ -1,77 +0,0 @@ -CONFIG_BLK_MQ_PCI=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GRO_CELLS=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_IFX_VPE_EXT=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INTEL_XWAY_PHY=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_XRX200=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MIPS_MT=y -# CONFIG_MIPS_MT_FPAFF is not set -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_NR_CPU_NR_MAP=2 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MIPS_VPE_APSP_API=y -CONFIG_MIPS_VPE_APSP_API_MT=y -CONFIG_MIPS_VPE_LOADER=y -CONFIG_MIPS_VPE_LOADER_MT=y -CONFIG_MIPS_VPE_LOADER_TOM=y -CONFIG_NEED_SRCU_NMI_SAFE=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NR_CPUS=2 -CONFIG_PADATA=y -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_LANTIQ=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_PHYLINK=y -CONFIG_PHY_LANTIQ_VRX200_PCIE=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_SENSORS_LTQ_CPUTEMP=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SYNC_R4K=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/lantiq/xway/config-6.12 b/target/linux/lantiq/xway/config-6.12 deleted file mode 100644 index 955abbe5392..00000000000 --- a/target/linux/lantiq/xway/config-6.12 +++ /dev/null @@ -1,83 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_AR8216_PHY=y -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_HW_RANDOM=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_ETOP=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MIPS_MT=y -CONFIG_MIPS_MT_FPAFF=y -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_NR_CPU_NR_MAP=2 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_XWAY=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NEED_SRCU_NMI_SAFE=y -CONFIG_NET_FLOW_LIMIT=y -# CONFIG_NET_SWITCHDEV is not set -CONFIG_NLS=y -CONFIG_NR_CPUS=2 -CONFIG_PADATA=y -CONFIG_PCI=y -# CONFIG_PCIE_LANTIQ is not set -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_PSB6970_PHY=y -CONFIG_QCOM_NET_PHYLIB=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTL8306_PHY=y -CONFIG_RTL8366RB_PHY=y -CONFIG_RTL8366_SMI=y -# CONFIG_SCHED_CORE is not set -CONFIG_SCHED_SMT=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SWCONFIG=y -CONFIG_SYNC_R4K=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/lantiq/xway_legacy/config-6.12 b/target/linux/lantiq/xway_legacy/config-6.12 deleted file mode 100644 index ffa5948c8e0..00000000000 --- a/target/linux/lantiq/xway_legacy/config-6.12 +++ /dev/null @@ -1,31 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_GENERIC_ALLOCATOR=y -# CONFIG_GPIO_CDEV is not set -# CONFIG_GPIO_SYSFS is not set -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_ETOP=y -# CONFIG_LEDS_TRIGGER_TIMER is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_NET_SWITCHDEV is not set -CONFIG_NLS=y -CONFIG_PCI=y -# CONFIG_PCIE_LANTIQ is not set -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RTL8306_PHY=y -CONFIG_SGL_ALLOC=y -CONFIG_SWCONFIG=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y