From 426b1a97ac62794d1288d98b852ad4a478f248e6 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Tue, 28 Apr 2026 20:53:52 +0000 Subject: [PATCH] realtek: make Zyxel XMG1915-10E generic for whole family The XMG1915 is a switch family with multiple variants sharing nearly all hardware (same SoC, PHYs, SFP cages, LEDs) and mainly differing in PoE and minor details. In preparation for adding further variants, move the bulk of the device tree into a shared rtl9302_zyxel_xmg1915.dtsi and reduce the per-device dts to the device identity (compatible, model) plus any variant-specific nodes. For images, factor a Device/zyxel_xmg1915 template holding the shared build settings so per-device definitions only need DEVICE_MODEL. No functional change for XMG1915-10E. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/23218 Signed-off-by: Robert Marko --- .../realtek/dts/rtl9302_zyxel_xmg1915-10e.dts | 269 +---------------- .../realtek/dts/rtl9302_zyxel_xmg1915.dtsi | 276 ++++++++++++++++++ target/linux/realtek/image/rtl930x.mk | 8 +- 3 files changed, 283 insertions(+), 270 deletions(-) create mode 100644 target/linux/realtek/dts/rtl9302_zyxel_xmg1915.dtsi diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xmg1915-10e.dts b/target/linux/realtek/dts/rtl9302_zyxel_xmg1915-10e.dts index 9d646ea1a61..fd9d51a3935 100644 --- a/target/linux/realtek/dts/rtl9302_zyxel_xmg1915-10e.dts +++ b/target/linux/realtek/dts/rtl9302_zyxel_xmg1915-10e.dts @@ -1,8 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include "macros.dtsi" -#include "rtl930x.dtsi" +#include "rtl9302_zyxel_xmg1915.dtsi" #include #include @@ -11,270 +10,4 @@ / { compatible = "zyxel,xmg1915-10e", "realtek,rtl9302c-soc"; model = "Zyxel XMG1915-10E Switch"; - - aliases { - label-mac-device = ðernet0; - led-boot = &led_pwr_sys_green; - led-failsafe = &led_pwr_sys_red; - led-running = &led_pwr_sys_green; - led-upgrade = &led_pwr_sys_green; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - - led_pwr_sys_green: led-0 { - color = ; - function = LED_FUNCTION_POWER; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - led_pwr_sys_red: led-1 { - color = ; - function = LED_FUNCTION_POWER; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - led_set: led_set { - compatible = "realtek,rtl9300-leds"; - active-low; - - /* Copper */ - led_set0 = <(RTL93XX_LED_SET_100M | RTL93XX_LED_SET_LINK | - RTL93XX_LED_SET_ACT) - (RTL93XX_LED_SET_100M |RTL93XX_LED_SET_1G | - RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | - RTL93XX_LED_SET_ACT) - (RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | - RTL93XX_LED_SET_ACT)>; - /* SFP+ */ - led_set1 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_2P5G | - RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT) - (RTL93XX_LED_SET_10G | RTL93XX_LED_SET_2P5G | - RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>; - - /* PoE and Cloud are 4 leds in total but software managed. - Assign them to led_set 1 to avoid shifting the others - incorrectly. */ - realtek,led-set1-force-port-mask = <0x01800000>; - }; - - keys { - compatible = "gpio-keys"; - - mode { - label = "restore"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - sfp0: sfp-p9 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>; - }; - - sfp1: sfp-p10 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c_mst1 { - status = "okay"; - - /* i2c of the left SFP+ cage seen from the front; port 9 */ - i2c0: i2c@0 { - reg = <0>; - }; - - /* i2c of the right SFP+ cage seen from the front; port 10 */ - i2c1: i2c@1 { - reg = <1>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootbase"; - reg = <0x0 0x80000>; - read-only; - - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x7e000>; - }; - - partition@7e000 { - label = "u-boot-env2"; - reg = <0x7e000 0x1000>; - }; - - partition@7f000 { - label = "mrd"; - reg = <0x7f000 0x1000>; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - /* 12 addresses are available */ - macaddr_factory: macaddr@ff8 { - compatible = "mac-base"; - reg = <0xff8 0x6>; - #nvmem-cell-cells = <1>; - }; - }; - }; - }; - - partition@80000 { - label = "reserved"; - reg = <0x80000 0x1e0000>; - read-only; - }; - - partition@260000 { - label = "factory"; - reg = <0x260000 0x1da0000>; - - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "loader"; - reg = <0x0 0x10000>; - }; - partition@10000 { - label = "firmware"; - reg = <0x10000 0x1d90000>; - compatible = "openwrt,uimage", "denx,uimage"; - }; - }; - }; - }; -}; - -&mdio_bus0 { - /* External RTL8224 PHY */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <0>; - enet-phy-pair-polarity = <0>; - }; - phy1: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <0>; - enet-phy-pair-polarity = <0>; - }; - phy2: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <1>; - enet-phy-pair-polarity = <0>; - }; - phy3: ethernet-phy@3 { - reg = <3>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <1>; - enet-phy-pair-polarity = <0>; - }; -}; - -&mdio_bus1 { - /* External RTL8224 PHY */ - phy8: ethernet-phy@4 { - reg = <4>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <0>; - enet-phy-pair-polarity = <0>; - }; - phy9: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <0>; - enet-phy-pair-polarity = <0>; - }; - phy10: ethernet-phy@6 { - reg = <6>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <1>; - enet-phy-pair-polarity = <0>; - }; - phy11: ethernet-phy@7 { - reg = <7>; - compatible = "ethernet-phy-ieee802.3-c45"; - enet-phy-pair-order = <1>; - enet-phy-pair-polarity = <0>; - }; -}; - -ðernet0 { - nvmem-cells = <&macaddr_factory 0>; - nvmem-cell-names = "mac-address"; -}; - -&switch0 { - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* Copper ports */ - SWITCH_PORT_LED(0, 1, 2, 0, 10g-qxgmii) - SWITCH_PORT_LED(1, 2, 2, 0, 10g-qxgmii) - SWITCH_PORT_LED(2, 3, 2, 0, 10g-qxgmii) - SWITCH_PORT_LED(3, 4, 2, 0, 10g-qxgmii) - SWITCH_PORT_LED(8, 5, 3, 0, 10g-qxgmii) - SWITCH_PORT_LED(9, 6, 3, 0, 10g-qxgmii) - SWITCH_PORT_LED(10, 7, 3, 0, 10g-qxgmii) - SWITCH_PORT_LED(11, 8, 3, 0, 10g-qxgmii) - - /* SFP cages */ - SWITCH_PORT_SFP(25, 9, 7, 1, 0) - SWITCH_PORT_SFP(27, 10, 9, 1, 1) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; }; diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xmg1915.dtsi b/target/linux/realtek/dts/rtl9302_zyxel_xmg1915.dtsi new file mode 100644 index 00000000000..ac25269f796 --- /dev/null +++ b/target/linux/realtek/dts/rtl9302_zyxel_xmg1915.dtsi @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/dts-v1/; + +#include "rtl930x.dtsi" + +#include +#include +#include + +/ { + aliases { + label-mac-device = ðernet0; + led-boot = &led_pwr_sys_green; + led-failsafe = &led_pwr_sys_red; + led-running = &led_pwr_sys_green; + led-upgrade = &led_pwr_sys_green; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_disable_sys_led>; + + led_pwr_sys_green: led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_pwr_sys_red: led-1 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + led_set: led_set { + compatible = "realtek,rtl9300-leds"; + active-low; + + /* Copper */ + led_set0 = <(RTL93XX_LED_SET_100M | RTL93XX_LED_SET_LINK | + RTL93XX_LED_SET_ACT) + (RTL93XX_LED_SET_100M |RTL93XX_LED_SET_1G | + RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | + RTL93XX_LED_SET_ACT) + (RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | + RTL93XX_LED_SET_ACT)>; + /* SFP+ */ + led_set1 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_2P5G | + RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT) + (RTL93XX_LED_SET_10G | RTL93XX_LED_SET_2P5G | + RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>; + + /* PoE and Cloud are 4 leds in total but software managed. + Assign them to led_set 1 to avoid shifting the others + incorrectly. */ + realtek,led-set1-force-port-mask = <0x01800000>; + }; + + keys { + compatible = "gpio-keys"; + + mode { + label = "restore"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sfp0: sfp-p9 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>; + los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + tx-disable-gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp-p10 { + compatible = "sff,sfp"; + i2c-bus = <&i2c1>; + mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>; + los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; + tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c_mst1 { + status = "okay"; + + /* i2c of the left SFP+ cage seen from the front; port 9 */ + i2c0: i2c@0 { + reg = <0>; + }; + + /* i2c of the right SFP+ cage seen from the front; port 10 */ + i2c1: i2c@1 { + reg = <1>; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootbase"; + reg = <0x0 0x80000>; + read-only; + + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x7e000>; + }; + + partition@7e000 { + label = "u-boot-env2"; + reg = <0x7e000 0x1000>; + }; + + partition@7f000 { + label = "mrd"; + reg = <0x7f000 0x1000>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + /* 12 addresses are available */ + macaddr_factory: macaddr@ff8 { + compatible = "mac-base"; + reg = <0xff8 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + }; + + partition@80000 { + label = "reserved"; + reg = <0x80000 0x1e0000>; + read-only; + }; + + partition@260000 { + label = "factory"; + reg = <0x260000 0x1da0000>; + + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "firmware"; + reg = <0x10000 0x1d90000>; + compatible = "openwrt,uimage", "denx,uimage"; + }; + }; + }; + }; +}; + +&mdio_bus0 { + /* External RTL8224 PHY */ + phy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <0>; + enet-phy-pair-polarity = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <0>; + enet-phy-pair-polarity = <0>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <1>; + enet-phy-pair-polarity = <0>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <1>; + enet-phy-pair-polarity = <0>; + }; +}; + +&mdio_bus1 { + /* External RTL8224 PHY */ + phy8: ethernet-phy@4 { + reg = <4>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <0>; + enet-phy-pair-polarity = <0>; + }; + phy9: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <0>; + enet-phy-pair-polarity = <0>; + }; + phy10: ethernet-phy@6 { + reg = <6>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <1>; + enet-phy-pair-polarity = <0>; + }; + phy11: ethernet-phy@7 { + reg = <7>; + compatible = "ethernet-phy-ieee802.3-c45"; + enet-phy-pair-order = <1>; + enet-phy-pair-polarity = <0>; + }; +}; + +ðernet0 { + nvmem-cells = <&macaddr_factory 0>; + nvmem-cell-names = "mac-address"; +}; + +&switch0 { + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* Copper ports */ + SWITCH_PORT_LED(0, 1, 2, 0, 10g-qxgmii) + SWITCH_PORT_LED(1, 2, 2, 0, 10g-qxgmii) + SWITCH_PORT_LED(2, 3, 2, 0, 10g-qxgmii) + SWITCH_PORT_LED(3, 4, 2, 0, 10g-qxgmii) + SWITCH_PORT_LED(8, 5, 3, 0, 10g-qxgmii) + SWITCH_PORT_LED(9, 6, 3, 0, 10g-qxgmii) + SWITCH_PORT_LED(10, 7, 3, 0, 10g-qxgmii) + SWITCH_PORT_LED(11, 8, 3, 0, 10g-qxgmii) + + /* SFP cages */ + SWITCH_PORT_SFP(25, 9, 7, 1, 0) + SWITCH_PORT_SFP(27, 10, 9, 1, 1) + + port@28 { + ethernet = <ðernet0>; + reg = <28>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/realtek/image/rtl930x.mk b/target/linux/realtek/image/rtl930x.mk index 9fb843f3bd6..388c698cd10 100644 --- a/target/linux/realtek/image/rtl930x.mk +++ b/target/linux/realtek/image/rtl930x.mk @@ -226,12 +226,16 @@ define Device/zyxel_xgs1250-12-b1 endef TARGET_DEVICES += zyxel_xgs1250-12-b1 -define Device/zyxel_xmg1915-10e +define Device/zyxel_xmg1915 SOC := rtl9302 - DEVICE_MODEL := XMG1915-10E FLASH_ADDR := 0xb4270000 IMAGE_SIZE := 30336k ZYNFW_ALIGN := 0x10000 $(Device/zyxel_zynos) endef + +define Device/zyxel_xmg1915-10e + DEVICE_MODEL := XMG1915-10E + $(Device/zyxel_xmg1915) +endef TARGET_DEVICES += zyxel_xmg1915-10e