diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c index 81dfa43d750..8dc8bd05c29 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c @@ -17,6 +17,7 @@ #include "l2.h" #include "l3.h" +#include "pie.h" #include "rtl-otto.h" #include "tc.h" #include "stp.h" diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/debugfs.c index 18da62a40d9..8c8c1ad351e 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/debugfs.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/debugfs.c @@ -4,10 +4,34 @@ #include #include +#include "mac.h" +#include "l2.h" #include "rtl-otto.h" #include "vlan.h" #include "stp.h" +#define RTL838X_STORM_CTRL_PORT_UC(p) (0x4718 + (((p) << 2))) +#define RTL838X_STORM_CTRL_PORT_MC(p) (0x478c + (((p) << 2))) +#define RTL838X_STORM_CTRL_PORT_BC(p) (0x4800 + (((p) << 2))) +#define RTL839X_STORM_CTRL_PORT_UC_0(p) (0x185C + (((p) << 3))) +#define RTL839X_STORM_CTRL_PORT_MC_0(p) (0x19FC + (((p) << 3))) +#define RTL839X_STORM_CTRL_PORT_BC_0(p) (0x1B9C + (((p) << 3))) + +#define RTL838X_LED_GLB_CTRL (0xA000) + +/* LED control by switch */ +#define RTL838X_LED_MODE_SEL (0x1004) +#define RTL838X_LED_MODE_CTRL (0xA004) +#define RTL838X_LED_P_EN_CTRL (0xA008) + +/* LED control by software */ +#define RTL838X_LED_SW_CTRL (0xA00C) +#define RTL838X_LED0_SW_P_EN_CTRL (0xA010) +#define RTL838X_LED1_SW_P_EN_CTRL (0xA014) +#define RTL838X_LED2_SW_P_EN_CTRL (0xA018) +#define RTL838X_LED_SW_P_CTRL (0xA01C) +#define RTL838X_LED_SW_P_CTRL_PORT(p) (RTL838X_LED_SW_P_CTRL + (((p) << 2))) + #define RTL838X_DRIVER_NAME "rtl838x" #define RTL8390_LED_GLB_CTRL (0x00E4) @@ -437,7 +461,6 @@ static const struct file_operations rtldsa_vlan_table_raw_fops = { .release = single_release, }; - static int rtldsa_vlan_table_show(struct seq_file *m, void *v) { struct rtl838x_switch_priv *priv = m->private; diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c index 9bdbc1f7fc9..c3c96fd255d 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c @@ -9,12 +9,52 @@ #include "lag.h" #include "mirror.h" +#include "mac.h" +#include "l2.h" #include "rtl-otto.h" #include "stats.h" #include "tc.h" #include "vlan.h" #include "stp.h" +/* Both length fields are 14 bits wide (hardware maximum 16383 bytes). */ +#define RTLDSA_MAC_MAX_LEN_FIELD GENMASK(13, 0) +/* Mask of both length fields, leaving the tag-inclusion bit (28) untouched. */ +#define RTLDSA_MAC_MAX_LEN_MASK \ + (RTLDSA_MAC_MAX_LEN_FIELD | (RTLDSA_MAC_MAX_LEN_FIELD << 14)) +/* Encode @len into both the high-speed and the 10/100M length field. */ +#define RTLDSA_MAC_MAX_LEN_VAL(len) \ + (((len) & RTLDSA_MAC_MAX_LEN_FIELD) | (((len) & RTLDSA_MAC_MAX_LEN_FIELD) << 14)) + +/* MAC link state bits */ +#define RTL_SPEED_10 0 +#define RTL_SPEED_100 1 +#define RTL_SPEED_1000 2 +#define RTL_SPEED_2500 5 +#define RTL_SPEED_5000 6 +#define RTL_SPEED_10000 4 + +#define RTL838X_NWAY_EN BIT(2) +#define RTL838X_DUPLEX_MODE BIT(3) +#define RTL838X_SPEED_SHIFT (4) +#define RTL838X_SPEED_MASK (3 << RTL838X_SPEED_SHIFT) +#define RTL838X_TX_PAUSE_EN BIT(6) +#define RTL838X_RX_PAUSE_EN BIT(7) + +#define RTL839X_DUPLEX_MODE BIT(2) +#define RTL839X_SPEED_SHIFT (3) +#define RTL839X_SPEED_MASK (3 << RTL839X_SPEED_SHIFT) +#define RTL839X_TX_PAUSE_EN BIT(5) +#define RTL839X_RX_PAUSE_EN BIT(6) + +#define RTL930X_DUPLEX_MODE BIT(2) +#define RTL930X_SPEED_SHIFT (3) +#define RTL930X_SPEED_MASK (15 << RTL930X_SPEED_SHIFT) +#define RTL930X_TX_PAUSE_EN BIT(7) +#define RTL930X_RX_PAUSE_EN BIT(8) + +#define RTL930X_PORT_IGNORE 0x3f + /* Ethernet header, two stacked VLAN tags (802.1ad QinQ) and FCS */ #define RTLDSA_FRAME_OVERHEAD (ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN) /* Tail tag the DSA core adds to a frame on its way to the conduit */ diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l2.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l2.c index 5bb4b851aa1..d6df4e9f3ee 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l2.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l2.c @@ -9,6 +9,52 @@ #include "l2.h" #include "rtl-otto.h" +#define RTL838X_L2_LRN_CONSTRT (0x329C) +#define RTL839X_L2_LRN_CONSTRT (0x3910) +#define RTL930X_L2_LRN_CONSTRT_CTRL (0x909c) +#define RTL931X_L2_LRN_CONSTRT_CTRL (0xC964) + +#define RTL838X_L2_FLD_PMSK (0x3288) +#define RTL839X_L2_FLD_PMSK (0x38EC) +#define RTL930X_L2_BC_FLD_PMSK (0x9068) +#define RTL931X_L2_BC_FLD_PMSK (0xC8FC) + +#define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064) +#define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4) + +#define RTL838X_L2_BC_FLD(pmsk) (pmsk << 9) +#define RTL838X_L2_UNKN_UC_FLD(pmsk) (pmsk) +#define RTL839X_L2_BC_FLD(pmsk) (pmsk << 12) +#define RTL839X_L2_UNKN_UC_FLD(pmsk) (pmsk) + +#define RTL838X_L2_LRN_CONSTRT_EN (0x3368) +#define RTL838X_L2_PORT_LRN_CONSTRT (0x32A0) +#define RTL839X_L2_PORT_LRN_CONSTRT (0x3914) +#define RTL930X_L2_LRN_PORT_CONSTRT_CTRL (0x90A4) +#define RTL931X_L2_LRN_PORT_CONSTRT_CTRL (0xC96C) + +#define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2))) +#define RTL930X_L2_PORT_SALRN(p) (0x8FEC + (((p >> 4) << 2))) +#define RTL931X_L2_PORT_NEW_SALRN(p) (0xC820 + (((p >> 4) << 2))) + +#define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2))) +#define RTL930X_L2_PORT_NEW_SA_FWD(p) (0x8FF4 + (((p / 10) << 2))) +#define RTL931X_L2_PORT_NEW_SA_FWD(p) (0xC830 + (((p / 10) << 2))) + +#define RTL838X_L2_PORT_STATIC_MV_ACT(p) (0x327c + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_STATIC_MV_ACT(p) (0x38dc + (((p >> 4) << 2))) + +#define MV_ACT_PORT_SHIFT(p) ((p % 16) * 2) +#define MV_ACT_MASK 0x3 +#define MV_ACT_FORWARD 0 +#define MV_ACT_DROP 1 + +#define RTL838X_SPCL_TRAP_ARP_CTRL (0x698C) + +#define RTL839X_SPCL_TRAP_ARP_CTRL (0x1060) + u64 rtl838x_l2_hash_seed(u64 mac, u32 vid) { return mac << 12 | vid; diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l2.h b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l2.h index a5d05e042cd..49d78cf3a13 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l2.h +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l2.h @@ -2,7 +2,60 @@ #ifndef _OTTO_L2_H #define _OTTO_L2_H -#include "rtl-otto.h" +#include +#include + +struct rtl838x_switch_priv; +struct rtl838x_l2_entry; + +enum rtldsa_flood_type { + RTLDSA_FLOOD_TYPE_FORWARD = 0, + RTLDSA_FLOOD_TYPE_DROP, + RTLDSA_FLOOD_TYPE_TRAP2CPU, + RTLDSA_FLOOD_TYPE_COPY2CPU, + RTLDSA_FLOOD_TYPE_TRAP2MASTER, + RTLDSA_FLOOD_TYPE_COPY2MASTER, +}; + +#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2)) + +#define RTL930X_L2_CTRL (0x8FD8) +#define RTL931X_L2_CTRL (0xC800) +#define RTL838X_L2_CTRL_1 (0x3204) +#define RTL839X_L2_CTRL_1 (0x3804) +#define RTL930X_L2_AGE_CTRL (0x8FDC) +#define RTL931X_L2_AGE_CTRL (0xC804) +#define RTL838X_L2_PORT_AGING_OUT (0x3358) +#define RTL839X_L2_PORT_AGING_OUT (0x3b74) +#define RTL930X_L2_PORT_AGE_CTRL (0x8FE0) +#define RTL931X_L2_PORT_AGE_CTRL (0xc808) + +#define RTL930X_L2_TBL_FLUSH_CTRL (0x9404) +#define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C) + +#define SALRN_PORT_SHIFT(p) ((p % 16) * 2) +#define SALRN_MODE_MASK 0x3 +#define SALRN_MODE_HARDWARE 0 +#define SALRN_MODE_DISABLED 2 + +#define RTL930X_L2_PORT_SABLK_CTRL (0x905c) +#define RTL930X_L2_PORT_DABLK_CTRL (0x9060) + +/* ToDo: MAX_MC_GROUPS could be increased + * 838x/839x/930x/931x -> 8192/16384/16384/32768 entries (priv->fib_entries) + * They are shared with unicast entries + */ +#define MAX_MC_GROUPS 512 +/* ToDo: MAX_MC_PMASKS could be increased + * 838x/839x/930x/931x -> 512/4096/1024/4096 entries + */ +#define MAX_MC_PMASKS 512 +#define RTL838X_MC_PMASK_ALL_PORTS (GENMASK(RTL838X_CPU_PORT, 0)) +#define RTL930X_MC_PMASK_ALL_PORTS (GENMASK(RTL930X_CPU_PORT, 0)) +#define RTL931X_MC_PMASK_ALL_PORTS (GENMASK_ULL(RTL931X_CPU_PORT, 0)) +#define MC_PMASK_ALL_PORTS_IDX ((MAX_MC_PMASKS - 1)) + +#define RTLDSA_L2_L3_REFCOUNT_MAX 0x7f u64 rtl838x_l2_hash_seed(u64 mac, u32 vid); u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed); diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.c index 86c88410607..8b4bd3c8a63 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.c @@ -17,8 +17,42 @@ #include #include "l3.h" +#include "pie.h" #include "rtl-otto.h" +/* L3 actions */ +#define L3_FORWARD 0 + +/* Route entry types */ +#define ROUTE_TYPE_IP4UC 0 +#define ROUTE_TYPE_IP4MC 1 +#define ROUTE_TYPE_IP6UC 2 +#define ROUTE_TYPE_IP6MC 3 + +/* Route actions */ +#define ROUTE_ACT_FORWARD 0 +#define ROUTE_ACT_TRAP2CPU 1 +#define ROUTE_ACT_COPY2CPU 2 +#define ROUTE_ACT_DROP 3 + +/* L3 Routing */ +#define RTL839X_ROUTING_SA_CTRL 0x6afc +#define RTL930X_L3_HOST_TBL_CTRL (0xAB48) +#define RTL930X_L3_IPUC_ROUTE_CTRL (0xAB4C) +#define RTL930X_L3_IP6UC_ROUTE_CTRL (0xAB50) +#define RTL930X_L3_IPMC_ROUTE_CTRL (0xAB54) +#define RTL930X_L3_IP6MC_ROUTE_CTRL (0xAB58) +#define RTL930X_L3_IP_MTU_CTRL(i) (0xAB5C + ((i >> 1) << 2)) +#define RTL930X_L3_IP6_MTU_CTRL(i) (0xAB6C + ((i >> 1) << 2)) +#define RTL930X_L3_HW_LU_KEY_CTRL (0xAC9C) +#define RTL930X_L3_HW_LU_KEY_IP_CTRL (0xACA0) +#define RTL930X_L3_HW_LU_CTRL (0xACC0) +#define RTL930X_L3_IP_ROUTE_CTRL 0xab44 + +#define DEFAULT_MTU 1536 +#define MAX_ROUTER_MACS 64 +#define L3_EGRESS_DMACS 2048 + static const struct rhashtable_params otto_l3_route_ht_params = { .key_len = sizeof(struct in6_addr), .key_offset = offsetof(struct otto_l3_route, gw_ip), @@ -422,7 +456,6 @@ static void otto_l3_930x_set_nexthop(struct otto_l3_ctrl *ctrl, otto_table_write(RTL9300_TBL_L3_NEXTHOP, idx, &v); } - /* Prefix length of an IPv6 mask, i.e. how many leading bits are set */ __maybe_unused static int otto_l3_930x_mask6_len(const struct in6_addr *mask) diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.h b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.h index 3cca9b001d3..60a181b5d3f 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.h +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.h @@ -3,10 +3,12 @@ #ifndef _OTTO_L3_H #define _OTTO_L3_H +#include "l3_limits.h" #include "rtl-otto.h" struct fib6_info; +#define MAX_SMACS 64 #define MAX_HOST_ROUTES 1536 #define MAX_ROUTES 512 diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3_limits.h b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3_limits.h new file mode 100644 index 00000000000..7bcf8e58d97 --- /dev/null +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3_limits.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _OTTO_L3_LIMITS_H +#define _OTTO_L3_LIMITS_H + +/* L3 MTU table size shared with the switch state. */ +#define MAX_INTF_MTUS 8 + +#endif /* _OTTO_L3_LIMITS_H */ diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/lag.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/lag.c index b83e3ae4df2..813e2cd19f8 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/lag.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/lag.c @@ -6,6 +6,131 @@ #include #include "lag.h" +#include "rtl-otto.h" + +/* Link aggregation (Trunking) */ +#define TRUNK_DISTRIBUTION_ALGO_SPA_BIT BIT(0) +#define TRUNK_DISTRIBUTION_ALGO_SMAC_BIT BIT(1) +#define TRUNK_DISTRIBUTION_ALGO_DMAC_BIT BIT(2) + +#define TRUNK_DISTRIBUTION_ALGO_SIP_BIT BIT(3) +#define TRUNK_DISTRIBUTION_ALGO_DIP_BIT BIT(4) +#define TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT BIT(5) +#define TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT BIT(6) +#define TRUNK_DISTRIBUTION_ALGO_VLAN_BIT BIT(7) +#define TRUNK_DISTRIBUTION_ALGO_MASKALL GENMASK(6, 0) + +#define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT BIT(0) +#define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT BIT(1) +#define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT BIT(2) +#define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT BIT(3) + +#define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT BIT(4 + 0) +#define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT BIT(4 + 1) +#define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT BIT(4 + 2) +#define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT BIT(4 + 3) +#define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT BIT(4 + 4) +#define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT BIT(4 + 5) +#define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT BIT(4 + 6) +#define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT BIT(4 + 7) + +#define RTL838X_TRK_MBR_CTR (0x3E00) +#define RTL838X_TRK_HASH_IDX_CTRL (0x3E20) +#define RTL838X_TRK_HASH_CTRL (0x3E24) + +#define RTL839X_TRK_MBR_CTR (0x2200) +#define RTL839X_TRK_HASH_IDX_CTRL (0x2280) +#define RTL839X_TRK_HASH_CTRL (0x2284) + +#define RTL930X_LOCAL_PORT_TRK_MAP (0xD0C8) +#define RTL930X_TRK_ID_CTRL (0xA3A8) +#define RTL930X_TRK_MBR_CTRL (0xA41C) +#define RTL930X_TRK_LOCAL_TBL_REFRESH (0x9F90) + +#define RTL930X_TRK_ID_CTRL_TRK_VALID BIT(6) +#define RTL930X_TRK_ID_CTRL_TRK_ID GENMASK(5, 0) + +#define RTL930X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR BIT(6) +#define RTL930X_LOCAL_PORT_TRK_MAP_TRK_ID GENMASK(5, 0) + +#define RTL930X_SRC_TRK_MAP_TRK_VALID BIT(31) +#define RTL930X_SRC_TRK_MAP_TRK_ID GENMASK(30, 25) + +#define RTL931X_LOCAL_PORT_TRK_MAP (0x4CAC) +#define RTL931X_TRK_ID_CTRL (0xB800) +#define RTL931X_TRK_MBR_CTRL (0xB8D0) +#define RTL931X_TRK_LOCAL_TBL_REFRESH (0xBA80) + +#define RLT931X_TRK_ID_CTRL_TRK_ID GENMASK(6, 0) +#define RTL931X_TRK_ID_CTRL_TRK_VALID BIT(7) + +#define RTL931X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR BIT(7) +#define RTL931X_LOCAL_PORT_TRK_MAP_TRK_ID GENMASK(6, 0) + +#define RTL931X_SRC_TRK_MAP_TRK_ID GENMASK(30, 24) +#define RTL931X_SRC_TRK_MAP_TRK_ID_VALID BIT(31) + +#define GENMASK_MOD(high, low) GENMASK((high) % 32, (low) % 32) +#define BIT_MOD(bit) BIT((bit) % 32) + +/* RTL930X LAG Table offsets */ +#define RTL930X_LAG_NUM_TX_CANDI GENMASK_MOD(92, 89) +#define RTL930X_LAG_L2_HASH_MSK_IDX BIT_MOD(88) +#define RTL930X_LAG_IP4_HASH_MSK_IDX BIT_MOD(87) +#define RTL930X_LAG_IP6_HASH_MSK_IDX BIT_MOD(86) +#define RTL930X_LAG_SEP_DLF_BCAST_EN BIT_MOD(85) +#define RTL930X_LAG_SEP_KWN_MC_EN BIT_MOD(84) +#define RTL930X_LAG_TRK_DEV7 GENMASK_MOD(83, 80) +#define RTL930X_LAG_TRK_PORT7 GENMASK_MOD(79, 74) +#define RTL930X_LAG_TRK_DEV6 GENMASK_MOD(73, 70) +#define RTL930X_LAG_TRK_PORT6 GENMASK_MOD(69, 64) + +#define RTL930X_LAG_TRK_DEV5 GENMASK_MOD(61, 58) +#define RTL930X_LAG_TRK_PORT5 GENMASK_MOD(57, 52) +#define RTL930X_LAG_TRK_DEV4 GENMASK_MOD(51, 48) +#define RTL930X_LAG_TRK_PORT4 GENMASK_MOD(47, 42) +#define RTL930X_LAG_TRK_DEV3 GENMASK_MOD(41, 38) +#define RTL930X_LAG_TRK_PORT3 GENMASK_MOD(37, 32) + +#define RTL930X_LAG_TRK_DEV2 GENMASK_MOD(29, 26) +#define RTL930X_LAG_TRK_PORT2 GENMASK_MOD(25, 20) +#define RTL930X_LAG_TRK_DEV1 GENMASK_MOD(19, 16) +#define RTL930X_LAG_TRK_PORT1 GENMASK_MOD(15, 10) +#define RTL930X_LAG_TRK_DEV0 GENMASK_MOD(9, 6) +#define RTL930X_LAG_TRK_PORT0 GENMASK_MOD(5, 0) + +/* RTL931X LAG Table offsets */ +#define RTL931X_LAG_NUM_TX_CANDI GENMASK_MOD(92, 89) +#define RTL931X_LAG_L2_HASH_MSK_IDX BIT_MOD(88) +#define RTL931X_LAG_IP4_HASH_MSK_IDX BIT_MOD(87) +#define RTL931X_LAG_IP6_HASH_MSK_IDX BIT_MOD(86) +#define RTL931X_LAG_SEP_FLOOD_EN BIT_MOD(85) +#define RTL931X_LAG_SEP_KWN_MC_EN BIT_MOD(84) +#define RTL931X_LAG_TRK_DEV7 GENMASK_MOD(83, 80) +#define RTL931X_LAG_TRK_PORT7 GENMASK_MOD(79, 74) +#define RTL931X_LAG_TRK_DEV6 GENMASK_MOD(73, 70) +#define RTL931X_LAG_TRK_PORT6 GENMASK_MOD(69, 64) + +#define RTL931X_LAG_TRK_DEV5 GENMASK_MOD(61, 58) +#define RTL931X_LAG_TRK_PORT5 GENMASK_MOD(57, 52) +#define RTL931X_LAG_TRK_DEV4 GENMASK_MOD(51, 48) +#define RTL931X_LAG_TRK_PORT4 GENMASK_MOD(47, 42) +#define RTL931X_LAG_TRK_DEV3 GENMASK_MOD(41, 38) +#define RTL931X_LAG_TRK_PORT3 GENMASK_MOD(37, 32) + +#define RTL931X_LAG_TRK_DEV2 GENMASK_MOD(29, 26) +#define RTL931X_LAG_TRK_PORT2 GENMASK_MOD(25, 20) +#define RTL931X_LAG_TRK_DEV1 GENMASK_MOD(19, 16) +#define RTL931X_LAG_TRK_PORT1 GENMASK_MOD(15, 10) +#define RTL931X_LAG_TRK_DEV0 GENMASK_MOD(9, 6) +#define RTL931X_LAG_TRK_PORT0 GENMASK_MOD(5, 0) + +#define RTL93XX_HASH_MASK_INDEX_L2 (0) +#define RTL93XX_HASH_MASK_INDEX_L23 (1) + +#define RTL93XX_TRK_CTRL_NON_TMN_TUNNEL_HASH_SEL BIT(0) +#define RTL93XX_TRK_CTRL_TRK_STAND_ALONE_MODE BIT(2) +#define RTL93XX_TRK_CTRL_LOCAL_FIRST BIT(4) /* Caller must hold priv->reg_mutex */ int rtldsa_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info) diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/lag.h b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/lag.h index 3a64acdaa03..a6afc7e121d 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/lag.h +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/lag.h @@ -2,7 +2,14 @@ #ifndef _OTTO_LAG_H #define _OTTO_LAG_H -#include "rtl-otto.h" +#include + +struct dsa_switch; +struct netdev_lag_upper_info; +struct rtl838x_switch_priv; +struct rtldsa_93xx_lag_entry; + +#define MAX_LAGS 16 int rtldsa_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info); int rtldsa_lag_del(struct dsa_switch *ds, int group, int port); diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mac.h b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mac.h new file mode 100644 index 00000000000..26d97ef38ee --- /dev/null +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mac.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _OTTO_MAC_H +#define _OTTO_MAC_H + +#include + +/* MAC definitions shared with family and DSA code. */ +#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) + +#define RTL83XX_FORCE_EN BIT(0) +#define RTL83XX_FORCE_LINK_EN BIT(1) + +#define RTL930X_FORCE_EN BIT(0) +#define RTL930X_FORCE_LINK_EN BIT(1) + +#endif /* _OTTO_MAC_H */ diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mirror.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mirror.c index 21ec3689e24..8e7df07d986 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mirror.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mirror.c @@ -7,6 +7,14 @@ #include "mirror.h" #include "rtl-otto.h" +#define RTL930X_MIR_CTRL (0xA2A0) +#define RTL930X_MIR_DPM_CTRL (0xA2C0) +#define RTL930X_MIR_SPM_CTRL (0xA2B0) + +#define RTL931X_MIR_CTRL (0xAF00) +#define RTL931X_MIR_DPM_CTRL (0xAF30) +#define RTL931X_MIR_SPM_CTRL (0xAF10) + int rtldsa_838x_get_mirror_config(struct rtldsa_mirror_config *config, int group, int port) { config->ctrl = RTL838X_MIR_CTRL + group * 4; diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mirror.h b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mirror.h index e3234a739c0..25c1e4acc09 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mirror.h +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/mirror.h @@ -5,6 +5,15 @@ #include +/* Port Mirroring */ +#define RTL838X_MIR_CTRL (0x5D00) +#define RTL838X_MIR_DPM_CTRL (0x5D20) +#define RTL838X_MIR_SPM_CTRL (0x5D10) + +#define RTL839X_MIR_CTRL (0x2500) +#define RTL839X_MIR_DPM_CTRL (0x2530) +#define RTL839X_MIR_SPM_CTRL (0x2510) + struct dsa_switch; struct dsa_mall_mirror_tc_entry; struct netlink_ext_ack; diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/pie.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/pie.c index 9e4f93cc235..d15188a0cbe 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/pie.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/pie.c @@ -7,6 +7,46 @@ #include "pie.h" #include "rtl-otto.h" +/* Packet Inspection Engine */ +#define RTL838X_METER_GLB_CTRL (0x4B08) +#define RTL839X_METER_GLB_CTRL (0x1300) +#define RTL930X_METER_GLB_CTRL (0xa0a0) +#define RTL931X_METER_GLB_CTRL (0x411C) + +#define RTL839X_ACL_CTRL (0x1288) + +#define RTL838X_ACL_BLK_LOOKUP_CTRL (0x6100) +#define RTL839X_ACL_BLK_LOOKUP_CTRL (0x1280) +#define RTL930X_PIE_BLK_LOOKUP_CTRL (0xa5a0) +#define RTL931X_PIE_BLK_LOOKUP_CTRL (0x4180) + +#define RTL838X_ACL_BLK_PWR_CTRL (0x6104) +#define RTL839X_PS_ACL_PWR_CTRL (0x049c) + +#define RTL838X_ACL_BLK_TMPLTE_CTRL(block) (0x6108 + ((block) << 2)) +#define RTL839X_ACL_BLK_TMPLTE_CTRL(block) (0x128c + ((block) << 2)) +#define RTL930X_PIE_BLK_TMPLTE_CTRL(block) (0xa624 + ((block) << 2)) +#define RTL931X_PIE_BLK_TMPLTE_CTRL(block) (0x4214 + ((block) << 2)) + +#define RTL838X_ACL_BLK_GROUP_CTRL (0x615C) + +#define RTL838X_ACL_CLR_CTRL (0x6168) +#define RTL839X_ACL_CLR_CTRL (0x12fc) +#define RTL930X_PIE_CLR_CTRL (0xa66c) +#define RTL931X_PIE_CLR_CTRL (0x42D8) + +#define RTL838X_DMY_REG27 (0x3378) + +#define RTL838X_ACL_PORT_LOOKUP_CTRL(p) (0x616C + (((p) << 2))) +#define RTL930X_ACL_PORT_LOOKUP_CTRL(p) (0xA784 + (((p) << 2))) +#define RTL931X_ACL_PORT_LOOKUP_CTRL(p) (0x44F8 + (((p) << 2))) + +#define RTL930X_PIE_BLK_PHASE_CTRL (0xA5A4) +#define RTL931X_PIE_BLK_PHASE_CTRL (0x4184) + +#define N_FIXED_FIELDS 12 +#define N_FIXED_FIELDS_RTL931X 14 + /* RTL838X */ /* see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c */ diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/pie.h b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/pie.h index d4157519b9b..a7c809d4ab2 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/pie.h +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/pie.h @@ -4,6 +4,16 @@ #include +/* PIE actions */ +#define PIE_ACT_COPY_TO_PORT 2 +#define PIE_ACT_REDIRECT_TO_PORT 4 +#define PIE_ACT_ROUTE_UC 6 +#define PIE_ACT_VID_ASSIGN 0 + +#define PIE_BLOCK_SIZE 128 +#define MAX_PIE_ENTRIES (18 * PIE_BLOCK_SIZE) +#define MAX_COUNTERS 2048 + struct pie_rule; struct rtl838x_switch_priv; diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/qos.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/qos.c index 3d259d9f558..559773615fe 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/qos.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/qos.c @@ -7,6 +7,78 @@ #include "qos.h" #include "rtl-otto.h" +#define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2))) + +#define RTL838X_SCHED_P_EGR_RATE_CTRL(p) (0xC008 + (((p) << 7))) + +/* QoS */ +#define RTL838X_QM_INTPRI2QID_CTRL (0x5F00) +#define RTL839X_QM_INTPRI2QID_CTRL(q) (0x1110 + (q << 2)) +#define RTL839X_QM_PORT_QNUM(p) (0x1130 + (((p / 10) << 2))) +#define RTL839X_PRI_SEL_PORT_PRI(p) (0x10A8 + (((p / 10) << 2))) +#define RTL838X_QM_PKT2CPU_INTPRI_MAP (0x5F10) +#define RTL839X_QM_PKT2CPU_INTPRI_MAP (0x1154) +#define RTL838X_PRI_SEL_TBL_CTRL(i) (0x5FD8 + (((i) << 2))) +#define RTL839X_PRI_SEL_TBL_CTRL(i) (0x10D0 + (((i) << 2))) +#define RTL838X_QM_PKT2CPU_INTPRI_1 (0x5F08) +#define RTL838X_QM_PKT2CPU_INTPRI_2 (0x5F0C) +#define RTL839X_OAM_CTRL (0x2100) +#define RTL839X_OAM_PORT_ACT_CTRL(p) (0x2104 + (((p) << 2))) +#define RTL839X_RMK_PORT_DEI_TAG_CTRL(p) (0x6A9C + (((p >> 5) << 2))) +#define RTL839X_PRI_SEL_IPRI_REMAP (0x1080) +#define RTL838X_PRI_SEL_IPRI_REMAP (0x5F8C) +#define RTL839X_PRI_SEL_DEI2DP_REMAP (0x10EC) +#define RTL839X_RMK_DEI_CTRL (0x6AA4) +#define RTL839X_WRED_PORT_THR_CTRL(i) (0x6084 + ((i) << 2)) +#define RTL839X_WRED_QUEUE_THR_CTRL(q, i) (0x6090 + ((q) * 12) + ((i) << 2)) +#define RTL838X_PRI_DSCP_INVLD_CTRL0 (0x5FE8) +#define RTL838X_RMK_IPRI_CTRL (0xA460) +#define RTL838X_RMK_OPRI_CTRL (0xA464) +#define RTL838X_SCHED_P_TYPE_CTRL(p) (0xC04C + (((p) << 7))) +#define RTL838X_SCHED_LB_CTRL(p) (0xC004 + (((p) << 7))) +#define RTL838X_FC_P_EGR_DROP_CTRL(p) (0x6B1C + (((p) << 2))) + +#define RTL930X_REMAP_DSCP(p) (0x9B04 + (((p) / 10) * 4)) +#define RTL931X_REMAP_DSCP(p) (0x9034 + (((p) / 10) * 4)) +#define RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(p) \ + (((p) % 10) * 3) +#define RTL93XX_REMAP_DSCP_INTPRI_DSCP_MASK(index) \ + (0x7 << RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(index)) + +#define RTL930X_PORT_TBL_IDX_CTRL(port) (0x9B20 + (((port) / 16) * 4)) +#define RTL931X_PORT_TBL_IDX_CTRL(port) (0x9064 + (((port) / 16) * 4)) +#define RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port) \ + (((port) & 0xF) << 1) +#define RTL93XX_PORT_TBL_IDX_CTRL_IDX_MASK(port) \ + (0x3 << RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port)) + +#define RTL930X_PRI_SEL_TBL_CTRL(group) (0x9B28 + ((group) * 4)) +#define RTL931X_PRI_SEL_TBL_CTRL(group) (0x9074 + ((group) * 8)) + +#define RTL93XX_PRI_SEL_TBL_CTRL_OTAG_MASK GENMASK(19, 16) +#define RTL93XX_PRI_SEL_TBL_CTRL_ITAG_MASK GENMASK(15, 12) +#define RTL93XX_PRI_SEL_TBL_CTRL_DSCP_MASK GENMASK(11, 8) +#define RTL93XX_PRI_SEL_TBL_CTRL_PORT_MASK GENMASK(3, 0) + +/* port: 0-23, index: 0-7 */ +#define RTL930X_SCHED_PORT_Q_CTRL_SET0(port, index) \ + (0x3D48 + ((port) * 384) + ((index) * 4)) +/* port: 24-27, index: 0-11 */ +#define RTL930X_SCHED_PORT_Q_CTRL_SET1(port, index) \ + ((0xE860 + ((port) - 24) * 48) + ((index) * 4)) +/* port: 0-51, index: 0-7 */ +#define RTL931X_SCHED_PORT_Q_CTRL_SET0(port, index) \ + (0x2888 + ((port) << 5) + ((index) * 4)) +/* port: 52-55, index: 0-11 */ +#define RTL931X_SCHED_PORT_Q_CTRL_SET1(port, index) \ + ((0x2F08 + ((port) - 52) * 48) + ((index) * 4)) + +#define RTL930X_QM_INTPRI2QID_CTRL (0xA320) +#define RTL931X_QM_INTPRI2QID_CTRL (0xA9D0) + +#define MAX_PRIOS 8 +#define DSCP_MAP_MAX 64 + enum scheduler_type { WEIGHTED_FAIR_QUEUE = 0, WEIGHTED_ROUND_ROBIN, diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h index 168d747c1f3..aa5567aed93 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h @@ -8,531 +8,15 @@ #include +#include "l2.h" +#include "l3_limits.h" +#include "lag.h" #include "mirror.h" +#include "pie.h" #include "stats.h" #include "stp.h" #include "vlan.h" -/* Register definition */ -#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7))) -#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7))) -#define RTL930X_MAC_PORT_CTRL(port) (0x3260 + (((port) << 6))) -#define RTL931X_MAC_PORT_CTRL (0x6004) - -#define RTL930X_MAC_L2_PORT_CTRL(port) (0x3268 + (((port) << 6))) -#define RTL931X_MAC_L2_PORT_CTRL (0x6000) - -/* MAC maximum packet length (jumbo frame) control. - * - * The switch MAC drops frames whose L2 length exceeds the configured maximum. - * A family holds either one register per user port or a single one for the - * whole switch. The length is a direct byte value held in two 14-bit fields - * (high-speed links in [13:0], 10/100M links in [27:14]); bit 28 selects - * whether VLAN tag bytes count towards the limit. - */ - -/* RTL930x holds one register per user port, inside the 64-byte MAC block of - * the port. The CPU port has a row of its own, which the ethernet driver owns - * and programs from the conduit MTU. Register offsets taken from the - * reverse-engineered Realtek register maps at https://svanheule.net/realtek/ - */ -#define RTL930X_MAC_L2_PORT_MAX_LEN_CTRL(port) (0x326C + (((port) << 6))) -/* RTL931x covers ports 0 to 55 only, one word each. The CPU port has no row: - * the word that would follow the array is MAC_DBG_SEL_CTRL. - */ -#define RTL931X_MAC_L2_PORT_MAX_LEN_CTRL (0x5554) -/* RTL838x and RTL839x hold one limit for the whole switch instead, bounding - * the CPU port with it. RTL838x mirrors it in a second register, and the - * vendor SDK writes both (dal_maple_switch_maxPktLenLinkSpeed_set()). - */ -#define RTL838X_MAC_MAX_LEN_CTRL (0xa9e0) -#define RTL838X_MAC_MAX_LEN_CTRL_DUP (0x6b00) -#define RTL839X_MAC_MAX_LEN_CTRL (0x02b0) - -/* Both length fields are 14 bits wide (hardware maximum 16383 bytes). */ -#define RTLDSA_MAC_MAX_LEN_FIELD GENMASK(13, 0) -/* Mask of both length fields, leaving the tag-inclusion bit (28) untouched. */ -#define RTLDSA_MAC_MAX_LEN_MASK \ - (RTLDSA_MAC_MAX_LEN_FIELD | (RTLDSA_MAC_MAX_LEN_FIELD << 14)) -/* Encode @len into both the high-speed and the 10/100M length field. */ -#define RTLDSA_MAC_MAX_LEN_VAL(len) \ - (((len) & RTLDSA_MAC_MAX_LEN_FIELD) | (((len) & RTLDSA_MAC_MAX_LEN_FIELD) << 14)) - -/* Largest frame each family switches; the length field would allow 16383 */ -#define RTL930X_MAX_FRAME 12288 -#define RTL931X_MAX_FRAME 12288 -/* RTL838x stops at what its datasheet gives, below the vendor SDK value */ -#define RTL838X_MAX_FRAME 10000 -#define RTL839X_MAX_FRAME 12288 - -#define RTL838X_RST_GLB_CTRL_0 (0x003c) - -#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) -#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) -#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C) -#define RTL931X_MAC_FORCE_MODE_CTRL (0x0DCC) - -#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2)) -#define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3)) - -/* Table access registers */ -#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) -#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) -#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8) -#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2)) - -#define RTL839X_TBL_ACCESS_CTRL_0 (0x1190) -#define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2)) -#define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80) -#define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2)) -#define RTL839X_TBL_ACCESS_CTRL_2 (0x611C) -#define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2))) - -#define RTL930X_TBL_ACCESS_CTRL_0 (0xB340) -#define RTL930X_TBL_ACCESS_DATA_0(idx) (0xB344 + ((idx) << 2)) -#define RTL930X_TBL_ACCESS_CTRL_1 (0xB3A0) -#define RTL930X_TBL_ACCESS_DATA_1(idx) (0xB3A4 + ((idx) << 2)) -#define RTL930X_TBL_ACCESS_CTRL_2 (0xCE04) -#define RTL930X_TBL_ACCESS_DATA_2(i) (0xCE08 + (((i) << 2))) - -#define RTL931X_TBL_ACCESS_CTRL_0 (0x8500) -#define RTL931X_TBL_ACCESS_DATA_0(idx) (0x8508 + ((idx) << 2)) -#define RTL931X_TBL_ACCESS_CTRL_1 (0x40C0) -#define RTL931X_TBL_ACCESS_DATA_1(idx) (0x40C4 + ((idx) << 2)) -#define RTL931X_TBL_ACCESS_CTRL_2 (0x8528) -#define RTL931X_TBL_ACCESS_DATA_2(i) (0x852C + (((i) << 2))) -#define RTL931X_TBL_ACCESS_CTRL_3 (0x0200) -#define RTL931X_TBL_ACCESS_DATA_3(i) (0x0204 + (((i) << 2))) -#define RTL931X_TBL_ACCESS_CTRL_4 (0x20DC) -#define RTL931X_TBL_ACCESS_DATA_4(i) (0x20E0 + (((i) << 2))) -#define RTL931X_TBL_ACCESS_CTRL_5 (0x7E1C) -#define RTL931X_TBL_ACCESS_DATA_5(i) (0x7E20 + (((i) << 2))) - -/* MAC handling */ -#define RTL838X_MAC_LINK_STS (0xa188) -#define RTL839X_MAC_LINK_STS (0x0390) -#define RTL930X_MAC_LINK_STS (0xCB10) -#define RTL931X_MAC_LINK_STS (0x0EC0) - -/* MAC link state bits */ -#define RTL_SPEED_10 0 -#define RTL_SPEED_100 1 -#define RTL_SPEED_1000 2 -#define RTL_SPEED_2500 5 -#define RTL_SPEED_5000 6 -#define RTL_SPEED_10000 4 - -#define RTL83XX_FORCE_EN BIT(0) -#define RTL83XX_FORCE_LINK_EN BIT(1) - -#define RTL838X_NWAY_EN BIT(2) -#define RTL838X_DUPLEX_MODE BIT(3) -#define RTL838X_SPEED_SHIFT (4) -#define RTL838X_SPEED_MASK (3 << RTL838X_SPEED_SHIFT) -#define RTL838X_TX_PAUSE_EN BIT(6) -#define RTL838X_RX_PAUSE_EN BIT(7) -#define RTL838X_MAC_FORCE_FC_EN BIT(8) - -#define RTL839X_DUPLEX_MODE BIT(2) -#define RTL839X_SPEED_SHIFT (3) -#define RTL839X_SPEED_MASK (3 << RTL839X_SPEED_SHIFT) -#define RTL839X_TX_PAUSE_EN BIT(5) -#define RTL839X_RX_PAUSE_EN BIT(6) -#define RTL839X_MAC_FORCE_FC_EN BIT(7) - -#define RTL930X_FORCE_EN BIT(0) -#define RTL930X_FORCE_LINK_EN BIT(1) -#define RTL930X_DUPLEX_MODE BIT(2) -#define RTL930X_SPEED_SHIFT (3) -#define RTL930X_SPEED_MASK (15 << RTL930X_SPEED_SHIFT) -#define RTL930X_TX_PAUSE_EN BIT(7) -#define RTL930X_RX_PAUSE_EN BIT(8) -#define RTL930X_MAC_FORCE_FC_EN BIT(9) - -#define RTL931X_FORCE_EN BIT(9) -#define RTL931X_FORCE_LINK_EN BIT(0) -#define RTL931X_DUPLEX_MODE BIT(2) -#define RTL931X_MAC_FORCE_FC_EN BIT(4) -#define RTL931X_TX_PAUSE_EN BIT(16) -#define RTL931X_RX_PAUSE_EN BIT(17) - -/* EEE */ -#define RTL838X_MAC_EEE_ABLTY (0xa1a8) -#define RTL838X_EEE_PORT_TX_EN (0x014c) -#define RTL838X_EEE_PORT_RX_EN (0x0150) -#define RTL838X_EEE_CLK_STOP_CTRL (0x0148) -#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) -#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) - -#define RTL839X_EEE_TX_TIMER_GELITE_CTRL (0x042C) -#define RTL839X_EEE_TX_TIMER_GIGA_CTRL (0x0430) -#define RTL839X_EEE_TX_TIMER_10G_CTRL (0x0434) -#define RTL839X_EEE_CTRL(p) (0x8008 + ((p) << 7)) -#define RTL839X_MAC_EEE_ABLTY (0x03C8) - -#define RTL930X_MAC_EEE_ABLTY (0xCB34) -#define RTL930X_EEE_CTRL(p) (0x3274 + ((p) << 6)) -#define RTL930X_EEEP_PORT_CTRL(p) (0x3278 + ((p) << 6)) - -#define RTL931X_MAC_EEE_ABLTY (0x0f08) - -/* L2 functionality */ -#define RTL838X_L2_CTRL_0 (0x3200) -#define RTL839X_L2_CTRL_0 (0x3800) -#define RTL930X_L2_CTRL (0x8FD8) -#define RTL931X_L2_CTRL (0xC800) -#define RTL838X_L2_CTRL_1 (0x3204) -#define RTL839X_L2_CTRL_1 (0x3804) -#define RTL930X_L2_AGE_CTRL (0x8FDC) -#define RTL931X_L2_AGE_CTRL (0xC804) -#define RTL838X_L2_PORT_AGING_OUT (0x3358) -#define RTL839X_L2_PORT_AGING_OUT (0x3b74) -#define RTL930X_L2_PORT_AGE_CTRL (0x8FE0) -#define RTL931X_L2_PORT_AGE_CTRL (0xc808) -#define RTL838X_TBL_ACCESS_L2_CTRL (0x6900) -#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) -#define RTL930X_TBL_ACCESS_L2_CTRL (0xB320) -#define RTL930X_TBL_ACCESS_L2_METHOD_CTRL (0xB324) -#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2)) -#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2)) -#define RTL930X_TBL_ACCESS_L2_DATA(idx) (0xab08 + ((idx) << 2)) - -#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) -#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) -#define RTL930X_L2_TBL_FLUSH_CTRL (0x9404) -#define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C) - -#define RTL838X_L2_LRN_CONSTRT (0x329C) -#define RTL839X_L2_LRN_CONSTRT (0x3910) -#define RTL930X_L2_LRN_CONSTRT_CTRL (0x909c) -#define RTL931X_L2_LRN_CONSTRT_CTRL (0xC964) - -#define RTL838X_L2_FLD_PMSK (0x3288) -#define RTL839X_L2_FLD_PMSK (0x38EC) -#define RTL930X_L2_BC_FLD_PMSK (0x9068) -#define RTL931X_L2_BC_FLD_PMSK (0xC8FC) - -#define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064) -#define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4) - -#define RTL838X_L2_BC_FLD(pmsk) (pmsk << 9) -#define RTL838X_L2_UNKN_UC_FLD(pmsk) (pmsk) -#define RTL839X_L2_BC_FLD(pmsk) (pmsk << 12) -#define RTL839X_L2_UNKN_UC_FLD(pmsk) (pmsk) - -#define RTL838X_L2_LRN_CONSTRT_EN (0x3368) -#define RTL838X_L2_PORT_LRN_CONSTRT (0x32A0) -#define RTL839X_L2_PORT_LRN_CONSTRT (0x3914) -#define RTL930X_L2_LRN_PORT_CONSTRT_CTRL (0x90A4) -#define RTL931X_L2_LRN_PORT_CONSTRT_CTRL (0xC96C) - -#define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2))) -#define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2))) -#define RTL930X_L2_PORT_SALRN(p) (0x8FEC + (((p >> 4) << 2))) -#define RTL931X_L2_PORT_NEW_SALRN(p) (0xC820 + (((p >> 4) << 2))) - -#define SALRN_PORT_SHIFT(p) ((p % 16) * 2) -#define SALRN_MODE_MASK 0x3 -#define SALRN_MODE_HARDWARE 0 -#define SALRN_MODE_DISABLED 2 - -#define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2))) -#define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2))) -#define RTL930X_L2_PORT_NEW_SA_FWD(p) (0x8FF4 + (((p / 10) << 2))) -#define RTL931X_L2_PORT_NEW_SA_FWD(p) (0xC830 + (((p / 10) << 2))) - -#define RTL838X_L2_PORT_MV_ACT(p) (0x335c + (((p >> 4) << 2))) -#define RTL839X_L2_PORT_MV_ACT(p) (0x3b80 + (((p >> 4) << 2))) - -#define RTL838X_L2_PORT_STATIC_MV_ACT(p) (0x327c + (((p >> 4) << 2))) -#define RTL839X_L2_PORT_STATIC_MV_ACT(p) (0x38dc + (((p >> 4) << 2))) - -#define MV_ACT_PORT_SHIFT(p) ((p % 16) * 2) -#define MV_ACT_MASK 0x3 -#define MV_ACT_FORWARD 0 -#define MV_ACT_DROP 1 -#define MV_ACT_TRAP2CPU 2 -#define MV_ACT_COPY2CPU 3 - -#define RTL930X_L2_PORT_SABLK_CTRL (0x905c) -#define RTL930X_L2_PORT_DABLK_CTRL (0x9060) - -#define RTL838X_L2_PORT_LM_ACT(p) (0x3208 + ((p) << 2)) - -/* Port Mirroring */ -#define RTL838X_MIR_CTRL (0x5D00) -#define RTL838X_MIR_DPM_CTRL (0x5D20) -#define RTL838X_MIR_SPM_CTRL (0x5D10) - -#define RTL839X_MIR_CTRL (0x2500) -#define RTL839X_MIR_DPM_CTRL (0x2530) -#define RTL839X_MIR_SPM_CTRL (0x2510) - -#define RTL930X_MIR_CTRL (0xA2A0) -#define RTL930X_MIR_DPM_CTRL (0xA2C0) -#define RTL930X_MIR_SPM_CTRL (0xA2B0) - -#define RTL931X_MIR_CTRL (0xAF00) -#define RTL931X_MIR_DPM_CTRL (0xAF30) -#define RTL931X_MIR_SPM_CTRL (0xAF10) - -/* Storm/rate control and scheduling */ -#define RTL838X_STORM_CTRL (0x4700) -#define RTL839X_STORM_CTRL (0x1800) -#define RTL838X_STORM_CTRL_LB_CTRL(p) (0x4884 + (((p) << 2))) -#define RTL838X_STORM_CTRL_BURST_PPS_0 (0x4874) -#define RTL838X_STORM_CTRL_BURST_PPS_1 (0x4878) -#define RTL838X_STORM_CTRL_BURST_0 (0x487c) -#define RTL838X_STORM_CTRL_BURST_1 (0x4880) -#define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0 (0x1804) -#define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1 (0x1808) -#define RTL838X_SCHED_CTRL (0xB980) -#define RTL839X_SCHED_CTRL (0x60F4) -#define RTL838X_SCHED_LB_TICK_TKN_CTRL_0 (0xAD58) -#define RTL838X_SCHED_LB_TICK_TKN_CTRL_1 (0xAD5C) -#define RTL839X_SCHED_LB_TICK_TKN_CTRL_0 (0x1804) -#define RTL839X_SCHED_LB_TICK_TKN_CTRL_1 (0x1808) -#define RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL (0x2000) -#define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0 (0x1604) -#define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1 (0x1608) -#define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60F8) -#define RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL (0x6200) -#define RTL838X_SCHED_LB_THR (0xB984) -#define RTL839X_SCHED_LB_THR (0x60FC) -#define RTL838X_SCHED_P_EGR_RATE_CTRL(p) (0xC008 + (((p) << 7))) -#define RTL838X_SCHED_Q_EGR_RATE_CTRL(p, q) (0xC00C + (p << 7) + (((q) << 2))) -#define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C) -#define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710) -#define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714) -#define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p) (0x180c + (((p >> 5) << 2))) -#define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p) (0x1814 + (((p >> 5) << 2))) -#define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p) (0x181c + (((p >> 5) << 2))) -#define RTL838X_STORM_CTRL_PORT_UC(p) (0x4718 + (((p) << 2))) -#define RTL838X_STORM_CTRL_PORT_MC(p) (0x478c + (((p) << 2))) -#define RTL838X_STORM_CTRL_PORT_BC(p) (0x4800 + (((p) << 2))) -#define RTL839X_STORM_CTRL_PORT_UC_0(p) (0x185C + (((p) << 3))) -#define RTL839X_STORM_CTRL_PORT_UC_1(p) (0x1860 + (((p) << 3))) -#define RTL839X_STORM_CTRL_PORT_MC_0(p) (0x19FC + (((p) << 3))) -#define RTL839X_STORM_CTRL_PORT_MC_1(p) (0x1a00 + (((p) << 3))) -#define RTL839X_STORM_CTRL_PORT_BC_0(p) (0x1B9C + (((p) << 3))) -#define RTL839X_STORM_CTRL_PORT_BC_1(p) (0x1BA0 + (((p) << 3))) -#define RTL839X_TBL_ACCESS_CTRL_2 (0x611C) -#define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2))) -#define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p) (0x1618 + (((p) << 3))) -#define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_1(p) (0x161C + (((p) << 3))) -#define RTL839X_IGR_BWCTRL_PORT_CTRL_0(p) (0x1640 + (((p) << 3))) -#define RTL839X_IGR_BWCTRL_PORT_CTRL_1(p) (0x1644 + (((p) << 3))) -#define RTL839X_IGR_BWCTRL_CTRL_LB_THR (0x1614) - -/* Link aggregation (Trunking) */ -#define TRUNK_DISTRIBUTION_ALGO_SPA_BIT BIT(0) -#define TRUNK_DISTRIBUTION_ALGO_SMAC_BIT BIT(1) -#define TRUNK_DISTRIBUTION_ALGO_DMAC_BIT BIT(2) - -#define TRUNK_DISTRIBUTION_ALGO_SIP_BIT BIT(3) -#define TRUNK_DISTRIBUTION_ALGO_DIP_BIT BIT(4) -#define TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT BIT(5) -#define TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT BIT(6) -#define TRUNK_DISTRIBUTION_ALGO_VLAN_BIT BIT(7) -#define TRUNK_DISTRIBUTION_ALGO_MASKALL GENMASK(6, 0) - -#define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT BIT(0) -#define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT BIT(1) -#define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT BIT(2) -#define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT BIT(3) - -#define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT BIT(4 + 0) -#define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT BIT(4 + 1) -#define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT BIT(4 + 2) -#define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT BIT(4 + 3) -#define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT BIT(4 + 4) -#define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT BIT(4 + 5) -#define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT BIT(4 + 6) -#define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT BIT(4 + 7) -#define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT BIT(4 + 8) -#define TRUNK_DISTRIBUTION_ALGO_L3_FLOW_LABEL_BIT BIT(4 + 9) - -#define RTL838X_TRK_MBR_CTR (0x3E00) -#define RTL838X_TRK_HASH_IDX_CTRL (0x3E20) -#define RTL838X_TRK_HASH_CTRL (0x3E24) - -#define RTL839X_TRK_MBR_CTR (0x2200) -#define RTL839X_TRK_HASH_IDX_CTRL (0x2280) -#define RTL839X_TRK_HASH_CTRL (0x2284) - -#define RTL930X_LOCAL_PORT_TRK_MAP (0xD0C8) -#define RTL930X_TRK_ID_CTRL (0xA3A8) -#define RTL930X_TRK_MBR_CTRL (0xA41C) -#define RTL930X_TRK_HASH_CTRL (0x9F80) -#define RTL930X_TRK_CTRL (0x9F88) -#define RTL930X_TRK_SHIFT_CTRL (0x9F8C) -#define RTL930X_TRK_LOCAL_TBL_REFRESH (0x9F90) -#define RTL930X_TRK_LOCAL_TBL (0x9F94) -#define RTL930X_TRK_STK_CTRL (0xA07C) - -#define RTL930X_TRK_ID_CTRL_TRK_VALID BIT(6) -#define RTL930X_TRK_ID_CTRL_TRK_ID GENMASK(5, 0) - -#define RTL930X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR BIT(6) -#define RTL930X_LOCAL_PORT_TRK_MAP_TRK_ID GENMASK(5, 0) - -#define RTL930X_SRC_TRK_MAP_TRK_VALID BIT(31) -#define RTL930X_SRC_TRK_MAP_TRK_ID GENMASK(30, 25) - -#define RTL931X_LOCAL_PORT_TRK_MAP (0x4CAC) -#define RTL931X_TRK_ID_CTRL (0xB800) -#define RTL931X_TRK_MBR_CTRL (0xB8D0) -#define RTL931X_TRK_HASH_CTRL (0xBA70) -#define RTL931X_TRK_CTRL (0xBA78) -#define RTL931X_TRK_SHIFT_CTRL (0xBA7C) -#define RTL931X_TRK_LOCAL_TBL_REFRESH (0xBA80) -#define RTL931X_TRK_LOCAL_TBL (0xBA84) -#define RTL931X_TRK_STK_CTRL (0xBE94) - -#define RLT931X_TRK_ID_CTRL_TRK_ID GENMASK(6, 0) -#define RTL931X_TRK_ID_CTRL_TRK_VALID BIT(7) - -#define RTL931X_LOCAL_PORT_TRK_MAP_IS_TRK_MBR BIT(7) -#define RTL931X_LOCAL_PORT_TRK_MAP_TRK_ID GENMASK(6, 0) - -#define RTL931X_SRC_TRK_MAP_TRK_ID GENMASK(30, 24) -#define RTL931X_SRC_TRK_MAP_TRK_ID_VALID BIT(31) - -#define GENMASK_MOD(high, low) GENMASK((high) % 32, (low) % 32) -#define BIT_MOD(bit) BIT((bit) % 32) - -/* RTL930X LAG Table offsets */ -#define RTL930X_LAG_NUM_TX_CANDI GENMASK_MOD(92, 89) -#define RTL930X_LAG_L2_HASH_MSK_IDX BIT_MOD(88) -#define RTL930X_LAG_IP4_HASH_MSK_IDX BIT_MOD(87) -#define RTL930X_LAG_IP6_HASH_MSK_IDX BIT_MOD(86) -#define RTL930X_LAG_SEP_DLF_BCAST_EN BIT_MOD(85) -#define RTL930X_LAG_SEP_KWN_MC_EN BIT_MOD(84) -#define RTL930X_LAG_TRK_DEV7 GENMASK_MOD(83, 80) -#define RTL930X_LAG_TRK_PORT7 GENMASK_MOD(79, 74) -#define RTL930X_LAG_TRK_DEV6 GENMASK_MOD(73, 70) -#define RTL930X_LAG_TRK_PORT6 GENMASK_MOD(69, 64) - -#define RTL930X_LAG_TRK_DEV5 GENMASK_MOD(61, 58) -#define RTL930X_LAG_TRK_PORT5 GENMASK_MOD(57, 52) -#define RTL930X_LAG_TRK_DEV4 GENMASK_MOD(51, 48) -#define RTL930X_LAG_TRK_PORT4 GENMASK_MOD(47, 42) -#define RTL930X_LAG_TRK_DEV3 GENMASK_MOD(41, 38) -#define RTL930X_LAG_TRK_PORT3 GENMASK_MOD(37, 32) - -#define RTL930X_LAG_TRK_DEV2 GENMASK_MOD(29, 26) -#define RTL930X_LAG_TRK_PORT2 GENMASK_MOD(25, 20) -#define RTL930X_LAG_TRK_DEV1 GENMASK_MOD(19, 16) -#define RTL930X_LAG_TRK_PORT1 GENMASK_MOD(15, 10) -#define RTL930X_LAG_TRK_DEV0 GENMASK_MOD(9, 6) -#define RTL930X_LAG_TRK_PORT0 GENMASK_MOD(5, 0) - -/* RTL931X LAG Table offsets */ -#define RTL931X_LAG_NUM_TX_CANDI GENMASK_MOD(92, 89) -#define RTL931X_LAG_L2_HASH_MSK_IDX BIT_MOD(88) -#define RTL931X_LAG_IP4_HASH_MSK_IDX BIT_MOD(87) -#define RTL931X_LAG_IP6_HASH_MSK_IDX BIT_MOD(86) -#define RTL931X_LAG_SEP_FLOOD_EN BIT_MOD(85) -#define RTL931X_LAG_SEP_KWN_MC_EN BIT_MOD(84) -#define RTL931X_LAG_TRK_DEV7 GENMASK_MOD(83, 80) -#define RTL931X_LAG_TRK_PORT7 GENMASK_MOD(79, 74) -#define RTL931X_LAG_TRK_DEV6 GENMASK_MOD(73, 70) -#define RTL931X_LAG_TRK_PORT6 GENMASK_MOD(69, 64) - -#define RTL931X_LAG_TRK_DEV5 GENMASK_MOD(61, 58) -#define RTL931X_LAG_TRK_PORT5 GENMASK_MOD(57, 52) -#define RTL931X_LAG_TRK_DEV4 GENMASK_MOD(51, 48) -#define RTL931X_LAG_TRK_PORT4 GENMASK_MOD(47, 42) -#define RTL931X_LAG_TRK_DEV3 GENMASK_MOD(41, 38) -#define RTL931X_LAG_TRK_PORT3 GENMASK_MOD(37, 32) - -#define RTL931X_LAG_TRK_DEV2 GENMASK_MOD(29, 26) -#define RTL931X_LAG_TRK_PORT2 GENMASK_MOD(25, 20) -#define RTL931X_LAG_TRK_DEV1 GENMASK_MOD(19, 16) -#define RTL931X_LAG_TRK_PORT1 GENMASK_MOD(15, 10) -#define RTL931X_LAG_TRK_DEV0 GENMASK_MOD(9, 6) -#define RTL931X_LAG_TRK_PORT0 GENMASK_MOD(5, 0) - -/* Attack prevention */ -#define RTL838X_ATK_PRVNT_PORT_EN (0x5B00) -#define RTL838X_ATK_PRVNT_CTRL (0x5B04) -#define RTL838X_ATK_PRVNT_ACT (0x5B08) -#define RTL838X_ATK_PRVNT_STS (0x5B1C) - -/* 802.1X */ -#define RTL838X_RMA_BPDU_FLD_PMSK (0x4348) -#define RTL930X_RMA_BPDU_FLD_PMSK (0x9F18) -#define RTL931X_RMA_BPDU_FLD_PMSK (0x8950) -#define RTL839X_RMA_BPDU_FLD_PMSK (0x125C) - -#define RTL838X_SPCL_TRAP_CTRL (0x6980) -#define RTL838X_SPCL_TRAP_EAPOL_CTRL (0x6988) -#define RTL838X_SPCL_TRAP_ARP_CTRL (0x698C) -#define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984) -#define RTL838X_SPCL_TRAP_IPV6_CTRL (0x6994) -#define RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL (0x6998) - -#define RTL839X_SPCL_TRAP_CTRL (0x1054) -#define RTL839X_SPCL_TRAP_EAPOL_CTRL (0x105C) -#define RTL839X_SPCL_TRAP_ARP_CTRL (0x1060) -#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058) -#define RTL839X_SPCL_TRAP_IPV6_CTRL (0x1064) -#define RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL (0x1068) -#define RTL839X_SPCL_TRAP_SWITCH_IPV4_ADDR_CTRL (0x106C) -#define RTL839X_SPCL_TRAP_CRC_CTRL (0x1070) - -/* Switch interrupts */ -#define RTL838X_IMR_GLB (0x1100) -#define RTL838X_IMR_PORT_LINK_STS_CHG (0x1104) -#define RTL838X_ISR_GLB_SRC (0x1148) -#define RTL838X_ISR_PORT_LINK_STS_CHG (0x114C) - -#define RTL839X_IMR_GLB (0x0064) -#define RTL839X_IMR_PORT_LINK_STS_CHG (0x0068) -#define RTL839X_ISR_GLB_SRC (0x009c) -#define RTL839X_ISR_PORT_LINK_STS_CHG (0x00a0) - -#define RTL930X_IMR_GLB (0xC628) -#define RTL930X_IMR_PORT_LINK_STS_CHG (0xC62C) -#define RTL930X_ISR_GLB (0xC658) -#define RTL930X_ISR_PORT_LINK_STS_CHG (0xC660) - -/* IMR_GLB does not exit on RTL931X */ -#define RTL931X_IMR_PORT_LINK_STS_CHG (0x126C) -#define RTL931X_ISR_GLB_SRC (0x12B4) -#define RTL931X_ISR_PORT_LINK_STS_CHG (0x12B8) - -#define RTL838X_SMI_GLB_CTRL (0xa100) /* used by RTL838x EEE setup */ - -#define RTL838X_LED_GLB_CTRL (0xA000) -#define RTL839X_LED_GLB_CTRL (0x00E4) -#define RTL930X_LED_GLB_CTRL (0xCC00) -#define RTL931X_LED_GLB_CTRL (0x0600) - -/* LED control by switch */ -#define RTL838X_LED_MODE_SEL (0x1004) -#define RTL838X_LED_MODE_CTRL (0xA004) -#define RTL838X_LED_P_EN_CTRL (0xA008) - -/* LED control by software */ -#define RTL838X_LED_SW_CTRL (0xA00C) -#define RTL838X_LED0_SW_P_EN_CTRL (0xA010) -#define RTL838X_LED1_SW_P_EN_CTRL (0xA014) -#define RTL838X_LED2_SW_P_EN_CTRL (0xA018) -#define RTL838X_LED_SW_P_CTRL (0xA01C) -#define RTL838X_LED_SW_P_CTRL_PORT(p) (RTL838X_LED_SW_P_CTRL + (((p) << 2))) - -#define RTL93XX_HASH_MASK_INDEX_L2 (0) -#define RTL93XX_HASH_MASK_INDEX_L23 (1) - -#define RTL93XX_TRK_CTRL_NON_TMN_TUNNEL_HASH_SEL BIT(0) -#define RTL93XX_TRK_CTRL_SEP_PORT_SEL BIT(1) -#define RTL93XX_TRK_CTRL_TRK_STAND_ALONE_MODE BIT(2) -#define RTL93XX_TRK_CTRL_STK_HASH_CAL BIT(3) -#define RTL93XX_TRK_CTRL_LOCAL_FIRST BIT(4) -#define RTL93XX_TRK_CTRL_CONGST_AVOID BIT(5) -#define RTL93XX_TRK_CTRL_LINK_DOWN_AVOID BIT(6) - /* special port action controls */ /* values: * 0 = FORWARD (default) @@ -564,252 +48,6 @@ typedef enum { COPY2CPU, } action_type_t; -enum rtldsa_flood_type { - RTLDSA_FLOOD_TYPE_FORWARD = 0, - RTLDSA_FLOOD_TYPE_DROP, - RTLDSA_FLOOD_TYPE_TRAP2CPU, - RTLDSA_FLOOD_TYPE_COPY2CPU, - RTLDSA_FLOOD_TYPE_TRAP2MASTER, - RTLDSA_FLOOD_TYPE_COPY2MASTER, -}; - -#define RTL838X_RMA_BPDU_CTRL (0x4330) -#define RTL839X_RMA_BPDU_CTRL (0x122C) -#define RTL930X_RMA_BPDU_CTRL (0x9E7C) -#define RTL931X_RMA_BPDU_CTRL (0x881C) - -#define RTL838X_RMA_PTP_CTRL (0x4338) -#define RTL839X_RMA_PTP_CTRL (0x123C) -#define RTL930X_RMA_PTP_CTRL (0x9E88) -#define RTL931X_RMA_PTP_CTRL (0x8834) - -#define RTL838X_RMA_LLDP_CTRL (0x4340) -#define RTL839X_RMA_LLDP_CTRL (0x124C) -#define RTL930X_RMA_LLDP_CTRL (0x9EFC) -#define RTL931X_RMA_LLDP_CTRL (0x8918) - -#define RTL930X_RMA_EAPOL_CTRL (0x9F08) -#define RTL930X_SPCL_TRAP_PORT_CTRL (0xA1A0) -#define RTL931X_RMA_EAPOL_CTRL (0x8930) -#define RTL931X_TRAP_ARP_GRAT_PORT_ACT (0x8C04) - -/* QoS */ -#define RTL838X_QM_INTPRI2QID_CTRL (0x5F00) -#define RTL839X_QM_INTPRI2QID_CTRL(q) (0x1110 + (q << 2)) -#define RTL839X_QM_PORT_QNUM(p) (0x1130 + (((p / 10) << 2))) -#define RTL838X_PRI_SEL_PORT_PRI(p) (0x5FB8 + (((p / 10) << 2))) -#define RTL839X_PRI_SEL_PORT_PRI(p) (0x10A8 + (((p / 10) << 2))) -#define RTL838X_QM_PKT2CPU_INTPRI_MAP (0x5F10) -#define RTL839X_QM_PKT2CPU_INTPRI_MAP (0x1154) -#define RTL838X_PRI_SEL_CTRL (0x10E0) -#define RTL839X_PRI_SEL_CTRL (0x10E0) -#define RTL838X_PRI_SEL_TBL_CTRL(i) (0x5FD8 + (((i) << 2))) -#define RTL839X_PRI_SEL_TBL_CTRL(i) (0x10D0 + (((i) << 2))) -#define RTL838X_QM_PKT2CPU_INTPRI_0 (0x5F04) -#define RTL838X_QM_PKT2CPU_INTPRI_1 (0x5F08) -#define RTL838X_QM_PKT2CPU_INTPRI_2 (0x5F0C) -#define RTL839X_OAM_CTRL (0x2100) -#define RTL839X_OAM_PORT_ACT_CTRL(p) (0x2104 + (((p) << 2))) -#define RTL839X_RMK_PORT_DEI_TAG_CTRL(p) (0x6A9C + (((p >> 5) << 2))) -#define RTL839X_PRI_SEL_IPRI_REMAP (0x1080) -#define RTL838X_PRI_SEL_IPRI_REMAP (0x5F8C) -#define RTL839X_PRI_SEL_DEI2DP_REMAP (0x10EC) -#define RTL839X_PRI_SEL_DSCP2DP_REMAP_ADDR(i) (0x10F0 + (((i >> 4) << 2))) -#define RTL839X_RMK_DEI_CTRL (0x6AA4) -#define RTL839X_WRED_PORT_THR_CTRL(i) (0x6084 + ((i) << 2)) -#define RTL839X_WRED_QUEUE_THR_CTRL(q, i) (0x6090 + ((q) * 12) + ((i) << 2)) -#define RTL838X_PRI_DSCP_INVLD_CTRL0 (0x5FE8) -#define RTL838X_RMK_IPRI_CTRL (0xA460) -#define RTL838X_RMK_OPRI_CTRL (0xA464) -#define RTL838X_SCHED_P_TYPE_CTRL(p) (0xC04C + (((p) << 7))) -#define RTL838X_SCHED_LB_CTRL(p) (0xC004 + (((p) << 7))) -#define RTL838X_FC_P_EGR_DROP_CTRL(p) (0x6B1C + (((p) << 2))) - -#define RTL930X_REMAP_DSCP(p) (0x9B04 + (((p) / 10) * 4)) -#define RTL931X_REMAP_DSCP(p) (0x9034 + (((p) / 10) * 4)) -#define RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(p) \ - (((p) % 10) * 3) -#define RTL93XX_REMAP_DSCP_INTPRI_DSCP_MASK(index) \ - (0x7 << RTL93XX_REMAP_DSCP_INTPRI_DSCP_OFFSET(index)) - -#define RTL930X_PORT_TBL_IDX_CTRL(port) (0x9B20 + (((port) / 16) * 4)) -#define RTL931X_PORT_TBL_IDX_CTRL(port) (0x9064 + (((port) / 16) * 4)) -#define RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port) \ - (((port) & 0xF) << 1) -#define RTL93XX_PORT_TBL_IDX_CTRL_IDX_MASK(port) \ - (0x3 << RTL93XX_PORT_TBL_IDX_CTRL_IDX_OFFSET(port)) - -#define RTL93XX_PRI_SEL_GROUP_0 (0) -#define RTL93XX_PRI_SEL_GROUP_1 (1) - -#define RTL930X_PRI_SEL_TBL_CTRL(group) (0x9B28 + ((group) * 4)) -#define RTL931X_PRI_SEL_TBL_CTRL(group) (0x9074 + ((group) * 8)) -#define RTL931X_PRI_SEL_TBL_CTRL_1BR_MASK GENMASK(15, 12) -#define RTL931X_PRI_SEL_TBL_CTRL_MPLS_MASK GENMASK(11, 8) -#define RTL931X_PRI_SEL_TBL_CTRL_11E_MASK GENMASK(7, 4) -#define RTL931X_PRI_SEL_TBL_CTRL_TUNNEL_MASK GENMASK(3, 0) - -#define RTL93XX_PRI_SEL_TBL_CTRL_ROUT_MASK GENMASK(31, 28) -#define RTL93XX_PRI_SEL_TBL_CTRL_PROT_VLAN_MASK GENMASK(27, 24) -#define RTL93XX_PRI_SEL_TBL_CTRL_MAC_VLAN_MASK GENMASK(23, 20) -#define RTL93XX_PRI_SEL_TBL_CTRL_OTAG_MASK GENMASK(19, 16) -#define RTL93XX_PRI_SEL_TBL_CTRL_ITAG_MASK GENMASK(15, 12) -#define RTL93XX_PRI_SEL_TBL_CTRL_DSCP_MASK GENMASK(11, 8) -#define RTL93XX_PRI_SEL_TBL_CTRL_VACL_MASK GENMASK(7, 4) -#define RTL93XX_PRI_SEL_TBL_CTRL_PORT_MASK GENMASK(3, 0) - -/* port: 0-23, index: 0-7 */ -#define RTL930X_SCHED_PORT_Q_CTRL_SET0(port, index) \ - (0x3D48 + ((port) * 384) + ((index) * 4)) -/* port: 24-27, index: 0-11 */ -#define RTL930X_SCHED_PORT_Q_CTRL_SET1(port, index) \ - ((0xE860 + ((port) - 24) * 48) + ((index) * 4)) -/* port: 0-51, index: 0-7 */ -#define RTL931X_SCHED_PORT_Q_CTRL_SET0(port, index) \ - (0x2888 + ((port) << 5) + ((index) * 4)) -/* port: 52-55, index: 0-11 */ -#define RTL931X_SCHED_PORT_Q_CTRL_SET1(port, index) \ - ((0x2F08 + ((port) - 52) * 48) + ((index) * 4)) - -#define RTL930X_QM_INTPRI2QID_CTRL (0xA320) -#define RTL931X_QM_INTPRI2QID_CTRL (0xA9D0) - -/* Packet Inspection Engine */ -#define RTL838X_METER_GLB_CTRL (0x4B08) -#define RTL839X_METER_GLB_CTRL (0x1300) -#define RTL930X_METER_GLB_CTRL (0xa0a0) -#define RTL931X_METER_GLB_CTRL (0x411C) - -#define RTL839X_ACL_CTRL (0x1288) - -#define RTL838X_ACL_BLK_LOOKUP_CTRL (0x6100) -#define RTL839X_ACL_BLK_LOOKUP_CTRL (0x1280) -#define RTL930X_PIE_BLK_LOOKUP_CTRL (0xa5a0) -#define RTL931X_PIE_BLK_LOOKUP_CTRL (0x4180) - -#define RTL838X_ACL_BLK_PWR_CTRL (0x6104) -#define RTL839X_PS_ACL_PWR_CTRL (0x049c) - -#define RTL838X_ACL_BLK_TMPLTE_CTRL(block) (0x6108 + ((block) << 2)) -#define RTL839X_ACL_BLK_TMPLTE_CTRL(block) (0x128c + ((block) << 2)) -#define RTL930X_PIE_BLK_TMPLTE_CTRL(block) (0xa624 + ((block) << 2)) -#define RTL931X_PIE_BLK_TMPLTE_CTRL(block) (0x4214 + ((block) << 2)) - -#define RTL838X_ACL_BLK_GROUP_CTRL (0x615C) -#define RTL839X_ACL_BLK_GROUP_CTRL (0x12ec) - -#define RTL838X_ACL_CLR_CTRL (0x6168) -#define RTL839X_ACL_CLR_CTRL (0x12fc) -#define RTL930X_PIE_CLR_CTRL (0xa66c) -#define RTL931X_PIE_CLR_CTRL (0x42D8) - -#define RTL838X_DMY_REG27 (0x3378) - -#define RTL838X_ACL_PORT_LOOKUP_CTRL(p) (0x616C + (((p) << 2))) -#define RTL930X_ACL_PORT_LOOKUP_CTRL(p) (0xA784 + (((p) << 2))) -#define RTL931X_ACL_PORT_LOOKUP_CTRL(p) (0x44F8 + (((p) << 2))) - -#define RTL930X_PIE_BLK_PHASE_CTRL (0xA5A4) -#define RTL931X_PIE_BLK_PHASE_CTRL (0x4184) - -/* PIE actions */ -#define PIE_ACT_COPY_TO_PORT 2 -#define PIE_ACT_REDIRECT_TO_PORT 4 -#define PIE_ACT_ROUTE_UC 6 -#define PIE_ACT_VID_ASSIGN 0 - -/* L3 actions */ -#define L3_FORWARD 0 -#define L3_DROP 1 -#define L3_TRAP2CPU 2 -#define L3_COPY2CPU 3 -#define L3_TRAP2MASTERCPU 4 -#define L3_COPY2MASTERCPU 5 -#define L3_HARDDROP 6 - -/* Route entry types */ -#define ROUTE_TYPE_IP4UC 0 -#define ROUTE_TYPE_IP4MC 1 -#define ROUTE_TYPE_IP6UC 2 -#define ROUTE_TYPE_IP6MC 3 - -/* Route actions */ -#define ROUTE_ACT_FORWARD 0 -#define ROUTE_ACT_TRAP2CPU 1 -#define ROUTE_ACT_COPY2CPU 2 -#define ROUTE_ACT_DROP 3 - -/* L3 Routing */ -#define RTL839X_ROUTING_SA_CTRL 0x6afc -#define RTL930X_L3_HOST_TBL_CTRL (0xAB48) -#define RTL930X_L3_IPUC_ROUTE_CTRL (0xAB4C) -#define RTL930X_L3_IP6UC_ROUTE_CTRL (0xAB50) -#define RTL930X_L3_IPMC_ROUTE_CTRL (0xAB54) -#define RTL930X_L3_IP6MC_ROUTE_CTRL (0xAB58) -#define RTL930X_L3_IP_MTU_CTRL(i) (0xAB5C + ((i >> 1) << 2)) -#define RTL930X_L3_IP6_MTU_CTRL(i) (0xAB6C + ((i >> 1) << 2)) -#define RTL930X_L3_HW_LU_KEY_CTRL (0xAC9C) -#define RTL930X_L3_HW_LU_KEY_IP_CTRL (0xACA0) -#define RTL930X_L3_HW_LU_CTRL (0xACC0) -#define RTL930X_L3_IP_ROUTE_CTRL 0xab44 - -/* Port LED Control */ -#define RTL930X_LED_PORT_NUM_CTRL(p) (0xCC04 + (((p >> 4) << 2))) -#define RTL930X_LED_SET0_0_CTRL (0xCC28) -#define RTL930X_LED_PORT_COPR_SET_SEL_CTRL(p) (0xCC2C + (((p >> 4) << 2))) -#define RTL930X_LED_PORT_FIB_SET_SEL_CTRL(p) (0xCC34 + (((p >> 4) << 2))) -#define RTL930X_LED_PORT_COPR_MASK_CTRL (0xCC3C) -#define RTL930X_LED_PORT_FIB_MASK_CTRL (0xCC40) -#define RTL930X_LED_PORT_COMBO_MASK_CTRL (0xCC44) - -#define RTL931X_LED_PORT_NUM_CTRL(p) (0x0604 + (((p >> 4) << 2))) -#define RTL931X_LED_SET0_0_CTRL (0x0630) -#define RTL931X_LED_PORT_COPR_SET_SEL_CTRL(p) (0x0634 + (((p >> 4) << 2))) -#define RTL931X_LED_PORT_FIB_SET_SEL_CTRL(p) (0x0644 + (((p >> 4) << 2))) -#define RTL931X_LED_PORT_COPR_MASK_CTRL (0x0654) -#define RTL931X_LED_PORT_FIB_MASK_CTRL (0x065c) -#define RTL931X_LED_PORT_COMBO_MASK_CTRL (0x0664) - -#define RTL931X_LED_GLB_ACTIVE_LOW BIT(21) - -#define RTL931X_LED_SETX_0_CTRL(x) (RTL931X_LED_SET0_0_CTRL - (x * 8)) -#define RTL931X_LED_SETX_1_CTRL(x) (RTL931X_LED_SETX_0_CTRL(x) - 4) - -/* get register for given set and led in the set */ -#define RTL931X_LED_SETX_LEDY(x, y) (RTL931X_LED_SETX_0_CTRL(x) - 4 * (y / 2)) - -/* get shift for given led in any set */ -#define RTL931X_LED_SET_LEDX_SHIFT(x) (16 * (x % 2)) - -#define MAX_LAGS 16 -#define MAX_PRIOS 8 -#define RTL930X_PORT_IGNORE 0x3f -/* ToDo: MAX_MC_GROUPS could be increased - * 838x/839x/930x/931x -> 8192/16384/16384/32768 entries (priv->fib_entries) - * They are shared with unicast entries - */ -#define MAX_MC_GROUPS 512 -/* ToDo: MAX_MC_PMASKS could be increased - * 838x/839x/930x/931x -> 512/4096/1024/4096 entries - */ -#define MAX_MC_PMASKS 512 -#define RTL838X_MC_PMASK_ALL_PORTS (GENMASK(RTL838X_CPU_PORT, 0)) -#define RTL839X_MC_PMASK_ALL_PORTS (GENMASK_ULL(RTL839X_CPU_PORT, 0)) -#define RTL930X_MC_PMASK_ALL_PORTS (GENMASK(RTL930X_CPU_PORT, 0)) -#define RTL931X_MC_PMASK_ALL_PORTS (GENMASK_ULL(RTL931X_CPU_PORT, 0)) -#define MC_PMASK_ALL_PORTS_IDX ((MAX_MC_PMASKS - 1)) -#define PIE_BLOCK_SIZE 128 -#define MAX_PIE_ENTRIES (18 * PIE_BLOCK_SIZE) -#define N_FIXED_FIELDS 12 -#define N_FIXED_FIELDS_RTL931X 14 -#define MAX_COUNTERS 2048 -#define MAX_INTF_MTUS 8 -#define DEFAULT_MTU 1536 -#define MAX_ROUTER_MACS 64 -#define L3_EGRESS_DMACS 2048 -#define MAX_SMACS 64 -#define DSCP_MAP_MAX 64 - struct rtldsa_93xx_lag_entry { u32 trk_port0:6; u32 trk_dev0:4; @@ -875,8 +113,6 @@ struct rtldsa_l2_uc { u8 l3_refcount:7; /* routes forwarding through it */ }; -#define RTLDSA_L2_L3_REFCOUNT_MAX 0x7f - struct rtl838x_l2_entry { u8 mac[6]; u16 vid; diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c index 26bc73e61a1..0cf748130b3 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c @@ -11,11 +11,67 @@ #include "pie.h" #include "qos.h" #include "mirror.h" +#include "mac.h" #include "rtl-otto.h" #include "stats.h" #include "vlan.h" #include "stp.h" +/* Register definition */ +#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7))) + +/* MAC maximum packet length (jumbo frame) control. + * + * The switch MAC drops frames whose L2 length exceeds the configured maximum. + * A family holds either one register per user port or a single one for the + * whole switch. The length is a direct byte value held in two 14-bit fields + * (high-speed links in [13:0], 10/100M links in [27:14]); bit 28 selects + * whether VLAN tag bytes count towards the limit. + */ + +/* RTL838x and RTL839x hold one limit for the whole switch instead, bounding + * the CPU port with it. RTL838x mirrors it in a second register, and the + * vendor SDK writes both (dal_maple_switch_maxPktLenLinkSpeed_set()). + */ +#define RTL838X_MAC_MAX_LEN_CTRL (0xa9e0) +#define RTL838X_MAC_MAX_LEN_CTRL_DUP (0x6b00) + +/* RTL838x stops at what its datasheet gives, below the vendor SDK value */ +#define RTL838X_MAX_FRAME 10000 + +/* MAC handling */ +#define RTL838X_MAC_LINK_STS (0xa188) + +#define RTL838X_EEE_PORT_TX_EN (0x014c) +#define RTL838X_EEE_PORT_RX_EN (0x0150) +#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) +#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) + +/* L2 functionality */ +#define RTL838X_L2_CTRL_0 (0x3200) + +#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) + +/* 802.1X */ +#define RTL838X_RMA_BPDU_FLD_PMSK (0x4348) + +#define RTL838X_SPCL_TRAP_EAPOL_CTRL (0x6988) +#define RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL (0x6998) + +/* Switch interrupts */ +#define RTL838X_IMR_GLB (0x1100) +#define RTL838X_IMR_PORT_LINK_STS_CHG (0x1104) +#define RTL838X_ISR_GLB_SRC (0x1148) +#define RTL838X_ISR_PORT_LINK_STS_CHG (0x114C) + +#define RTL838X_SMI_GLB_CTRL (0xa100) /* used by RTL838x EEE setup */ + +#define RTL838X_RMA_BPDU_CTRL (0x4330) + +#define RTL838X_RMA_PTP_CTRL (0x4338) + +#define RTL838X_RMA_LLDP_CTRL (0x4340) + void rtldsa_838x_print_matrix(void) { unsigned volatile int *ptr8; diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c index b41db97571f..c12ccdf4596 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c @@ -9,11 +9,60 @@ #include "pie.h" #include "qos.h" #include "mirror.h" +#include "mac.h" #include "rtl-otto.h" #include "stats.h" #include "vlan.h" #include "stp.h" +#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7))) + +/* MAC maximum packet length (jumbo frame) control. + * + * The switch MAC drops frames whose L2 length exceeds the configured maximum. + * A family holds either one register per user port or a single one for the + * whole switch. The length is a direct byte value held in two 14-bit fields + * (high-speed links in [13:0], 10/100M links in [27:14]); bit 28 selects + * whether VLAN tag bytes count towards the limit. + */ + +#define RTL839X_MAC_MAX_LEN_CTRL (0x02b0) + +#define RTL839X_MAX_FRAME 12288 + +#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) + +#define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3)) + +#define RTL839X_TBL_ACCESS_CTRL_2 (0x611C) + +#define RTL839X_MAC_LINK_STS (0x0390) + +#define RTL839X_EEE_TX_TIMER_GELITE_CTRL (0x042C) +#define RTL839X_EEE_TX_TIMER_GIGA_CTRL (0x0430) +#define RTL839X_EEE_TX_TIMER_10G_CTRL (0x0434) +#define RTL839X_EEE_CTRL(p) (0x8008 + ((p) << 7)) + +#define RTL839X_L2_CTRL_0 (0x3800) + +#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) + +#define RTL839X_RMA_BPDU_FLD_PMSK (0x125C) + +#define RTL839X_SPCL_TRAP_EAPOL_CTRL (0x105C) +#define RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL (0x1068) + +#define RTL839X_IMR_GLB (0x0064) +#define RTL839X_IMR_PORT_LINK_STS_CHG (0x0068) +#define RTL839X_ISR_GLB_SRC (0x009c) +#define RTL839X_ISR_PORT_LINK_STS_CHG (0x00a0) + +#define RTL839X_RMA_BPDU_CTRL (0x122C) + +#define RTL839X_RMA_PTP_CTRL (0x123C) + +#define RTL839X_RMA_LLDP_CTRL (0x124C) + void rtldsa_839x_print_matrix(void) { volatile u64 *ptr9; diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c index fc3321e42dc..2bef01c5bd5 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c @@ -10,12 +10,70 @@ #include "pie.h" #include "qos.h" #include "mirror.h" +#include "mac.h" #include "rtl-otto.h" #include "stats.h" #include "tc.h" #include "vlan.h" #include "stp.h" +#define RTL930X_MAC_L2_PORT_CTRL(port) (0x3268 + (((port) << 6))) + +/* MAC maximum packet length (jumbo frame) control. + * + * The switch MAC drops frames whose L2 length exceeds the configured maximum. + * A family holds either one register per user port or a single one for the + * whole switch. The length is a direct byte value held in two 14-bit fields + * (high-speed links in [13:0], 10/100M links in [27:14]); bit 28 selects + * whether VLAN tag bytes count towards the limit. + */ + +/* RTL930x holds one register per user port, inside the 64-byte MAC block of + * the port. The CPU port has a row of its own, which the ethernet driver owns + * and programs from the conduit MTU. Register offsets taken from the + * reverse-engineered Realtek register maps at https://svanheule.net/realtek/ + */ +#define RTL930X_MAC_L2_PORT_MAX_LEN_CTRL(port) (0x326C + (((port) << 6))) + +/* Largest frame each family switches; the length field would allow 16383 */ +#define RTL930X_MAX_FRAME 12288 + +#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C) + +#define RTL930X_MAC_LINK_STS (0xCB10) + +#define RTL930X_EEE_CTRL(p) (0x3274 + ((p) << 6)) + +#define RTL930X_TRK_HASH_CTRL (0x9F80) +#define RTL930X_TRK_CTRL (0x9F88) + +#define RTL930X_RMA_BPDU_FLD_PMSK (0x9F18) + +#define RTL930X_IMR_GLB (0xC628) +#define RTL930X_IMR_PORT_LINK_STS_CHG (0xC62C) +#define RTL930X_ISR_GLB (0xC658) +#define RTL930X_ISR_PORT_LINK_STS_CHG (0xC660) + +#define RTL930X_LED_GLB_CTRL (0xCC00) + +#define RTL930X_RMA_BPDU_CTRL (0x9E7C) + +#define RTL930X_RMA_PTP_CTRL (0x9E88) + +#define RTL930X_RMA_LLDP_CTRL (0x9EFC) + +#define RTL930X_RMA_EAPOL_CTRL (0x9F08) +#define RTL930X_SPCL_TRAP_PORT_CTRL (0xA1A0) + +/* Port LED Control */ +#define RTL930X_LED_PORT_NUM_CTRL(p) (0xCC04 + (((p >> 4) << 2))) +#define RTL930X_LED_SET0_0_CTRL (0xCC28) +#define RTL930X_LED_PORT_COPR_SET_SEL_CTRL(p) (0xCC2C + (((p >> 4) << 2))) +#define RTL930X_LED_PORT_FIB_SET_SEL_CTRL(p) (0xCC34 + (((p >> 4) << 2))) +#define RTL930X_LED_PORT_COPR_MASK_CTRL (0xCC3C) +#define RTL930X_LED_PORT_FIB_MASK_CTRL (0xCC40) +#define RTL930X_LED_PORT_COMBO_MASK_CTRL (0xCC44) + #define RTL930X_LED_GLB_ACTIVE_LOW BIT(22) #define RTL930X_LED_CLK_SEL_MASK GENMASK(17, 16) #define RTL930X_LED_CLK_SEL_800NS 0 diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c index 803ae38f5e4..287f0a86a99 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c @@ -14,6 +14,71 @@ #include "vlan.h" #include "stp.h" +#define RTL931X_MAC_L2_PORT_CTRL (0x6000) + +/* MAC maximum packet length (jumbo frame) control. + * + * The switch MAC drops frames whose L2 length exceeds the configured maximum. + * A family holds either one register per user port or a single one for the + * whole switch. The length is a direct byte value held in two 14-bit fields + * (high-speed links in [13:0], 10/100M links in [27:14]); bit 28 selects + * whether VLAN tag bytes count towards the limit. + */ + +/* RTL931x covers ports 0 to 55 only, one word each. The CPU port has no row: + * the word that would follow the array is MAC_DBG_SEL_CTRL. + */ +#define RTL931X_MAC_L2_PORT_MAX_LEN_CTRL (0x5554) + +#define RTL931X_MAX_FRAME 12288 + +#define RTL931X_MAC_FORCE_MODE_CTRL (0x0DCC) + +#define RTL931X_MAC_LINK_STS (0x0EC0) + +#define RTL931X_FORCE_EN BIT(9) +#define RTL931X_FORCE_LINK_EN BIT(0) + +#define RTL931X_TRK_HASH_CTRL (0xBA70) +#define RTL931X_TRK_CTRL (0xBA78) + +#define RTL931X_RMA_BPDU_FLD_PMSK (0x8950) + +/* IMR_GLB does not exit on RTL931X */ +#define RTL931X_IMR_PORT_LINK_STS_CHG (0x126C) +#define RTL931X_ISR_GLB_SRC (0x12B4) +#define RTL931X_ISR_PORT_LINK_STS_CHG (0x12B8) + +#define RTL931X_LED_GLB_CTRL (0x0600) + +#define RTL931X_RMA_BPDU_CTRL (0x881C) + +#define RTL931X_RMA_PTP_CTRL (0x8834) + +#define RTL931X_RMA_LLDP_CTRL (0x8918) + +#define RTL931X_RMA_EAPOL_CTRL (0x8930) +#define RTL931X_TRAP_ARP_GRAT_PORT_ACT (0x8C04) + +#define RTL931X_LED_PORT_NUM_CTRL(p) (0x0604 + (((p >> 4) << 2))) +#define RTL931X_LED_SET0_0_CTRL (0x0630) +#define RTL931X_LED_PORT_COPR_SET_SEL_CTRL(p) (0x0634 + (((p >> 4) << 2))) +#define RTL931X_LED_PORT_FIB_SET_SEL_CTRL(p) (0x0644 + (((p >> 4) << 2))) +#define RTL931X_LED_PORT_COPR_MASK_CTRL (0x0654) +#define RTL931X_LED_PORT_FIB_MASK_CTRL (0x065c) +#define RTL931X_LED_PORT_COMBO_MASK_CTRL (0x0664) + +#define RTL931X_LED_GLB_ACTIVE_LOW BIT(21) + +#define RTL931X_LED_SETX_0_CTRL(x) (RTL931X_LED_SET0_0_CTRL - (x * 8)) +#define RTL931X_LED_SETX_1_CTRL(x) (RTL931X_LED_SETX_0_CTRL(x) - 4) + +/* get register for given set and led in the set */ +#define RTL931X_LED_SETX_LEDY(x, y) (RTL931X_LED_SETX_0_CTRL(x) - 4 * (y / 2)) + +/* get shift for given led in any set */ +#define RTL931X_LED_SET_LEDX_SHIFT(x) (16 * (x % 2)) + #define RTL931X_LED_CLK_SEL_MASK GENMASK(16, 15) #define RTL931X_LED_CLK_SEL_800NS 0 #define RTL931X_LED_CLK_SEL_400NS 1 diff --git a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c index 9f8a39a749a..614aef3f744 100644 --- a/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c +++ b/target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c @@ -9,6 +9,7 @@ #include #include +#include "pie.h" #include "rtl-otto.h" #include "tc.h"