From 5df1a6ab80ab81ce8cbc41baba977dbf1960f7eb Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 16 Sep 2026 18:23:29 +0200 Subject: [PATCH] qualcommax: ipq60xx: pass UNIPHY clocks directly to GCC Passing UNIPHY clocks as DT references directly to GCC allows us to drop the old global name hack we needed for SSDK. Signed-off-by: Robert Marko --- .../arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi | 2 + ...com-ipq6018-add-uniphy-clocks-to-gcc.patch | 44 +++++++ ...-workaround-networking-clock-parenti.patch | 109 ------------------ ...arm64-dts-qcom-ipq6018-add-wifi-node.patch | 2 +- ...07-soc-qcom-fix-smp2p-ack-on-ipq6018.patch | 2 +- ...pq6018-assign-QDSS_AT-clock-to-wifi-.patch | 2 +- 6 files changed, 49 insertions(+), 112 deletions(-) create mode 100644 target/linux/qualcommax/patches-6.18/0145-arm64-dts-qcom-ipq6018-add-uniphy-clocks-to-gcc.patch delete mode 100644 target/linux/qualcommax/patches-6.18/0904-clk-qcom-ipq6018-workaround-networking-clock-parenti.patch diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi index 0de37caf7da..b590004f983 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi @@ -44,6 +44,7 @@ "port5_rx", "port5_tx"; clock-output-names = "uniphy0_gcc_tx_clk", "uniphy0_gcc_rx_clk"; + #clock-cells = <1>; resets = <&gcc GCC_UNIPHY0_SOFT_RESET>, <&gcc GCC_UNIPHY0_XPCS_RESET>, <&gcc GCC_UNIPHY0_PORT1_ARES>, @@ -69,6 +70,7 @@ "port5_rx", "port5_tx"; clock-output-names = "uniphy1_gcc_tx_clk", "uniphy1_gcc_rx_clk"; + #clock-cells = <1>; resets = <&gcc GCC_UNIPHY1_SOFT_RESET>, <&gcc GCC_UNIPHY1_XPCS_RESET>; reset-names = "soft", "xpcs"; diff --git a/target/linux/qualcommax/patches-6.18/0145-arm64-dts-qcom-ipq6018-add-uniphy-clocks-to-gcc.patch b/target/linux/qualcommax/patches-6.18/0145-arm64-dts-qcom-ipq6018-add-uniphy-clocks-to-gcc.patch new file mode 100644 index 00000000000..eab2ee36e27 --- /dev/null +++ b/target/linux/qualcommax/patches-6.18/0145-arm64-dts-qcom-ipq6018-add-uniphy-clocks-to-gcc.patch @@ -0,0 +1,44 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 16 Sep 2026 18:07:28 +0200 +Subject: [PATCH] arm64: dts: qcom: ipq6018: add UNIPHY clocks to GCC + +Add the UNIPHY RX and TX clocks as inputs of GCC so its RCGs can use +them as their clock parents. + +Signed-off-by: Robert Marko +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 +++++++++++++-- + 1 file changed, 13 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + / { + #address-cells = <2>; +@@ -401,8 +402,18 @@ + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-ipq6018"; + reg = <0x0 0x01800000 0x0 0x80000>; +- clocks = <&xo>, <&sleep_clk>; +- clock-names = "xo", "sleep_clk"; ++ clocks = <&xo>, ++ <&sleep_clk>, ++ <&uniphy0 UNIPHY_CLK_RX>, ++ <&uniphy0 UNIPHY_CLK_TX>, ++ <&uniphy1 UNIPHY_CLK_RX>, ++ <&uniphy1 UNIPHY_CLK_TX>; ++ clock-names = "xo", ++ "sleep_clk", ++ "uniphy0_gcc_rx_clk", ++ "uniphy0_gcc_tx_clk", ++ "uniphy1_gcc_rx_clk", ++ "uniphy1_gcc_tx_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/target/linux/qualcommax/patches-6.18/0904-clk-qcom-ipq6018-workaround-networking-clock-parenti.patch b/target/linux/qualcommax/patches-6.18/0904-clk-qcom-ipq6018-workaround-networking-clock-parenti.patch deleted file mode 100644 index 30c6eced96c..00000000000 --- a/target/linux/qualcommax/patches-6.18/0904-clk-qcom-ipq6018-workaround-networking-clock-parenti.patch +++ /dev/null @@ -1,109 +0,0 @@ -From 0c5b5243ad55ae744e790ba90c5ad37a93bd1377 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 11 Oct 2022 23:38:45 +0200 -Subject: [PATCH] clk: qcom: ipq6018: workaround networking clock parenting - -Currently, networking clocks are only looked up by fw_name however, -these are registered and setup by SSDK and are not available to the -GCC driver at all, so work around that by providing a global name -fallback. - -While we are here, provide global fallback for bias_pll_cc_clk and -bias_pll_nss_noc_clk as well as these are fixed clocks also not available -to the driver. - -Signed-off-by: Robert Marko ---- - drivers/clk/qcom/gcc-ipq6018.c | 39 +++++++++++++++++----------------- - 1 file changed, 19 insertions(+), 20 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq6018.c -+++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -360,7 +360,7 @@ static const struct freq_tbl ftbl_nss_pp - - static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = { - { .fw_name = "xo" }, -- { .fw_name = "bias_pll_cc_clk" }, -+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll4.clkr.hw }, - { .hw = &nss_crypto_pll.clkr.hw }, -@@ -534,12 +534,12 @@ static const struct freq_multi_tbl ftbl_ - static const struct clk_parent_data - gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = { - { .fw_name = "xo" }, -- { .fw_name = "uniphy0_gcc_rx_clk" }, -- { .fw_name = "uniphy0_gcc_tx_clk" }, -- { .fw_name = "uniphy1_gcc_rx_clk" }, -- { .fw_name = "uniphy1_gcc_tx_clk" }, -+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, -+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, -+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" }, -+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" }, - { .hw = &ubi32_pll.clkr.hw }, -- { .fw_name = "bias_pll_cc_clk" }, -+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, - }; - - static const struct parent_map -@@ -589,12 +589,12 @@ static const struct freq_multi_tbl ftbl_ - static const struct clk_parent_data - gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = { - { .fw_name = "xo" }, -- { .fw_name = "uniphy0_gcc_tx_clk" }, -- { .fw_name = "uniphy0_gcc_rx_clk" }, -- { .fw_name = "uniphy1_gcc_tx_clk" }, -- { .fw_name = "uniphy1_gcc_rx_clk" }, -+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, -+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, -+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" }, -+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" }, - { .hw = &ubi32_pll.clkr.hw }, -- { .fw_name = "bias_pll_cc_clk" }, -+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, - }; - - static const struct parent_map -@@ -730,10 +730,10 @@ static const struct freq_tbl ftbl_nss_po - - static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = { - { .fw_name = "xo" }, -- { .fw_name = "uniphy0_gcc_rx_clk" }, -- { .fw_name = "uniphy0_gcc_tx_clk" }, -+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, -+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, - { .hw = &ubi32_pll.clkr.hw }, -- { .fw_name = "bias_pll_cc_clk" }, -+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, - }; - - static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = { -@@ -766,10 +766,10 @@ static const struct freq_tbl ftbl_nss_po - - static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = { - { .fw_name = "xo" }, -- { .fw_name = "uniphy0_gcc_tx_clk" }, -- { .fw_name = "uniphy0_gcc_rx_clk" }, -+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" }, -+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" }, - { .hw = &ubi32_pll.clkr.hw }, -- { .fw_name = "bias_pll_cc_clk" }, -+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" }, - }; - - static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = { -@@ -1915,12 +1915,11 @@ static const struct freq_tbl ftbl_ubi32_ - { } - }; - --static const struct clk_parent_data -- gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = { -+static const struct clk_parent_data gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = { - { .fw_name = "xo" }, - { .hw = &gpll0.clkr.hw }, - { .hw = &gpll2.clkr.hw }, -- { .fw_name = "bias_pll_nss_noc_clk" }, -+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" }, - }; - - static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = { diff --git a/target/linux/qualcommax/patches-6.18/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch b/target/linux/qualcommax/patches-6.18/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch index 7f924e18494..08466331298 100644 --- a/target/linux/qualcommax/patches-6.18/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch +++ b/target/linux/qualcommax/patches-6.18/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch @@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -817,6 +817,102 @@ +@@ -828,6 +828,102 @@ }; }; diff --git a/target/linux/qualcommax/patches-6.18/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch b/target/linux/qualcommax/patches-6.18/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch index 1882139180b..ae28c4cb927 100644 --- a/target/linux/qualcommax/patches-6.18/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch +++ b/target/linux/qualcommax/patches-6.18/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch @@ -15,7 +15,7 @@ Signed-off-by: Mantas Pucka --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -1185,6 +1185,7 @@ +@@ -1196,6 +1196,7 @@ wcss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; diff --git a/target/linux/qualcommax/patches-6.18/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch b/target/linux/qualcommax/patches-6.18/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch index d588c05c186..ed6cbd164e0 100644 --- a/target/linux/qualcommax/patches-6.18/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch +++ b/target/linux/qualcommax/patches-6.18/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch @@ -13,7 +13,7 @@ Signed-off-by: Mantas Pucka --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -938,8 +938,8 @@ +@@ -949,8 +949,8 @@ "wcss_reset", "wcss_q6_reset";