From aa773443ce6dd5fbb4c7a8d014f6e3819d7a7369 Mon Sep 17 00:00:00 2001 From: Joseph Chen Date: Sun, 4 Oct 2026 08:46:32 +0800 Subject: [PATCH] sunxi: enable H3 R-PIO support for H5 boards The Allwinner H5 uses the H3 R-PIO controller in addition to its H5-specific main PIO controller. Moving the pinctrl configuration to the subtargets left PINCTRL_SUN8I_H3_R disabled for cortexa53. On the NanoPi NEO 2, usb0-vbus depends on the R-PIO PL2 GPIO. Without the driver, the regulator and USB PHY remain deferred, preventing the USB host controllers from probing. No USB device nodes are created and lsusb reports "unable to initialize libusb: -99". Enable PINCTRL_SUN8I_H3_R in the cortexa53 configuration to restore the R-PIO driver required by H5 boards. Fixes: 920fa6f06103 ("sunxi: enable pinctrl driver in subtarget") Signed-off-by: Joseph Chen Link: https://github.com/openwrt/openwrt/pull/25588 Signed-off-by: Hauke Mehrtens --- target/linux/sunxi/cortexa53/config-6.18 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/sunxi/cortexa53/config-6.18 b/target/linux/sunxi/cortexa53/config-6.18 index 65ee51de311..b90dd5adf75 100644 --- a/target/linux/sunxi/cortexa53/config-6.18 +++ b/target/linux/sunxi/cortexa53/config-6.18 @@ -95,6 +95,7 @@ CONFIG_PINCTRL_SUN50I_H6=y CONFIG_PINCTRL_SUN50I_H616=y CONFIG_PINCTRL_SUN50I_H616_R=y CONFIG_PINCTRL_SUN50I_H6_R=y +CONFIG_PINCTRL_SUN8I_H3_R=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y