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qualcommax: add EDMA driver
EDMA dataplane ethernet driver for Qualcomm IPQ platforms. Signed-off-by: John Crispin <john@phrozen.org> [ rework Makefile for external repository, dependency ] Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> [ rework for in-tree ] Link: https://github.com/openwrt/openwrt/pull/22381 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
John Crispin authored and 
Robert Marko committed
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@@ -415,6 +415,7 @@ CONFIG_QCOM_BAM_DMA=y
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# CONFIG_QCOM_CPR is not set
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# CONFIG_QCOM_CPUCP_MBOX is not set
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# CONFIG_QCOM_EBI2 is not set
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# CONFIG_QCOM_EDMA is not set
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# CONFIG_QCOM_FASTRPC is not set
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# CONFIG_QCOM_GENI_SE is not set
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# CONFIG_QCOM_GSBI is not set
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File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,259 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016, 2018-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef __QCA_EDMA_H__
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#define __QCA_EDMA_H__
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#include <linux/dsa/oob.h>
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#include <linux/etherdevice.h>
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#include <linux/netdevice.h>
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#include <linux/platform_device.h>
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#include <net/page_pool/helpers.h>
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#define EDMA_HW_RESET_ID "edma_rst"
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/* Global / control registers */
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#define EDMA_REG_MAS_CTRL 0x0
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#define EDMA_REG_PORT_CTRL 0x4
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#define EDMA_REG_RXDESC2FILL_MAP_0 0x18
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#define EDMA_REG_RXDESC2FILL_MAP_1 0x1c
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#define EDMA_REG_DMAR_CTRL 0x48
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#define EDMA_REG_AXIW_CTRL 0x50
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#define EDMA_REG_MISC_INT_STAT 0x5c
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#define EDMA_REG_MISC_INT_MASK 0x60
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#define EDMA_PORT_PAD_EN 0x1
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#define EDMA_PORT_EDMA_EN 0x2
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#define EDMA_DMAR_REQ_PRI_MASK 0x7
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#define EDMA_DMAR_REQ_PRI_SHIFT 0
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#define EDMA_DMAR_BURST_LEN_MASK 0x1
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#define EDMA_DMAR_BURST_LEN_SHIFT 3
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#define EDMA_DMAR_TXDATA_NUM_MASK 0x1f
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#define EDMA_DMAR_TXDATA_NUM_SHIFT 4
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#define EDMA_DMAR_TXDESC_NUM_MASK 0x7
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#define EDMA_DMAR_TXDESC_NUM_SHIFT 9
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#define EDMA_DMAR_RXFILL_NUM_MASK 0x7
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#define EDMA_DMAR_RXFILL_NUM_SHIFT 12
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#define EDMA_DMAR_REQ_PRI_SET(x) \
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(((x)&EDMA_DMAR_REQ_PRI_MASK) << EDMA_DMAR_REQ_PRI_SHIFT)
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#define EDMA_DMAR_TXDATA_NUM_SET(x) \
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(((x)&EDMA_DMAR_TXDATA_NUM_MASK) << EDMA_DMAR_TXDATA_NUM_SHIFT)
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#define EDMA_DMAR_TXDESC_NUM_SET(x) \
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(((x)&EDMA_DMAR_TXDESC_NUM_MASK) << EDMA_DMAR_TXDESC_NUM_SHIFT)
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#define EDMA_DMAR_RXFILL_NUM_SET(x) \
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(((x)&EDMA_DMAR_RXFILL_NUM_MASK) << EDMA_DMAR_RXFILL_NUM_SHIFT)
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#define EDMA_DMAR_BURST_LEN_SET(x) \
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(((x)&EDMA_DMAR_BURST_LEN_MASK) << EDMA_DMAR_BURST_LEN_SHIFT)
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#define EDMA_AXIW_MAX_WR_SIZE_EN 0x400
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/* TX descriptor ring registers */
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#define EDMA_REG_TXDESC_BA(n) (0x1000 + (0x1000 * (n)))
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#define EDMA_REG_TXDESC_PROD_IDX(n) (0x1004 + (0x1000 * (n)))
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#define EDMA_REG_TXDESC_CONS_IDX(n) (0x1008 + (0x1000 * (n)))
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#define EDMA_REG_TXDESC_RING_SIZE(n) (0x100c + (0x1000 * (n)))
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#define EDMA_REG_TXDESC_CTRL(n) (0x1010 + (0x1000 * (n)))
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#define EDMA_TXDESC_PROD_IDX_MASK 0xffff
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#define EDMA_TXDESC_CONS_IDX_MASK 0xffff
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#define EDMA_TXDESC_RING_SIZE_MASK 0xffff
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#define EDMA_TXDESC_TX_EN 0x1
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/* TX completion ring registers */
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#define EDMA_REG_TXCMPL_BA(b, n) ((b) + (0x1000 * (n)))
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#define EDMA_REG_TXCMPL_PROD_IDX(b, n) ((b) + 0x004 + (0x1000 * (n)))
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#define EDMA_REG_TXCMPL_CONS_IDX(b, n) ((b) + 0x008 + (0x1000 * (n)))
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#define EDMA_REG_TXCMPL_RING_SIZE(b, n) ((b) + 0x00c + (0x1000 * (n)))
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#define EDMA_REG_TXCMPL_CTRL(b, n) ((b) + 0x014 + (0x1000 * (n)))
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#define EDMA_TXCMPL_PROD_IDX_MASK 0xffff
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#define EDMA_TXCMPL_CONS_IDX_MASK 0xffff
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#define EDMA_TXCMPL_RETMODE_OPAQUE 0x0
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/* TX interrupt registers */
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#define EDMA_REG_TX_INT_STAT(b, n) ((b) + (0x1000 * (n)))
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#define EDMA_REG_TX_INT_MASK(b, n) ((b) + 0x004 + (0x1000 * (n)))
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#define EDMA_REG_TX_MOD_TIMER(b, n) ((b) + 0x008 + (0x1000 * (n)))
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#define EDMA_REG_TX_INT_CTRL(b, n) ((b) + 0x00c + (0x1000 * (n)))
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#define EDMA_TX_INT_MASK 0x3
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#define EDMA_TX_MOD_TIMER 150
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/* RX fill ring registers */
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#define EDMA_REG_RXFILL_BA(n) (0x29000 + (0x1000 * (n)))
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#define EDMA_REG_RXFILL_PROD_IDX(n) (0x29004 + (0x1000 * (n)))
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#define EDMA_REG_RXFILL_CONS_IDX(n) (0x29008 + (0x1000 * (n)))
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#define EDMA_REG_RXFILL_RING_SIZE(n) (0x2900c + (0x1000 * (n)))
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#define EDMA_REG_RXFILL_RING_EN(n) (0x2901c + (0x1000 * (n)))
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#define EDMA_RXFILL_PROD_IDX_MASK 0xffff
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#define EDMA_RXFILL_CONS_IDX_MASK 0xffff
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#define EDMA_RXFILL_RING_SIZE_MASK 0xffff
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#define EDMA_RXFILL_BUF_SIZE_MASK 0x3fff
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#define EDMA_RXFILL_RING_EN 0x1
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#define EDMA_RXFILL_INT_MASK 0x1
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/* RX fill ring interrupt registers */
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#define EDMA_REG_RXFILL_INT_STAT(n) (0x31000 + (0x1000 * (n)))
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#define EDMA_REG_RXFILL_INT_MASK(n) (0x31004 + (0x1000 * (n)))
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/* RX descriptor ring registers */
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#define EDMA_REG_RXDESC_BA(n) (0x39000 + (0x1000 * (n)))
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#define EDMA_REG_RXDESC_PROD_IDX(n) (0x39004 + (0x1000 * (n)))
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#define EDMA_REG_RXDESC_CONS_IDX(n) (0x39008 + (0x1000 * (n)))
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#define EDMA_REG_RXDESC_RING_SIZE(n) (0x3900c + (0x1000 * (n)))
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#define EDMA_REG_RXDESC_CTRL(n) (0x39018 + (0x1000 * (n)))
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#define EDMA_RXDESC_PROD_IDX_MASK 0xffff
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#define EDMA_RXDESC_CONS_IDX_MASK 0xffff
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#define EDMA_RXDESC_RING_SIZE_MASK 0xffff
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#define EDMA_RXDESC_PL_OFFSET_MASK 0x1ff
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#define EDMA_RXDESC_PL_OFFSET_SHIFT 16
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#define EDMA_RXDESC_RX_EN 0x1
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#define EDMA_RXDESC_PACKET_LEN_MASK 0x3fff
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/* RX descriptor ring interrupt registers */
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#define EDMA_REG_RXDESC_INT_STAT(n) (0x49000 + (0x1000 * (n)))
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#define EDMA_REG_RXDESC_INT_MASK(n) (0x49004 + (0x1000 * (n)))
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#define EDMA_REG_RX_MOD_TIMER(n) (0x49008 + (0x1000 * (n)))
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#define EDMA_REG_RX_INT_CTRL(n) (0x4900c + (0x1000 * (n)))
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#define EDMA_RXDESC_INT_MASK_PKT_INT 0x1
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#define EDMA_RX_MOD_TIMER_INIT 1000
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/* QID to ring mapping */
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#define EDMA_QID2RID_TABLE_MEM(q) (0x5a000 + (0x4 * (q)))
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/* TXDESC to TXCMPL ring mapping */
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#define EDMA_REG_TXDESC2CMPL_MAP(n) (0x0c + 0x4 * (n))
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/* Misc error interrupt masks */
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#define EDMA_MISC_AXI_RD_ERR_MASK_EN 0x1
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#define EDMA_MISC_AXI_WR_ERR_MASK_EN 0x2
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#define EDMA_MISC_RX_DESC_FIFO_FULL_MASK_EN 0x4
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#define EDMA_MISC_RX_ERR_BUF_SIZE_MASK_EN 0x8
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#define EDMA_MISC_TX_SRAM_FULL_MASK_EN 0x10
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#define EDMA_MISC_TX_CMPL_BUF_FULL_MASK_EN 0x20
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#define EDMA_MISC_DATA_LEN_ERR_MASK_EN 0x40
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#define EDMA_MISC_TX_TIMEOUT_MASK_EN 0x80
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/* Sizes and ring configuration */
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#define EDMA_RX_BUFFER_SIZE 1984
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#define EDMA_RX_PREHDR_SIZE (sizeof(struct edma_rx_preheader))
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#define EDMA_TX_PREHDR_SIZE (sizeof(struct edma_tx_preheader))
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#define EDMA_TX_RING_SIZE 128
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#define EDMA_RX_RING_SIZE 2048
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#define EDMA_TX_RING_THRESH 16
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/* Descriptor accessors */
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#define EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
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#define EDMA_RXFILL_DESC(R, i) EDMA_GET_DESC(R, i, struct edma_rxfill_desc)
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#define EDMA_RXDESC_DESC(R, i) EDMA_GET_DESC(R, i, struct edma_rxdesc)
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#define EDMA_TXDESC_DESC(R, i) EDMA_GET_DESC(R, i, struct edma_txdesc)
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#define EDMA_TXCMPL_DESC(R, i) EDMA_GET_DESC(R, i, struct edma_txcmpl)
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/* TX descriptor fields */
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#define EDMA_TXDESC_PREHEADER_SHIFT 29
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#define EDMA_TXDESC_DATA_OFFSET_SHIFT 16
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#define EDMA_TXDESC_DATA_OFFSET_MASK 0xff
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#define EDMA_TXDESC_DATA_LENGTH_MASK 0xffff
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/* Preheader fields */
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#define EDMA_DST_PORT_TYPE 0x20
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#define EDMA_DST_PORT_ID_MASK 0x1f
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#define EDMA_SRC_PORT_MASK 0x0fff
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#define EDMA_PREHDR_DSTINFO_PORTID_IND 0x20
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#define EDMA_RXPH_SRC_INFO_TYPE_GET(rxph) (((rxph)->src_info >> 8) & 0xf0)
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struct edma_txdesc {
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u32 buffer_addr;
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u32 word1;
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};
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struct edma_txcmpl {
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u32 buffer_addr;
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u32 status;
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};
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struct edma_rxdesc {
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u32 buffer_addr;
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u32 status;
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};
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struct edma_rxfill_desc {
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u32 buffer_addr;
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u32 word1;
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};
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struct edma_tx_preheader {
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u32 opaque;
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u16 src_info;
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u16 dst_info;
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u32 tx_pre2;
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u32 tx_pre3;
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u32 tx_pre4;
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u32 tx_pre5;
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u32 tx_pre6;
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u32 tx_pre7;
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};
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struct edma_rx_preheader {
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u32 opaque;
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u16 src_info;
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u16 dst_info;
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u32 rx_pre2;
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u32 rx_pre3;
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u32 rx_pre4;
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u32 rx_pre5;
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u32 rx_pre6;
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u32 rx_pre7;
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};
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struct edma_soc_data {
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u32 txcmpl_base;
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u32 tx_int_base;
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u32 misc_int_mask;
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u8 txdesc_ring;
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u8 txcmpl_ring;
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u8 rxfill_ring;
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u8 rxdesc_ring;
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u8 tx_min_size;
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bool burst_enable;
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bool axiw_enable;
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};
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struct edma_ring {
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void *desc;
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dma_addr_t dma;
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u16 count;
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struct sk_buff **skb_store;
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};
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struct edma_priv {
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const struct edma_soc_data *soc;
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struct napi_struct tx_napi;
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struct napi_struct rx_napi;
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struct net_device *netdev;
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struct platform_device *pdev;
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struct regmap *regmap;
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struct reset_control *rst;
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struct page_pool *page_pool;
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struct edma_ring txdesc_ring;
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struct edma_ring txcmpl_ring;
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struct edma_ring rxfill_ring;
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struct edma_ring rxdesc_ring;
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spinlock_t tx_lock;
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int txcmpl_irq;
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int rxfill_irq;
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int rxdesc_irq;
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int misc_irq;
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};
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#endif /* __QCA_EDMA_H__ */
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@@ -0,0 +1,110 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/qualcomm,ipq-edma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm IPQ EDMA Ethernet Controller
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maintainers:
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- John Crispin <john@phrozen.org>
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description: |
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The Enhanced Direct Memory Access (EDMA) controller in Qualcomm IPQ6018 and
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IPQ8074 SoCs provides the dataplane for the PPE (Packet Processing Engine)
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switch. It registers a network device that serves as the DSA conduit
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interface. The EDMA handles packet DMA between the PPE hardware and the
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host CPU through dedicated TX/RX descriptor and completion rings.
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properties:
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compatible:
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enum:
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- qualcomm,ipq6018-edma
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- qualcomm,ipq8074-edma
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: TX completion interrupt
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- description: RX fill interrupt
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- description: RX descriptor interrupt
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- description: Miscellaneous interrupt
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clocks:
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items:
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- description: EDMA core clock
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- description: EDMA configuration clock
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- description: PPE core clock
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- description: PPE configuration clock
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- description: NSSNOC PPE clock
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- description: NSSNOC PPE configuration clock
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- description: NSS NOC clock
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- description: NSSNOC SNOC clock
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- description: NOC interconnect clock (SoC-specific)
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clock-names:
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items:
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- const: nss_edma_clk
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- const: nss_edma_cfg_clk
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- const: nss_ppe_clk
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- const: nss_ppe_cfg_clk
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- const: nssnoc_ppe_clk
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- const: nssnoc_ppe_cfg_clk
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- const: gcc_nss_noc_clk
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- const: gcc_nssnoc_snoc_clk
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- enum:
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- gcc_mem_noc_nss_axi_clk
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- gcc_snoc_nssnoc_clk
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: edma_rst
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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edma@3ab00000 {
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compatible = "qualcomm,ipq8074-edma";
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reg = <0x3ab00000 0xb0000>;
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interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_NSS_EDMA_CLK>,
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<&gcc GCC_NSS_EDMA_CFG_CLK>,
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<&gcc GCC_NSS_PPE_CLK>,
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<&gcc GCC_NSS_PPE_CFG_CLK>,
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<&gcc GCC_NSSNOC_PPE_CLK>,
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<&gcc GCC_NSSNOC_PPE_CFG_CLK>,
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<&gcc GCC_NSS_NOC_CLK>,
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<&gcc GCC_NSSNOC_SNOC_CLK>,
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<&gcc GCC_MEM_NOC_NSS_AXI_CLK>;
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clock-names = "nss_edma_clk", "nss_edma_cfg_clk",
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"nss_ppe_clk", "nss_ppe_cfg_clk",
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"nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
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"gcc_nss_noc_clk", "gcc_nssnoc_snoc_clk",
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"gcc_mem_noc_nss_axi_clk";
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resets = <&gcc GCC_EDMA_HW_RESET>;
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reset-names = "edma_rst";
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};
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@@ -0,0 +1,24 @@
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--- a/drivers/net/ethernet/qualcomm/Kconfig
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+++ b/drivers/net/ethernet/qualcomm/Kconfig
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@@ -67,6 +67,11 @@ config QCOM_80211AX_PPE
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help
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Driver for Qualcomm 802.11ax PPE (Packet Processing Engine) switches.
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+config QCOM_EDMA
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+ tristate "EDMA dataplane ethernet driver for Qualcomm IPQ platforms"
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+ help
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+ EDMA dataplane ethernet driver for Qualcomm IPQ platforms.
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+
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source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
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--- a/drivers/net/ethernet/qualcomm/Makefile
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+++ b/drivers/net/ethernet/qualcomm/Makefile
|
||||
@@ -10,6 +10,7 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
|
||||
qcauart-objs := qca_uart.o
|
||||
obj-$(CONFIG_QCOM_80211AX_PPE) += qca_ppe.o
|
||||
qca_ppe-objs := qca_ppe_main.o qca_ppe_vlan.o qca_ppe_scheduler.o
|
||||
+obj-$(CONFIG_QCOM_EDMA) += qca_edma.o
|
||||
|
||||
obj-y += emac/
|
||||
|
||||
Reference in new issue
Block a user