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realtek: add RTL8224 initialization to Realtek driver
Adds an initialization sequence for the RTL8224. It relies a lot on magic values, however it explicitely initializes the SerDes part of the chip. Signed-off-by: Damien Dejean <dam.dejean@gmail.com> Link: https://github.com/openwrt/openwrt/pull/22609 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Damien Dejean
committed by
Robert Marko
Robert Marko
parent
03002d456a
commit
c99a30668d
@@ -0,0 +1,203 @@
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--- a/drivers/net/phy/realtek/realtek_main.c
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+++ b/drivers/net/phy/realtek/realtek_main.c
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@@ -171,6 +171,41 @@
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#define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4)
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+#define RTL8224_VND1_SERDES_CMD 0x3f8
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+#define RTL8224_VND1_SERDES_READ 0x3fc
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+#define RTL8224_VND1_SERDES_WRITE 0x400
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+#define RTL8224_SDS_CMD_READ BIT(15)
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+#define RTL8224_SDS_CMD_WRITE (BIT(15) | BIT(14))
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+
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+#define RTL8224_VND1_SERDES_MODE 0x7b20
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+#define RTL8224_VND1_SERDES_MODE_MASK GENMASK(4, 0)
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+#define RTL8224_VND1_SERDES_MODE_OFF 0x1f
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+#define RTL8224_VND1_SERDES_MODE_USXGMII 0x0d
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+#define RTL8224_VND1_SERDES_SUBMODE_MASK GENMASK(14, 10)
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+#define RTL8224_VND1_SERDES_SUBMODE_10G_QXGMII (0x2 << 10)
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+
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+#define RTL8224_SDS_AM_PAGE 0x6
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+#define RTL8224_SDS_AM_PERIOD_REG 0x12
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+
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+#define RTL8224_SDS_AM_CFG0_REG 0x13
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+#define RTL8224_SDS_AM_CFG1_REG 0x14
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+#define RTL8224_SDS_AM_CFG2_REG 0x15
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+#define RTL8224_SDS_AM_CFG3_REG 0x16
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+#define RTL8224_SDS_AM_CFG4_REG 0x17
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+#define RTL8224_SDS_AM_CFG5_REG 0x18
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+
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+#define RTL8224_SDS_NWAY_PAGE 0x7
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+#define RTL8224_SDS_NWAY_OPCODE_REG 0x10
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+#define RTL8224_SDS_NWAY_OPCODE_MASK GENMASK(7, 0)
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+#define RTL8224_SDS_NWAY_AN_REG 0x11
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+#define RTL8224_SDS_NWAY_AN_EN_MASK GENMASK(3, 0)
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+
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+#define RTL8224_SDS_REG0_TX_PAGE 0x2e
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+#define RTL8224_SDS_REG0_TX_POST1_REG 0x6
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+#define RTL8224_SDS_REG0_TX_REG 0x7
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+#define RTL8224_SDS_REG0_TX_Z0_REG 0xb
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+
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+
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#define RTL8221B_PHYCR1 0xa430
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#define RTL8221B_PHYCR1_ALDPS_EN BIT(2)
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#define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12)
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@@ -2034,6 +2069,147 @@ exit:
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return ret;
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}
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+static int rtl8224_sds_read(struct phy_device *phydev, int page, u32 reg)
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+{
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+ int ret;
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+ u32 val;
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+ u32 cmd = RTL8224_SDS_CMD_READ | (reg << 7) | (page << 1);
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+
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+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_CMD, cmd);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
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+ RTL8224_VND1_SERDES_CMD, val,
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+ !(val & BIT(15)), 500, 500000000,
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+ false);
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+ if (ret < 0)
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+ return ret;
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+
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+ return phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_READ);
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+}
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+
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+static int rtl8224_sds_write(struct phy_device *phydev, int page, int reg, u32 data)
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+{
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+ int ret;
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+ u32 tmp;
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+ u32 cmd = RTL8224_SDS_CMD_WRITE | (reg << 7) | (page << 1);
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+
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+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_WRITE,
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+ data);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_CMD, cmd);
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+ if (ret < 0)
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+ return ret;
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+
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+ return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
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+ RTL8224_VND1_SERDES_CMD, tmp,
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+ !(tmp & BIT(15)), 500, 500000000,
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+ false);
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+}
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+
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+static int rtl8224_sds_modify(struct phy_device *phydev, int page, int reg, u32 mask, u32 data)
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+{
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+ int ret;
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+ u32 val;
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+
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+ ret = rtl8224_sds_read(phydev, page, reg);
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+ if (ret < 0)
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+ return ret;
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+
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+ val = (u32)ret;
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+ val = (val & ~mask) | (data & mask);
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+
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+ ret = rtl8224_sds_write(phydev, page, reg, val);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int rtl8224_serdes_config(struct phy_device *phydev)
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+{
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+ if ((phydev->mdio.addr & 3) != 0)
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+ return 0;
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+
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+ /* Turn SerDes OFF */
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+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_MODE,
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+ RTL8224_VND1_SERDES_MODE_MASK,
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+ RTL8224_VND1_SERDES_MODE_OFF);
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+
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+ /* Use generic/standard-compliant AN mode */
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+ rtl8224_sds_modify(phydev, RTL8224_SDS_NWAY_PAGE,
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+ RTL8224_SDS_NWAY_OPCODE_REG,
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+ RTL8224_SDS_NWAY_OPCODE_MASK, 0x0003);
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+
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+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
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+ RTL8224_SDS_AM_PERIOD_REG, 0x00a4);
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+
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+ /* Set all AM markers to 0 */
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+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
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+ RTL8224_SDS_AM_CFG0_REG, 0);
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+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
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+ RTL8224_SDS_AM_CFG1_REG, 0);
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+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
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+ RTL8224_SDS_AM_CFG2_REG, 0);
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+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
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+ RTL8224_SDS_AM_CFG3_REG, 0);
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+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
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+ RTL8224_SDS_AM_CFG4_REG, 0);
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+ rtl8224_sds_write(phydev, RTL8224_SDS_AM_PAGE,
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+ RTL8224_SDS_AM_CFG5_REG, 0);
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+
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+ /* Enable USXGMII autoneg on all 4 channels */
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+ rtl8224_sds_modify(phydev, RTL8224_SDS_NWAY_PAGE,
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+ RTL8224_SDS_NWAY_AN_REG,
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+ RTL8224_SDS_NWAY_AN_EN_MASK, 0xf);
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+
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+ rtl8224_sds_modify(phydev, 0x06, 0x03, BIT(15), BIT(15));
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+ rtl8224_sds_modify(phydev, 0x06, 0x1d, BIT(9), BIT(9));
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+ rtl8224_sds_modify(phydev, 0x06, 0x1f, BIT(13), BIT(13));
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+ rtl8224_sds_write(phydev, 0x21, 0x10, 0x4480);
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+ rtl8224_sds_write(phydev, 0x21, 0x13, 0x0400);
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+ rtl8224_sds_write(phydev, 0x21, 0x18, 0x6d02);
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+ rtl8224_sds_write(phydev, 0x21, 0x1b, 0x424e);
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+ rtl8224_sds_write(phydev, 0x21, 0x1d, 0x0002);
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+ rtl8224_sds_write(phydev, 0x36, 0x1c, 0x1390);
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+ rtl8224_sds_write(phydev, 0x2e, 0x04, 0x0080);
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+
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+ rtl8224_sds_write(phydev, RTL8224_SDS_REG0_TX_PAGE,
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+ RTL8224_SDS_REG0_TX_POST1_REG, 0x0408);
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+
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+ rtl8224_sds_write(phydev, RTL8224_SDS_REG0_TX_PAGE,
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+ RTL8224_SDS_REG0_TX_REG, 0x020d);
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+
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+ rtl8224_sds_write(phydev, 0x2e, 0x09, 0x0601);
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+
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+ rtl8224_sds_write(phydev, RTL8224_SDS_REG0_TX_PAGE,
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+ RTL8224_SDS_REG0_TX_Z0_REG, 0x222c);
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+
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+ rtl8224_sds_write(phydev, 0x2e, 0x0c, 0xa217);
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+ rtl8224_sds_write(phydev, 0x2e, 0x0d, 0xfe40);
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+ rtl8224_sds_write(phydev, 0x2e, 0x15, 0xf5f1);
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+ rtl8224_sds_write(phydev, 0x2e, 0x16, 0x0443);
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+ rtl8224_sds_write(phydev, 0x2e, 0x1d, 0xabb0);
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+
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+ /* Turn SerDes ON in 10G_QXGMII mode */
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+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_MODE,
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+ RTL8224_VND1_SERDES_SUBMODE_MASK,
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+ RTL8224_VND1_SERDES_SUBMODE_10G_QXGMII);
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+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8224_VND1_SERDES_MODE,
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+ RTL8224_VND1_SERDES_MODE_MASK,
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+ RTL8224_VND1_SERDES_MODE_USXGMII);
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+
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+ rtl8224_sds_modify(phydev, 0x20, 0x00, GENMASK(5, 4), 0x30);
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+ rtl8224_sds_modify(phydev, 0x20, 0x00, GENMASK(5, 4), 0x10);
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+ rtl8224_sds_modify(phydev, 0x20, 0x00, GENMASK(5, 4), 0x30);
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+ rtl8224_sds_modify(phydev, 0x20, 0x00, GENMASK(5, 4), 0x00);
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+
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+ return 0;
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+}
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+
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static int rtl8224_mdi_config_order(struct phy_device *phydev)
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{
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struct device_node *np = phydev->mdio.dev.of_node;
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@@ -2088,6 +2264,10 @@ static int rtl8224_config_init(struct ph
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{
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int ret;
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+ ret = rtl8224_serdes_config(phydev);
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+ if (ret)
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+ return ret;
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+
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ret = rtl8224_mdi_config_order(phydev);
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if (ret)
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return ret;
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