The factory image of the Dongwon DW02-412H sometimes carries a broken
header CRC, as seen by the rebuilder:
-Header CRC: 0X990A0000
+Header CRC: 0X990A9FB7
The CRC is written with printf piped into dd bs=4 count=1. Bash's printf
writes its output line buffered, so a CRC holding a 0x0a byte is written
in two parts:
write(1, "\231\n", 2) = 2
write(1, "\237\267", 2) = 2
If dd reads the pipe between the two writes, it gets a short block, and
with count=1 it stops there and leaves the rest of the CRC zero. This
depends on the scheduling, so busy builders hit it while idle machines
almost never do. Delaying the writes reproduces it every time:
old: CRC be f8 0a 00
new: CRC be f8 0a 17
Put the header together by concatenation instead, so the image no longer
goes through dd. Without the race, the output is the same as before
(300 random kernels, all identical and with valid CRCs).
Link: https://github.com/openwrt/openwrt/pull/25867
Signed-off-by: Paul Spooren <mail@aparcar.org>
The wdr4300.dtsi USB port feeds a 4-port GL850G hub, so the LED trigger
sources are its four downstream ports. Override usb0 to drop the generic
trigger node and declare the hub with its device ID, mirroring the NEC
aterm boards.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25340
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Pi-WiFi4 USB port feeds a 4-port GL850G hub, so the LED trigger
sources are its four downstream ports. Override usb0 to drop the generic
trigger node and declare the hub with its device ID, mirroring the NEC
aterm boards.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25340
Signed-off-by: Robert Marko <robimarko@gmail.com>
The &usb override re-declares hub_port/@address-cells/#size-cells with
values identical to the ones inherited from ar934x.dtsi, so it has no
effect. Drop it and leave only the status change.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25340
Signed-off-by: Robert Marko <robimarko@gmail.com>
The internal PHYs of the QCA8327/8334/8337 switches are handled by the
qca83xx PHY driver. Without it they silently fall back to genphy and
lose the chip-specific setup and fixups. Every device using
kmod-dsa-qca8k already pulls it in manually except the MikroTik
RB960PGS, which was missing it.
Add the dependency, like other DSA packages do with their PHY drivers,
and drop the now-redundant device package entries.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25767
Signed-off-by: Robert Marko <robimarko@gmail.com>
All of these AR8327s are claimed through the PHY ID by
ar8xxx_phy_probe(), which needs a plain ethernet-phy@0 node carrying
qca,ar8327-initvals, while a CPU port has to hang off a phandle to
that PHY. The switch nodes already in the tree take the other path:
ar8xxx_mdiodev_probe() claims them by compatible and the CPU port
runs off a fixed-link. Both end up with the same single swconfig
device and the same initvals.
Switch the remaining boards over to that second form, i.e. an
ethernet-switch@10 with compatible = "qca,ar8327" and reg = <0x10>.
0x10 is the first register of the AR8327 window, 0x18 being the page
select register, so that is the address to probe at. Where the phy-mode
only lived on the PHY node, move it to the MAC that took over the
link.
For zyxel,nbg6x16, wd,mynet-n750, and comfast,cf-wr650ac, fix the address
from 1f to 10. The former is for built-in 100Mbps switches. The mdio1
stuff is also irrelevant. Both ethernet interfaces are part of the switch.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25467
Signed-off-by: Robert Marko <robimarko@gmail.com>
These external AR8236s were copied from the builtin-switch pattern
(switch0@1f). QCA9558 has no builtin switch; AR8236 register access
starts at MDIO 0x10.
Use ethernet-switch@10 with compatible = "qca,ar8236" and reg = <0x10>,
matching the other external QCA switches.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25467
Signed-off-by: Robert Marko <robimarko@gmail.com>
Current GL-E750 units (V2, sold as "Mudi V2") ship a QCA9887 without
calibration data in its EEPROM, so the 5 GHz radio never comes up:
ath10k_pci 0000:00:00.0: failed to read device EEPROM at 0000
ath10k_pci 0000:00:00.0: failed to read calibration data from EEPROM: -22
On V2 the calibration is stored in art at 0x5000 (0x844 bytes, starting
with its length 0x0844). On V1 the radio has calibration in EEPROM and
art is empty at that offset (0xff apart from a MAC address), so the
block cannot simply be wired up as an nvmem cell: doing that on a V1
makes the firmware fail to boot ("wmi unified ready event not
received") and the 5 GHz radio disappears.
Extract the block as the ath10k cal file only when it carries the
expected length header, otherwise leave ath10k to read its EEPROM.
Tested with this script installed on 24.10.8 (kernel 6.6) and on a
main snapshot r36812-13f1e1c66d (kernel 6.18), same results on both:
- GL-E750 V1: the block is discarded, ath10k reports "cal eeprom";
5 GHz AP on ch 36, VHT80, 23 dBm.
- GL-E750 V2: without the script ath10k fails ("could not probe fw");
with it the block is used, ath10k reports "cal file" and the 5 GHz
AP comes up on ch 36, VHT80, 23 dBm with the MAC from art.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Serv Pol <tureens_balsa_7g@icloud.com>
Link: https://github.com/openwrt/openwrt/pull/25606
Signed-off-by: Robert Marko <robimarko@gmail.com>
swconfig,port is used in only two places, here and ramips. This stuff is
already handled in userspace. No need for it here.
This aliases node is not only in the wrong location, it serves no
purpose. Remove.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25406
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
The factory images of the ZyXEL NWA11xx devices differ between builds
in the tar.bz2 they wrap:
-drwxr-xr-x 0 buildbot (1000) buildbot (1000) 0 2026-09-24 21:39:18 ./
-rw-r--r-- 0 buildbot (1000) buildbot (1000) 3387 2026-09-24 21:39:18 ./vmlinux_mi124_f1e.lzma.uImage
-rw-r--r-- 0 buildbot (1000) buildbot (1000) 8388608 2026-09-24 21:39:18 ./mi124_f1e-jffs2
+drwxr-xr-x 0 rebuilder (1000) rebuilder (1000) 0 2026-09-25 01:03:01 ./
+-rw-r--r-- 0 rebuilder (1000) rebuilder (1000) 8388608 2026-09-25 01:03:01 ./mi124_f1e-jffs2
+-rw-r--r-- 0 rebuilder (1000) rebuilder (1000) 3387 2026-09-25 01:03:01 ./vmlinux_mi124_f1e.lzma.uImage
zyxel-tar-bz2 archives the staging directory as it is, so owner, mtime
and the order of the members come from the build host.
Store the members as root with the mtime set to SOURCE_DATE_EPOCH and
without group or other write permission. List them explicitly, kernel
first, which is the order of the images built so far, instead of
sorting them by name.
Link: https://github.com/openwrt/openwrt/pull/25389
Signed-off-by: Paul Spooren <mail@aparcar.org>
The driver doesn't really care about the address in dts, but might as
well fix it anyway.
0 is just wrong.
1f is the address for the builtin FE switch, not the external gigabit
switch.
10 is the driver default.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25370
Signed-off-by: Robert Marko <robimarko@gmail.com>
This reverts commit 487ff3cfa0.
Three problems:
CONFIG_AR8216_PHY is enabled and to stop it from interfering and
crashing on boot, internal MDIO needs to be used.
Once internal MDIO gets used, ports end up dying even in the absence of
traffic. This is currently believed to be an issue with qca,qca8327
specifically. There are no reports of qca,qca8337 behaving badly.
Routing speed with DSA becomes much slower. Gigabit routing is no longer
doable, even with flow offload. This needs further research.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25308
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
The generic config builds CONFIG_INTEL_XWAY_PHY for all devices while
only a single one uses it. Avoid bloating the kernel by using the module
for the only device that uses this PHY.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25294
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
The module is available where needed. It's also unused by ath79 devices.
The symbol was introduced in the transition to ath79. The hope was
probably that all devices would be migrated, but the one user in ar71xx
(RB493) never got converted.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25274
Signed-off-by: Robert Marko <robimarko@gmail.com>
Rename the switch, port and PHY nodes to match the upstream device
tree binding names for the qca8k driver. Also drop the now superfluous
hex form for the switch MDIO address on the RB-951G-2HnD.
No functional change.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25188
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
Convert 4 devices from the legacy swconfig framework to DSA.
- Replace the deprecated qca,ar8327 switch binding with the modern
qca,qca8327 DSA binding in the device tree, defining each port
explicitly (cpu, wan, lan1-4) with appropriate PHY handles and
fixed-link configurations.
- Move the board out of the shared swconfig switch setup in
02_network and add a DSA-specific network configuration.
- Add a compat-version bump (1.1) via 05_compat-version to trigger
automatic config migration on upgrade.
- Update the image Makefile to drop swconfig from device packages
and add the necessary DSA dependencies.
This enables native DSA features such as bridge offloading and
simplifies the network stack by removing the swconfig abstraction
layer.
These routers have enough space for DSA so no concern there.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24011
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
The u-boot-env0 partition on this board stores a redundant U-Boot
environment (4-byte CRC32 + 1-byte flag + data), with the flag byte
differing between the u-boot-env0/u-boot-env1 copies (0x00 vs 0x01).
The actual environment size used by U-Boot for the CRC calculation is
0x1000 bytes, not the full 0x10000 byte partition.
The DTS declared this as the plain, non-redundant "u-boot,env" layout
with no env-size, so the kernel's u-boot-env nvmem-layout driver
miscomputes the CRC and fails to probe:
u-boot-env-layout ...nvmem-layout: Invalid calculated CRC32: 0xbc490a68 (expected: 0xfae56b95)
u-boot-env-layout ...nvmem-layout: probe with driver u-boot-env-layout failed with error -22
Because the probe fails, the macaddr_uboot_ethaddr nvmem cell is never
created, so eth0's nvmem-cells reference never resolves and the
ag71xx-legacy platform device is stuck in "deferred probe pending"
forever - the device boots with no functioning Ethernet interface at
all.
Switch to "u-boot,env-redundant-count" (matching the redundant-env
layout already used on other boards from this vendor lineage, e.g.
qca9557_extreme-networks_ws-ap3805i.dts) and set env-size to the
verified 0x1000, which fixes CRC validation and lets eth0 probe
successfully.
Verified on real hardware: before the fix, eth0 never comes up
(confirmed against the official 25.12.5 release, matching CRC values
exactly); after the fix, eth0 links up normally and dmesg is free of
any CRC/nvmem-layout errors.
Signed-off-by: Zoltan Szalay <dealer@ddsweb.hu>
Signed-off-by: Zoltan Szalay <szazo@halycomp.hu>
Link: https://github.com/openwrt/openwrt/pull/24134
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
This commit adds support for the NanoStation Loco M2/M5 XW devices
on the ath79 target with test date (label on the packaging, not the
device) later than October 2017.
To discover whether you have the new version, open a console on the
stock web interface and run `dmesg | grep AR803`. New versions print
AR8035, v1 shows AR8032.
Specifications:
- AR9342 (rev 3) SoC @ 535 MHz
- 64 MB RAM
- 8 MB SPI flash
- 1x 10/100 Mbps Ethernet, 24 Vdc PoE-in
- AR8035 switch
- 2T2R 5 GHz radio, 22 dBm
- 13 dBi built-in directional antenna
- POWER/LAN green LEDs
- 4x RSSI LEDs (red, orange, green, green)
- UART (115200 8N1) on PCB
Flashing via TFTP:
- Use a pointy tool (e.g., pen cap, paper clip) and keep the reset
button on the device pressed
- Power on the device via PoE (keep reset button pressed)
- Keep pressing until LEDs flash alternatively LED1+LED3 =>
LED2+LED4 => LED1+LED3, etc.
- Release reset button
- The device starts a TFTP server at 192.168.1.20
- Set a static IP on the computer (e.g., 192.168.1.21/24)
- Upload via tftp the factory image:
$ tftp 192.168.1.20
tftp> bin
tftp> put openwrt-ath79-generic-xxxxx-ubnt_nanostation-loco-m-xw-v2-squashfs-factory.bin
MAC addresses: stored on Flash, in the "art" partition.
Signed-off-by: Matthias Urlichs <matthias@urlichs.de>
Link: https://github.com/openwrt/openwrt/pull/23912
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
On the ZoneFlex 7025 the uplink port (eth0) is connected to PHY 4 of
the AR7240 built-in switch. This PHY erroneously advertises
1000baseT/Full capability, even though the AR7240 built-in switch only
supports 10/100 Mbps.
Because of the bogus gigabit capability, phylib performs 1000BASE-T
master/slave resolution against the PHY's non-functional gigabit
registers, which never completes. Auto-negotiation then fails: the
link flaps between speeds or never comes up at all, while a manually
forced fixed speed works fine.
Cap the PHY at 100 Mbps so the gigabit capability is removed and the
master/slave resolution path is skipped. eth0 then auto-negotiates
reliably to 100 Mbps full-duplex.
Signed-off-by: Dhimant Thanki <dhimant.thanki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24022
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Use _scoped loop to about fwnode_handle_put everywhere.
Remove usage of of_node.
Use devm_led_classdev_register_ext to avoid fwnode handle leaks.
Remove custom struct_size function.
Fix other various issues found with AI.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21027
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Paul Spooren
Rosen Penev
Serv Pol
Edoardo Pinci
John Audia
Shivansh SainiandCursor
Shiji Yang
Leopoldo Pla
Zoltan Szalay
Matthias Urlichs
Dhimant Thanki