Backport patch merged upstream that optimize the QDMA rx queue descriptor
setup by configuring the CPU IDX only when needed.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
It seems that upstream one of the patch had a compilation erro caused by
merging net and net-next and it was fixed silently in a merge commit.
Fix this error in the affected patch.
Fixes: 155c610962 ("airoha: backport additional patch for memory leak and multi-serdes rework")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport upstream memory leak patch merged upstream and even more
preliminary patch for multi-serdes rewrk.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Previous commits carved out some TX configuration from different places
into a dedicated function. A cause of this is a behavioral change where
the TX amplifier values aren't applied anymore if it isn't a "fiber
mode". To restore this behavior and make the media/TX-RX configuration
more generic, we need a dedicated media type. The existing ones only
cover fiber and DACs, but not the other left case where a PHY is
attached to the SerDes. This now calls set_media for USXGMII and XSGMII
modes intentionally, both to prepare for future changes and to restore
previous behavior.
We do not have a reliable way to distinct between the actually used
media types, this is still a TODO. But several parts of the code already
have different values applied based on this information. Moreover, this
is especially needed for DAC cables to work properly. While this is
missing, we need to rely on inferring the media from the SerDes mode.
While at it, improve the call site of media handling since there's a
media type for all cases now. This allows to reduce the number of
function calls by moving it out and just have the media type in the
decision block.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22814
Signed-off-by: Robert Marko <robimarko@gmail.com>
Proceed with the consolidation of TX/RX path config by carving out some
TX configuration out into a separate function. For now, this only
affects TX amplifier config. But it already slims down other polluted
call sites and brings some structure into the TX/RX path config.
While at it, already provide a similar function for RX configuration.
This does nothing yet but should be filled with RX path config later.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22814
Signed-off-by: Robert Marko <robimarko@gmail.com>
Shed some light into the darkness by giving a part of the setup a
dedicated name. This applies to the magic data blocks in the generic
setup entrypoint and some writes in the media handling. This was just
copied from the SDK which doesn't annotate this properly with
information. But we can clearly connect this with some other functions
of the SDK and extract meaningful information.
The mentioned magic blocks and register writes set coefficients of three
amplifiers in the TX path, a pre-amp, a main-amp and a post-amp. They
are used to tune the signal for different kinds of media. Generic values
are applied for all SerDes and further special values for different media
types depending on the needs.
Provide a dedicated function that sets these amplifier coefficients.
Replace the mystic register writes with the function call so one can see
at a glance what's happening. Also replace the magic TX values with the
coefficients organized into a separate struct. This might be extended
further and is also applicable for RTL930x.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22814
Signed-off-by: Robert Marko <robimarko@gmail.com>
Within RTL931x set_media, two writes are applied in general for all modes
but later again changed depending on the mode. This is a confusing
pattern. To fix this, move those generic writes into the switch-block as
a default case. To maintain behavior, pull the 10G guard into the fiber
media case.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22814
Signed-off-by: Robert Marko <robimarko@gmail.com>
Relocate the analog reset code within set_media for RTL931X to have it
in one place at the very top of the function, running all reset actions
before further real configuration is done. Also drop a separate call to
rx_reset because a subsequent sequence already includes this
functionality.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22814
Signed-off-by: Robert Marko <robimarko@gmail.com>
eip93_hmac_setkey() allocates a temporary ahash transform for
computing HMAC ipad/opad key material. The allocation uses the
driver-specific cra_driver_name (e.g. "sha256-eip93") but passes
CRYPTO_ALG_ASYNC as the mask, which excludes async algorithms.
Since the EIP93 hash algorithms are the only ones registered
under those driver names and they are inherently async, the
lookup is self-contradictory and always fails with -ENOENT.
When called from the AEAD setkey path, this failure leaves the
SA record partially initialized with zeroed digest fields. A
subsequent crypto operation then dereferences a NULL pointer in
the request context, resulting in a kernel panic:
```
pc : eip93_aead_handle_result+0xc8c/0x1240 [crypto_hw_eip93]
lr : eip93_aead_handle_result+0xbec/0x1240 [crypto_hw_eip93]
sp : ffffffc082feb820
x29: ffffffc082feb820 x28: ffffff8011043980 x27: 0000000000000000
x26: 0000000000000000 x25: ffffffc078da0bc8 x24: 0000000091043980
x23: ffffff8004d59e50 x22: ffffff8004d59410 x21: ffffff8004d593c0
x20: ffffff8004d593c0 x19: ffffff8004d4f300 x18: 0000000000000000
x17: 0000000000000000 x16: 0000000000000000 x15: 0000007fda7aa498
x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000
x11: 0000000000000000 x10: fffffffff8127a80 x9 : 0000000000000000
x8 : ffffff8004d4f380 x7 : 0000000000000000 x6 : 000000000000003f
x5 : 0000000000000040 x4 : 0000000000000008 x3 : 0000000000000009
x2 : 0000000000000008 x1 : 0000000028000003 x0 : ffffff8004d388c0
Code: 910142b6 f94012e0 f9002aa0 f90006d3 (f9400740)
```
The reported symbol eip93_aead_handle_result+0xc8c is a
resolution artifact from static functions being merged under
the nearest exported symbol. Decoding the faulting sequence:
```
910142b6 ADD X22, X21, #0x50
f94012e0 LDR X0, [X23, #0x20]
f9002aa0 STR X0, [X21, #0x50]
f90006d3 STR X19, [X22, #0x8]
f9400740 LDR X0, [X26, #0x8]
```
The faulting LDR at [X26, #0x8] is loading ctx->flags
(offset 8 in eip93_hash_ctx), where ctx has been resolved
to NULL from a partially initialized or unreachable
transform context following the failed setkey.
Fix this by dropping the CRYPTO_ALG_ASYNC mask from the
crypto_alloc_ahash() call. The code already handles async
completion correctly via crypto_wait_req(), so there is no
requirement to restrict the lookup to synchronous algorithms.
Note that hashing a single 64-byte block through the hardware
is likely slower than doing it in software due to the DMA
round-trip overhead, but offloading it may still spare CPU
cycles on the slower embedded cores where this IP is found.
Fixes: 9739f5f93b78 ("crypto: eip93 - Add Inside Secure SafeXcel EIP-93 crypto engine support")
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
[Detailed investigation report of this bug]
Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/22886
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MCU (GD32E230G8) which controls the RTL8239 POE++ PSE chips can
sometimes hang. In this case, it is necessary to to reset the chip using
the nRESET pin which is connected to the GPIO1 of the RTL8231 GPIO
expander.
For a reset, the `/sys/class/gpio/poe_mcu_reset/value` file must be set to
1 for a short period and then back to 0. After that, the poemgr must be
"restarted" to the MCU back in the expected state.
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/22916
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix a long standing bug in the mediatek-cci-devfreq driver which leads
to the driver switching off the CPU power regulator in case of another
resource not being ready in time -- a classic probe-order race condition.
As a work-around it would of course just as well be possible to set the
CPU regulator as 'regulator-always-on' (and not just 'regulator-boot-on'),
but practically all MT7988 devices have copy&pasted the PMIC device tree
hunk which sets only 'regulator-boot-on').
Hence, in order not having to fix all device trees, a proper fix in the
driver is preferred.
Fixes: #683
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Since f1f0572d1 ("remove redundant integrated phy attribute") the
phy-is-integrated attribute of an phy in the dts is obsolete.
This was important for the INTERNAL_PHY() macro. Now it is
useless. Convert the macro to its successor PHY_C22().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22892
Signed-off-by: Robert Marko <robimarko@gmail.com>
CPR driver was converted to use of_device_get_match_data and it locally
constified the CPR match data structures but they are also stored per
regulator in their struct, these were not constified and would cause a
compile time error.
So, constify those as well.
Fixes: c1fa85f659 ("treewide: use of_device_get_match_data")
Signed-off-by: Robert Marko <robimarko@gmail.com>
The initial bringup missed two GPIO-related settings:
- TX Disable GPIO for the SFP modules
- LED Sync GPIO selection for the port LEDs
This adds the missing TX Disable GPIOs and muxes GPIO18 to LED sync
(there are HC595 shift registers on the board that require the sync).
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Link: https://github.com/openwrt/openwrt/pull/22551
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some new DRM kernel modules appeared in the 6.18 kernel and
are now prompting for selection when enabling DRM in the kernel.
The Gemini D-Link DIR-685 is always the first to run into this
problem hence let's fix it before someone else tries to enable
DRM.
Link: https://github.com/openwrt/openwrt/pull/22875
Signed-off-by: Linus Walleij <linusw@kernel.org>
Specification:
* CPU: MediaTek MT7628AN (580 MHz)
* Flash: GigaDevice GD25Q128CSIG (16 MiB)
* RAM: Winbond W9751G6KB-25 (64 MiB)
WikiDevi page: <https://wikidevi.wi-cat.ru/Keenetic_City_(KN-1510)>
How to flash:
* Configure TFTP server with IP address 192.168.1.2/24
* Serve OpenWrt factory image as "KN-1510_recovery.bin"
* Connect the PC to router's LAN port, hold the reset button and power
the router up. When the power LED starts blinking release the
button.
The same instructions apply to OEM firmware, except one can take it
from osvault.keenetic.net
Signed-off-by: Ivan Davydov <lotigara@lotigara.ru>
Link: https://github.com/openwrt/openwrt/pull/22404
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Specification:
The device is similar to the M30 but has only one LAN port and no WAN port.
- MT7981 CPU using 2.4GHz and 5GHz WiFi (both AX)
- 512MB RAM
- 128MB NAND flash with two UBI partitions with identical size
- 1 multi color LED (red, green, blue, white) connected via GCA230718
- 2 buttons (WPS, reset, LED)
- 1 1Gbit LAN port
Disassembly:
- There are two screws at the power connector which must be removed. Afterwards the top case can be removed (it is clipped on, so some tools are required).
Serial Interface:
- The serial interface can be connected to the 4 pin holes on the board. Do NOT connect VCC.
- The pins are labelled on the PCB (RX, TX, GND)
- Settings: 115200, 8N1
MAC addresses:
- LAN MAC is stored in partition "Odm" at offset 0x8f
- WLAN MAC (2.4 GHz and 5GHz) is LAN MAC + 1
Reverting back to OEM firmware:
- There is currently no easy way to revert back to the OEM image
- The methods from M30 and M60 doesn't seem to work anymore
- If you plan to revert back to OEM firmware later, do the following steps before flashing OpenWrt:
- Boot from initramfs as described in "Flashing via U-Boot" but don't flash anything
- Instead, make a backup of UBI and UBI1 partition
- The created dumps must be written to the initial partitions to revert back to OEM
Flashing via Recovery Web Interface:
- Set your IP address to 192.168.200.10, subnetmask 255.255.255.0
- Press the reset button while powering on the device
- Keep the reset button pressed until the LED blinks red
- Open a Chromium based and goto http://192.168.200.50/ (recovery web interface)
- Download openwrt-mediatek-filogic-dlink_aquila-pro-ai-e30-a1-squashfs-recovery.bin
- Note: The recovery web interface always reports successful flashing, even if it fails
- After flashing, the recovery web interface will try to forward the browser to 192.168.0.1 (can be ignored)
- If flashing was successful, OpenWrt is accessible via 192.168.1.1
- The recovery image boots an initramfs image, flash the sys upgrade image to get to „normal“ OpenWrt mode
Flashing via U-Boot:
- Open the case, connect to the UART console
- Set your IP address to 192.168.200.2, subnet mask 255.255.255.0. Connect to one of the LAN interfaces of the router
- Run a tftp server which provides openwrt-mediatek-filogic-dlink_aquila-pro-ai-e30-a1-initramfs-kernel.bin
- Supply the board with 12V
- Select "7. Load image" in the U-Boot menu
- Enter image file, tftp server IP and device IP (if they differ from the default).
- TFTP download to RAM will start. After a few seconds OpenWrt initramfs should start
- The initramfs is accessible via 192.168.1.1, change your IP address accordingly (or use multiple IP addresses on your interface)
- Perform a sysupgrade using openwrt-mediatek-filogic-dlink_aquila-pro-ai-e30-a1-squashfs-sysupgrade.bin
- Reboot the device. OpenWrt should start from flash now
Flashing via OEM web interface is not possible, as it will change the active partition and OpenWrt is only running on the first UBI partition.
Signed-off-by: Roland Reinl <reinlroland+github@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22776
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Replace conditional "LINUX_6_12:mod" / "!LINUX_6_12:mod" AUTOLOAD entries
with version-filtered module names using @lt6.18 / @ge6.18. This makes
version_filter emit plain module names into /etc/modules.d(e.g. "crc32c_generic"),
allowing kmodloader to find and load the correct module for the running kernel.
Fixes crc32c (and related crypto modules) not being autoloaded on 6.12 kernels.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/22798
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
EDUP EP-RT2983 comes with a factory installed version of OpenWrt 23.05
with device name "netis,n6".
Specification
--------------
- SoC : MediaTek MT7621AT, MIPS, 880 MHz
- RAM : 256 MiB
- Flash : NAND 128 MiB (Toshiba)
- WLAN : MT7905DAN + MT7975DN
- 2.4 GHz : b/g/n/ax, 574 Mbps, MIMO 2x2
- 5 GHz : a/n/ac/ax, 1201 Mbps, MIMO 2x2
- Ethernet : 10/100/1000 Mbps x4 (1x WAN, 3x LAN)
- UART : 3.3V, 115200n8
- Buttons : 1x Reset
1x WPS
- LEDs : 1x Power (green)
1x WiFi (green)
1x Mesh/WPS (green); flashing green during boot
3x LAN (green)
1x WAN (green); flashing red during upgrade and failsafe
- Power : 12 VDC 1A
Installation
-------------
1. Log in to LuCI
2. Go to System, Backup / Flash Firmware
3. If desired, backup the current system by saving (all) the mtdblock
contents.
4. Flash new firmware image, select Flash image.
5. Browse and select the sysupgrade file
"openwrt-*-ramips-mt7621-edup_ep-rt2983-squashfs-sysupgrade.bin"
and then Upload.
6. Unselect "Keep settings and retain the current configuration"
Note: All settings will be reset to default. WiFi is not enabled by
default so a connection via Ethernet is necessary to log in and set up.
7. Allow "Force upgrade" (tick the box if there is one), or press Continue
if there is no box to tick. This is because the name is now
"edup,ep-rt2983" as it should have been from the start.
8. Proceed to flash. Wait for reboot and keep power connected.
9. After reboot, default address to access LuCI is 192.168.1.1 with
no password
Recovery (UART)
----------------
1. Remove the 4 screws on the bottom and pry open the cover.
2. Connect serial adapter to the unpopulated serial header pins
TX, RX, GND near the WPS button. Do not connect VCC.
3. Start serial terminal (e.g. minicom, screen, etc) on the computer and
turn on the router.
4. As prompted, hit any key to stop autoboot.
5. Enter 2 to select "2. Upgrade firmware"
6. Enter 0 to select "0 - TFTP client (Default)"
7. Accept the defaults by pressing Enter for
"Input U-Boot's IP address: 192.168.1.1",
"TFTP server's IP address: 192.168.1.2",
"Input IP netmask: 255.255.255.0"
8. Assign your PC's Ethernet port a static IP 192.168.1.2 with netmask
255.255.255.0 and connect to a LAN port on the router using the
Ethernet cable. Disconnect all other network connections (e.g. WiFi) on
the computer.
9. Serve the factory image
"openwrt-*-ramips-mt7621-edup_ep-rt2983-squashfs-factory.bin" using
a TFTP server, e.g. tftpd64. For convenience, the filename can be renamed
to something shorter.
10. In the serial terminal, when prompted "Input file name:", enter the
filename from the previous step and press Enter.
11. The factory image will be flashed as indicated. Wait for reboot.
MAC addresses prototype
------------------------
+---------+---------------------+
| | MAC example |
+---------+---------------------+
| LAN | CC:D8:1F:47:xx:yy |
| WAN | CC:D8:1F:47:xx:yy+1 |
| WLAN 2G | CC:D8:1F:17:xx:yy+2 |
| WLAN 5G | CC:D8:1F:77:xx:yy+2 |
+---------+---------------------+
Signed-off-by: Ryan Leung <untilscour@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/22197
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
For some unknown reason carving out the mdio bus from the ethernet
node forgot the TP-Link SG2452P. The notation still reads
ðernet0 {
mdio: mdio-bus {
compatible = "realtek,rtl838x-mdio";
...
Like everywhere else it should be
&mdio_bus0 {
PHY_C22(0, 0)
...
Fix that.
Fixes: 57b270684 ("rearrange mdio-bus below mdio-controller")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22866
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Zoltan HERPAI
Christian Marangi
Rosen Penev
Eric Fahlgren
Linus Walleij
Shiji Yang
Ziyang Huang
Jonas Jelonek
Kenneth Kasilag
Sven Eckelmann
Sven Friedmann
Daniel Golle
Markus Stockhausen
Robert Marko
Andreas Böhler
Paul Spooren
Hiroki Utsunomiya
Ivan Davydov
Roland Reinl
Qingfang Deng
Luiz Angelo Daros de Luca
Mieczyslaw Nalewaj
Ryan Leung
Richard Huynh