The patch/config sequences we took over from the SDK are partially
redundant, i.e. they share common parts which can be separated per
speed. For example, the config for 10GR contains the one for 2500Base-X
but we have a dedicated one for 2500Base-X. This is a first step to
modularize and reverse-engineer those sequences, and decrease the size
they claim.
The sequences are nearly exclusive ordered by ascending pages. This
suggests that those register/writes do not have a hidden function of
performing inline resets but rather are just configuration values.
Likely, they may be applied in rather arbitrary order. Splitting up the
sequences here assumes this is true and does some minor order changes.
Testing shows no behavioral change. Looking at [1] there are no relevant
reset or trigger bits affected by that. Suspiciously ordered writes have
mostly been kept though.
USXGMII setup needs to be adjusted too due to shared sequence parts.
[1] https://github.com/plappermaul/realtek-doc/blob/82af3a36b7f65dbe2158fef3a9b71e7aab94315e/sources/rtk-dms1250/include/hal/phy/rtl8295_reg_def.h
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
USXGMII configuration is currently only performed via the patching
sequences although there's a dedicated function which configures several
parameters and assigns meaningful names to some register fields. It was
introduced in dca20f91ea ("realtek: add serdes patch for 10G_QXGMII")
but somewhat abandoned later due to a partial revert.
To improve the situation, prioritize usage of the function for USXGMII
variants and remove some parts from the patch sequences which seem to be
exclusive for USXGMII and thus can be covered by this function. Writes
to registers [0x6, 0xE], [0x6, 0x13] and [0x6, 0x14] can be dropped
completely because they are redundant. The bits really affected by
these writes (compared to the default register values aquired from a
dump) are overwritten below again. Testing on real hardware and USXGMII
supports this.
While at it, improve the style a bit and add comments explaining some of
the fields a bit more. Additionally, fix the call situation which
currently is dead code due to early exit. Provide two calls to the
mentioned functions but comment one of them to remain current
functionality. Names and meaning of fields is inferred from [1].
[1] https://github.com/plappermaul/realtek-doc/blob/82af3a36b7f65dbe2158fef3a9b71e7aab94315e/sources/rtk-dms1250/include/hal/phy/rtl8295_reg_def.h
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Handle QSGMII config earlier within the configuration function as a
preparation for subsequent patches in this area. Those will target
splitting up the config sequences and 5G-QSGMII is special there.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Rename the function that currently "applies patches" so that it covers
everything it does (and will do). It doesn't only apply patches but in
general performs configuration of a SerDes for a particular hardware
mode.
While at it, remove a print above that call because it is both placed
wrong and redundant due to what the generic pcs_config prints.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Change how patches are applied to reduce redundancy and make the code
more readable. Define a generic function that applies any patch. Within
the RTL930x patch application, define a local macro that helps to get
rid of repeated even/odd checks. While making the code cleaner, it is
also a preparation for further refactoring here.
This adds a local helper macro intended to be only temporary but keeps
the style of the code clean by avoiding a lot of if-else clauses.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Several devices (including the upcoming DGS-1250) need a fully
featured port definition that includes:
- port number
- label
- led-set
- pcs-handle
- phy-handle
- phy-mode
Provide a new macro for that and make the Zyxel XGS-1210 series
the first consumer of it.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22591
Signed-off-by: Robert Marko <robimarko@gmail.com>
Allow to configure the LM75 alert pin to active-high instead
of its default active-low. This patch is needed for the D-Link
DGS-1250 series where the alert pin steers the fan speed
between low and high.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22589
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
When the link goes down on the other end of a bond, it was noticed that the
switch was still trying to send data over this link.
Problem here is that net_lag_port_dev_txable() uses
bond_is_active_slave_dev() to look the state up. But this is actually
showing if a link is a NOT a backup - not if the link should be really be
TX enabled or not.
As a DSA driver, it is important to consume the DSA information.
dp->lag_tx_enabled must therefore be used for DSA .port_lag_change events.
This variable contains two information from the
struct netdev_lag_lower_state_info:
tx_enabled = linfo->link_up && linfo->tx_enabled;
Fixes: 89322b4d69 ("rtl93xx: dsa: Handle lag_change properly")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/22382
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL93xx based D-Link DGS-1250 series is currently being
prepared for OpenWrt support. These devices have some extras
that are not yet supported by the existing configuration.
Add the following items to the kernel configuration:
- CONFIG_SENSORS_GPIO_FAN: The devices have a simple gpio
controlled fan (0/1 aka off/on).
- CONFIG_I2C_GPIO_SHARED: The busses of the SFP+ slots are
not controlled by the built-in SOC I2C controller. Instead
they are realized by shared SCL bit banged GPIOs.
- CONFIG_EEPROM_AT24: The MAC address and other device data
is storend in an Atmel EEPROM.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22543
Signed-off-by: Robert Marko <robimarko@gmail.com>
The i2c-shared-gpio driver is designed to emulate up to four
i2c busses with distinct sda lines and a a shared scl line.
For some reason the check for the number of allowed busses
is one off and the driver can only allocate three busses.
Fix that.
Fixes: acd7ecc9ed ("realtek: add new i2c-gpio-shared driver")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22543
Signed-off-by: Robert Marko <robimarko@gmail.com>
Due to the last refactorings it has become clear that the following
code is wrong.
static void rteth_tx_timeout()
{
...
rteth_838x_hw_en_rxtx(ctrl);
A generic function must not call a device specific function directly.
Make hw_en_rxtx() a config member and call that instead of the
functions directly.
With this change another optimization can take place. hw_init()
currently calls device specific hw_en_rxtx() functions at the start
of the function. This is wrong. Initialize the hardware first before
activating the network rx/tx. Take out the multiple calls and place
the rx/tx setup just before the hw_init() call.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22421
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL93xx sets up the ring counters twice. One location is
inside rteth_93xx_hw_en_rxtx() and the other one is inside
rteth_93xx_hw_reset(). There are slight differences (e.g.
the ring size that is set or how the counters are cleared).
It is currently unclear where to place it best. For now
align this to RTL83xx and remove the coding from function
rteth_93xx_hw_en_rxtx(). Provide a complete & proper setup
in rteth_93xx_hw_reset().
Looking at the different old implementations one can see
that one initialized the ring counters with offset "-2".
This headroom is not needed. The old comment " Some SoCs
have issues with missing underflow protection" was only
regarding the way the counters are being resetted and not
how large they are setup.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22421
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove another family check inside rteth_open() and split it
out into device specific hw_init() helper functions.
RTL93xx still use a common rteth_93xx_hw_en_rxtx() helper.
That will be split later.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22421
Signed-off-by: Robert Marko <robimarko@gmail.com>
The hw_en_rxtx() functions still use the old prefix. Rename
them to align with the rest of the code. This refactoring
makes clear that there is a bug in rteth_tx_timeout(). A
generic function should not call a device specific function
directly. The bug will be fixed separately.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22421
Signed-off-by: Robert Marko <robimarko@gmail.com>
The hw_stop() function uses multiple family checks to determine
what needs to be done. Split that into device specific helpers
to simplify the code.
For further simplification common parts of the stop functions
have been kept in rteth_hw_stop().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22421
Signed-off-by: Robert Marko <robimarko@gmail.com>
The build system currently issues the following warnings.
../dts/rtl9303_xikestor_sks8300-8t.dts:57.4-17: Warning (reg_format):
/switchcore@1b000000/i2c@36c/i2c@0/temperature-sensor@48:reg: property
has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Fix that by providing proper cell data.
Fixes: c63433acd ("add support for XikeStor SKS8300-8T")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22593
Signed-off-by: Robert Marko <robimarko@gmail.com>
The build system currently issues the following warnings.
../dts/rtl9303_xikestor_sks8310-8x.dts:141.4-17: Warning (reg_format):
/switchcore@1b000000/i2c@36c/i2c@0/sensor@48:reg: property has invalid
length (4 bytes) (#address-cells == 2, #size-cells == 1)
Fix that by providing proper cell data.
Fixes: 4a73f72a2 ("add monitor IC node for XikeStor SKS8310-8X")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22593
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Netgear GS110TPP uses an RTL8214C to drive ports 9 and 10. The
DTS is missing the corresponding serdes assignment. From looking at
[1] it seems to be connected to pins 82-85 (serdes 2). Add that
definition. With that the last improper use of SWITCH_PORT() macro
is sorted out.
Remark: I do not own this device. The patch just resembles what
the picture [1] shows.
[1] https://svanheule.net/switches/_media/wiki/gs110tpp-top.jpg
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22232
Signed-off-by: Robert Marko <robimarko@gmail.com>
Until now the driver determines the validity of a phy (or port)
by checking "smi_bus[] < 0". That is somehow confusing. Align
with upstream and add a valid_port bitmask that can be used for
this check with common kernel bit operations.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22565
Signed-off-by: Robert Marko <robimarko@gmail.com>
The mdio driver has come a long way. The code is
quite stable now and whenever bugs are analyzed
one can look at the registers with devmem from
command line. Drop unneeded debugging information.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22565
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit backports 2 patches that add gpio controller support
to RTL9607C SoCs. It enables us to make use of anything that
can be controlled by GPIO on RTL9607C, like LEDs, buttons and such.
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/22358
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL93xx devices can no longer find the switch node in the DTS.
Commit 4c92254 ("relocate/retype switch node") refactored the
switch node definition to better align with upstream. Sadly
the redefinition for RTL93xx devices failed.
- RTL83xx: use "switch0: ethernet-switch"
- RTL93xx: use "switch0: switch@1b000000"
Follow up commit 8b969f7 ("drop realtek,smi-address property)
changed the dts lookup sequence for mdio initialization. On
RTL93xx devices it cannot find the switchnode via
of_get_child_by_name(dev->of_node->parent, "ethernet-switch")
Fix the switch node type for RTL93xx
Fixes: 8b969f7 ("drop realtek,smi-address property)
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22557
Signed-off-by: Robert Marko <robimarko@gmail.com>
The order within the FGCAL code is not optimal. Right now, there's
output printed even in successful cases (which doesn't really help) and
a value is read although it isn't used if the run succeeds. To fix both,
move that below the success loop exit so it's just printed in
non-success case where the information might be helpful.
Suggested-by: Bevan Weiss <bevan.weiss@gmail.com>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Comparing our calibration check with the one in the SDK ([1]), one can
see some discrepancies for which there are no apparent reasons. SGMII
and 1000Base-X are handled equal to XSGMII although they aren't in the
SDK and have different symbol error registers. USXGMII and 10GBase-R are
fine, but other modes are explicitly handled with failure then.
Restructure this by keeping XSGMII alone with its dedicated check (as
the SDK does) and handle all other modes differently. Though the SDK
just skips symbol error check for modes like SGMII, 1000Base-X,
2500Base-X, it was found to be ok to perform a simple check for them
too. Since we have also a default case in the symbol error read
implementation now, we can cover all other modes with default case here
too. As a side-effect, this removes the confusing and probably wrong
failure stating calibration has failed although just the checks were
insufficient.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Our implementation waiting for RX idle signal of a 10G SerDes deviates
from what the SDK does. While we timeout after 100 reads and thus cannot
really control the real time, the SDK times out after 10ms. Adjust that
accordingly by switching the timeout to ktime_* functions with a 10ms
timeout as per the SDK.
While at it, improve the overall style of the function a bit.
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix the symbol error read implementation to be usable for other modes
too. While we handle other modes as 'not supported', the SDK has a
generic read used in the 'default' case. Do the same so we can have
proper 2500Base-X support here and avoid confusing error messages.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Part of the calibration procedure contains some weird and harebrained
piece of code where a specific register write is guarded by a check for
the SerDes mode, otherwise an error is printed. But right after this
if-else block, the exact same write is applied anyway. Remove this
brain-dead piece of code with something meaningful, i.e. reference code
from the SDK [1]. Over there, more writes are applied and a proper check
is in place.
While at it, add some another comment to the code. While it is
honourable to have code developed by someone quite some time ago that
works, it's discouraged to just have code without any explanation
especially if it differs from the SDK.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
Calibration for RTL930x uses multiple iterations for several checks.
While this is fine and needed, it shouldn't be allowed to run forever in
trust that at some point there will always be a "valid" value causing a
loop exit. This has occured a couple of times, causing the driver to
loop forever in case something doesn't run as expected.
To avoid this (and in general as a good practice) limit the affected
loop to a rough estimate of 10 iterations instead of running possibly
forever. The estimate is based on the fact that under normal conditions
it usually takes 1 or 2 to iterations to succeed, more is likely never
to succeed but 10 gives some reasonable headroom.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22450
Signed-off-by: Robert Marko <robimarko@gmail.com>
A phy node in the dts has two properties:
- reg: the (overall) address of the phy
- realtek,smi-address: the address of the phy on its bus
This notation does not align with upstream. reg should be the address
of the phy on its bus. But where to get the overall address that is
needed for register writes to the hardware?
Luckily the mdio driver and the hardware design sync the ports and
phys (overall) addresses. Thus derive missing data from the dts port
nodes (below ethernet-ports). To realize this
- carve out the port mapping into a separate function to align with
the upstream driver.
- do more sanity checks and catch more inconsistencies
- raise more/better errors via dev_err_probe()
With this commit all dts files must be rewritten as follows:
- if phy has no realtek,smi-address leave it as is
- if phy has realtek,smi-address, write that value into the reg
property and drop realtek,smi-address.
Remark: This commit might bring some confusion about the phyXX and
phy@YY and <reg=YY> naming convention. To be somehow consistent with
the current port/phy identifiers from now on the dts will have:
- phyXX: where XX matches the port number
- phy@YY: where YY is the phy address on the mdio bus
- <reg=YY>: where YY is the phy address on the mdio bus
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22236
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The switch node is currently located outside of the switchcore@1b000000
tree. This makes it hard to find when referencing from other nodes in
this tree. Make it a subnode of switchcore and "retype" it to
ethernet-switch like upstream does.
This is not perfectly aligned as upstream just mixes the switchcore and
the ethernet-switch node into one. But this will be future work for
downstream.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22236
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
The Zyxel XGS1x10 DTS overzealously tries to avoid redundancies. For
this the phy24/phy25 definitions were split into a common and a device
specific part. Understanding how these phys are defined is therefore
a little bit tricky. Add a little bit of redundancy to make the
definitions easier to read and understand in a single location.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22236
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This commit adds support for RTL9607C/RTL8198D clocks to the existing
clk-rtl83xx driver. Setting clock rates is not supported due to
lack of knowledge on this topic at the moment. Clocks for CPU1, SRAM
and SPI can also be calculated but not included in this commit.
Since the registers, calculations are widely different to RTL83XX it
was decide to have different clk_ops for RTL960X.
The code was partly based on naseef's work with some changes to
integrate it into the clk-rtl83xx driver.
Tested-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/22080
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL8226 PHYs in Zyxel XGS1010-10 and XGS1210-10 rev A1 have swapped
MDI lanes. Specify this in the device tree, so the driver can configure
it. With this change, the PHYs no longer require initialization by the
bootloader.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/21261
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The PHY supports swapping the MDI pairs (ABCD->DCBA) to simplify board
layout. On devices making use of this, it needs to be configured in the
driver, otherwise the PHY won't work properly.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/21261
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Jonas Jelonek
Markus Stockhausen
Sven Eckelmann
Damien Dejean
Rosen Penev
Andreas Böhler
Rustam Adilov
John Audia
Jan Hoffmann
