Instead of the whole series from Microchips UNG kernel, use the simple
upstream pending support.
Update the Tactical 1000 DTS with driver changes.
There is no HS200 support in the SoC controller.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Backport a series of upstream patches for the adt7470 hwmon driver,
accepted for kernel v7.3. It exposes the fan control lines via the
generic PWM framework and thermal zone sensors.
Instead of relying on userland scripts, the kernel can now control
the fan speed directly through standard cooling maps and PWM fans
configured in the DTS. Currently in the tree, only edgecore_ecs4100-12ph
seems to use this chip.
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24803
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Linus Torvalds released the next kernel after 6.19 as version 7.0
instead of 6.20. Rename the backported patch files accordingly so
their names correctly reflect the upstream release they originate
from. This is a pure rename (100% similarity), no functional changes.
Affected targets:
- microchipsw (patches-6.18)
- qualcommax (patches-6.12, patches-6.18)
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/24491
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
On the TSN and RED variants of SparX-5 and LAN969x TAS (Time-Aware Shaper)
is present in the silicon.
Currently, the driver does not use configure it at all, which means that
the TAS_PROFILE_CONFIG.LINK_SPEED[1] value is left at the default of 3
which means that its configured for 1 Gbps.
So, running iperf between two 10G switch ports will result in only 940-ish
Mbps while we should be getting around 9.3 Gbps.
Correctly populating the TAS_PROFILE_CONFIG.LINK_SPEED[1] with the current
port speed fixes this issue and we achieve around 9.4 Gbps between two 10G
switch ports.
So, port the TAS port link speed setting from the vendor BSP 6.18 kernel[2]
[1] https://microchip-ung.github.io/lan969x-industrial_reginfo/reginfo_LAN969x-Industrial.html?select=hsch,tas_profile_cfg,tas_profile_config,link_speed
[2] https://github.com/microchip-ung/linux/tree/bsp-6.18-2026
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Selection of Sparx5 hwmon driver for LAN969x was upstreamed, so use that
instead of the downstream patch.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Currently, MDIO driver will print the probe defferal as error.
So, instead of spaming the log, backport the upstream fix for it.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Currently, moving from a port on one LAN8814 PHY package to another results
in a no traffic flowing on that new port.
It was tracked down to upstream change that fixed the issue that QSGMII
was soft reset on .config_init of each of 4 PHY-s in the package resulting
in a temporary traffic loss until QSGMII resynced.
However, it seems that the QSGMII soft reset timing is crucial and doing
the reset during probe only cause the QSGMII link to become partially
unsynced (Like 2 or 3 lanes are not synced).
So, add an upstream pending patch[1] to fix this, patch was modified as we
dont have the inband caps currently.
[1] https://patchwork.kernel.org/project/netdevbpf/patch/20260428134138.1741253-1-robert.marko@sartura.hr/
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
As preparation for enabling 6.18 kernel, rename the existing config to a
version specific 6.12 config.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Expand the FIP partition size to future proof and allow custom firmware
to be used as BL31 instead of U-Boot.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
LAN969x DTS was finally merged upstream, so lets backport the backported
DTS instead of keeping a local copy.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Tactical 1000 has per per port RS0 and RS1 pins, however internally they
are tied together.
So, model them as RS0 at least.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
SFP I2C buses for ports 1 and 3 were swapped as order changed on production
boards.
So, swap them around to fix SFP 1 and 3 failed to read EEPROM errors.
Fixes: 29b3d929a6 ("microchipsw: lan969x: add Novarq Tactical 1000")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Now that DCB is enabled by default, it makes sense to include it on
lan969x.
While we are here, lets include ip-bridge as these devices are switches
and the Busybox applet does not expose enough functionality.
These devices have no space constraints.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Update the DTS to the latest pending upstream version, it looks like this
should get merged soon upstream.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Due to PTP conflicts with CONFIG_ALL_KMODS which causes the end images
to end up with no switchdev driver included, lets switch to using the
switchdev and PHY drivers as modules instead.
Fixes: 88a404a2d1 ("microchipsw: add support for Microchip LAN969x switches")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Backport a bunch of upstream commits simplifying the RealTek PHY driver
and re-unifying the C22 and C45 driver instances.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Now that there is a consumer board available, lets drop source-only so that
buildbots provide official images.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Novarq Tactical 1000 is a LAN9696 based switch.
Specifications:
* CPU: Microchip LAN9696 switch SoC
* DRAM: 2GB DDR4
* Storage:
* 32MB QSPI NOR
* 16GB eMMC
* Networking:
* 24 x 10/100/1000 RJ45 via LAN8804 Quad PHY-s over QSGMII
* 4 x 100/1000/2500/5000/10000 SFP+ ports
* 1 x 10/100/1000 management RJ45 via LAN8840 PHY over RGMII (U-Boot too)
* USB: 1 x USB2.0 Type-A
* Management via USB-C (MCP2200):
* UART @ 115200 baud (Default), 921600 possible
* GPIO-s for bootstrap and reset
* LED-s:
* 2 per networking port (Green and Yellow)
* Green status LED
* Soft reset GPIO
* Power: 12V DC barrel jack
* External PoE:
* Option for PoE add-on
* Temperature Sensors:
* TMP1075 onboard
* CPU temperature
* Microchip MCP79402 RTC with battery back-up
* Microchip ATECC608C secure peripheral
* CPU heatsink with PWM fan
* Onboard header for case fan
Installation instructions:
1. Connect to UART via the USB-C port
2. Connect the management port
3. Boot and interrupt U-Boot
4. TFTP the OpenWrt initramfs image and boot it
5. SCP the OpenWrt eMMC GPT image to a running OpenWrt initramfs to /tmp
openwrt-microchipsw-lan969x-novarq_tactical-1000-squashfs-emmc-gpt.img.gz
And decompress it via:
gzip -d /tmp/openwrt-microchipsw-lan969x-novarq_tactical-1000-squashfs-emmc-gpt.img.gz
6. Wipe eMMC with:
dd if=/dev/zero of=/dev/mmcblk0 bs=1M
7. Flash OpenWrt eMMC image with:
dd if=/tmp/openwrt-microchipsw-lan969x-novarq_tactical-1000-squashfs-emmc-gpt.img
of=/dev/mmcblk0
After a restart OpenWrt will boot, and then regular sysupgrade can be used
for upgrades.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Microchip EV23X71A is a LAN9696 based EVB.
Specifications:
* CPU: Microchip LAN9696 switch SoC
* DRAM: 1GB DDR4
* Storage:
* 2MB QSPI NOR
* 4GB eMMC
* Networking:
* 24 x 10/100/1000 RJ45 via LAN8814 Quad PHY-s over QSGMII
* 4 x 100/1000/2500/5000/10000 SFP+ ports
* 1 x 10/100/1000 management RJ45 via LAN8840 PHY over RGMII (U-Boot too)
* USB: 1 x USB2.0 Type-A
* Management via USB-C (MCP2200):
* UART @ 115200 baud
* GPIO-s for bootstrap, reset and clock selection
* DIP switch for boostrap configuration
* LED-s:
* 2 per networking port (Green and Yellow)
* Green status LED
* Yellow reset LED
* Hard reset button
* Power:
* 12V DC barrel jack
* 48/56V DC screw terminal
* Selectable via toggle switch
* PTP support:
* Sync-E DPLL ZL30732B to generate the board required clocks
* Two SMAs for PTP and two for Station clock inputs and outputs
* Two ITU-T G.8275-compliant RS-422 interfaces for PTP applications
* External PoE:
* Option for PoE add-on, like EV14Y36A (IEEE 802.3af/at/bt Type 4
standard com-pliant)
* Option for external CPU control via SPI and PCIe
Installation instructions:
1. Connect to UART via the USB-C port
2. Connect the management port
3. Boot and interrupt U-Boot
4. TFTP the OpenWrt initramfs image and boot it
5. SCP the OpenWrt eMMC GPT image to a running OpenWrt initramfs to /tmp
openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img.gz
And decompress it via:
gzip -d /tmp/openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img.gz
6. Wipe eMMC with:
dd if=/dev/zero of=/dev/mmcblk0 bs=1M
7. Flash OpenWrt eMMC image with:
dd if=/tmp/openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img
of=/dev/mmcblk0
After a restart OpenWrt will boot, and then regular sysupgrade can be used
for upgrades.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Add a new microchipsw target aimed add supporting Microchip switch
SoC-s.
Start by supporting LAN969x SoC-s as the first subtarget.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Robert Marko
Luiz Angelo Daros de Luca
Mieczyslaw Nalewaj
John Audia
Shiji Yang
Jonas Jelonek
Daniel Golle