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Jan Hoffmann
45633073fe
At least the XikeStor SKT-2.5G-100M SFP module seems to internally use MDIO address 0 to access the PHY. This module allows accessing PHY registers using Rollball protocol on address 0x51, and also provides read-only C22 access on address 0x56. However, after disabling the PHYAD0 configuration bit, only 0xffff can be read via both methods (except for MMD device 30 which can still be accessed). Since having MDIO address 0 enabled shouldn't do any harm on SFP modules just leave the configuration bit alone in that case. Signed-off-by: Jan Hoffmann <jan@3e8.eu> Link: https://github.com/openwrt/openwrt/pull/23065 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
48 lines
1.8 KiB
Diff
48 lines
1.8 KiB
Diff
From: Daniel Golle <daniel@makrotopia.org>
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Date: Thu, 30 Jan 2025 05:38:31 +0000
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Subject: [PATCH] net: phy: realtek: disable MDIO broadcast
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RealTek's PHYs by default also listen on MDIO address 0 which is defined
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as broadcast address. This can lead to problems if there is an actual PHY
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(such as MT7981 built-in PHY) present at this address, as accessing that
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PHY may then confuse the RealTek PHY.
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Disabled listening on the MDIO broadcast address to avoid such problems.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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--- a/drivers/net/phy/realtek/realtek_main.c
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+++ b/drivers/net/phy/realtek/realtek_main.c
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@@ -173,6 +173,7 @@
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#define RTL8221B_PHYCR1 0xa430
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#define RTL8221B_PHYCR1_ALDPS_EN BIT(2)
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#define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12)
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+#define RTL8221B_PHYCR1_PHYAD_0_EN BIT(13)
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#define RTL8366RB_POWER_SAVE 0x15
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#define RTL8366RB_POWER_SAVE_ON BIT(12)
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@@ -1351,14 +1352,21 @@ static int rtl822xb_write_mmd(struct phy
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static int rtl822x_init_phycr1(struct phy_device *phydev, bool no_aldps)
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{
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struct rtl822x_priv *priv = phydev->priv;
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+ u16 mask = RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN;
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u16 val = 0;
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+ /* The controller in some SFP modules uses MDIO address 0 to access the
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+ * PHY. Leave the MDIO broadcast configuration bit alone for SFP
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+ * modules, as it won't cause any issues there anyways.
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+ */
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+ if (!phydev->is_on_sfp_module)
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+ mask |= RTL8221B_PHYCR1_PHYAD_0_EN;
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+
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if (priv->enable_aldps && !no_aldps)
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val = RTL8221B_PHYCR1_ALDPS_EN | RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN;
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return phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL8221B_PHYCR1,
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- RTL8221B_PHYCR1_ALDPS_EN |
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- RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN, val);
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+ mask, val);
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}
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static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1)
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