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Daniel Golle
c271123724
LINK_INBAND_ENABLE isn't valid for 5GBase-R/10GBase-R modes which by definition don't support any in-band an. Correctly report LINK_INBAND_DISABLE to fix 10G fiber SFP modules no longer working. While at it also get rid of downstream pn-swap properties in favor of using the upstream schema. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
85 lines
2.4 KiB
Diff
85 lines
2.4 KiB
Diff
From 3bc50ced1c42f0a31173eb65a61307d657109382 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 12 Dec 2023 03:47:31 +0000
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Subject: [PATCH 1/2] dt-bindings: net: pcs: add bindings for MediaTek USXGMII
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PCS
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MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
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it in order to configure and monitor the Ethernet SerDes link in
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USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
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legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
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interface modes are also available.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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.../bindings/net/pcs/mediatek,usxgmii.yaml | 63 +++++++++++++++++++
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1 file changed, 63 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
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@@ -0,0 +1,63 @@
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: MediaTek USXGMII PCS
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+
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+maintainers:
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+ - Daniel Golle <daniel@makrotopia.org>
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+
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+description:
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+ The MediaTek USXGMII PCS provides physical link control and status
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+ for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces
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+ provided by the PEXTP PHY.
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+ In order to also support legacy 2500Base-X, 1000Base-X and Cisco
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+ SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to
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+ provide those interfaces modes on the same SerDes interfaces shared
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+ with the USXGMII PCS.
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+
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+properties:
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+ $nodename:
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+ pattern: "^pcs@[0-9a-f]+$"
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+
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+ compatible:
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+ const: mediatek,mt7988-usxgmiisys
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: USXGMII top-level clock
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+
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+ resets:
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+ items:
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+ - description: XFI reset
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - resets
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+
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+allOf:
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+ - $ref: /schemas/phy/phy-common-props.yaml#
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
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+ #define MT7988_TOPRGU_XFI0_GRST 12
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ usxgmiisys0: pcs@10080000 {
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+ compatible = "mediatek,mt7988-usxgmiisys";
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+ reg = <0 0x10080000 0 0x1000>;
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+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
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+ resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
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+ };
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+ };
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