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Chukun Pan
69f0ee5baf
Backport changes to the pinctrl driver to bring it closer to
the upstream version. Also fix the bug in the pinctrl driver:
pinctrl-airoha ...pinctrl: invalid function mdio in map table
Fixes: bd7f5b3 ("airoha: replace AN7583 pinctrl patch with upstream version")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/20770
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
59 lines
1.8 KiB
Diff
59 lines
1.8 KiB
Diff
From 110930eb12699b92f767fc599c7ab467dd42358a Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Tue, 8 Jul 2025 14:49:56 +0200
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Subject: [PATCH 2/2] pinctrl: airoha: fix wrong MDIO function bitmaks
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With further testing with an attached Aeonsemi it was discovered that
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the pinctrl MDIO function applied the wrong bitmask. The error was
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probably caused by the confusing documentation related to these bits.
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Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE
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is never actually set but instead it's set force enable to the 2 GPIO
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(gpio 1-2) for MDC and MDIO pin.
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Applying this configuration permits correct functionality of any
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externally attached PHY.
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Cc: stable@vger.kernel.org
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Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/pinctrl/mediatek/pinctrl-airoha.c | 15 +++++++++------
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1 file changed, 9 insertions(+), 6 deletions(-)
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--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
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+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
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@@ -103,6 +103,9 @@
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#define JTAG_UDI_EN_MASK BIT(4)
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#define JTAG_DFD_EN_MASK BIT(3)
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+#define REG_FORCE_GPIO_EN 0x0228
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+#define FORCE_GPIO_EN(n) BIT(n)
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+
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/* LED MAP */
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#define REG_LAN_LED0_MAPPING 0x027c
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#define REG_LAN_LED1_MAPPING 0x0280
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@@ -714,16 +717,16 @@ static const struct airoha_pinctrl_func_
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.name = "mdio",
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.regmap[0] = {
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AIROHA_FUNC_MUX,
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- REG_GPIO_PON_MODE,
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- GPIO_SGMII_MDIO_MODE_MASK,
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- GPIO_SGMII_MDIO_MODE_MASK
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- },
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- .regmap[1] = {
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- AIROHA_FUNC_MUX,
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REG_GPIO_2ND_I2C_MODE,
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GPIO_MDC_IO_MASTER_MODE_MODE,
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GPIO_MDC_IO_MASTER_MODE_MODE
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},
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+ .regmap[1] = {
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+ AIROHA_FUNC_MUX,
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+ REG_FORCE_GPIO_EN,
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+ FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
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+ FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
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+ },
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.regmap_size = 2,
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},
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};
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