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John Audia
b00d26376e
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.12.81
Removed upstreamed:
ramips/patches-6.12/100-mips-ralink-update-CPU-clock-index.patch[1]
airoha/patches-6.12/135-v7.1-net-airoha-Add-missing-cleanup-bits-in-airoha_qdma_c.patch[2]
Manually rebased:
airoha/patches-6.12/048-01-v6.15-net-airoha-Move-airoha_eth-driver-in-a-dedicated-fol.patch
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.81&id=e8fd60338545f4bc9c23d3d4686c88324aa76fb8
2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.81&id=cce5027f9dc3a333ccbcd59a2c3ab2906bd08d30
Signed-off-by: John Audia <therealgraysky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/22913
[Modify airoha move patch]
(cherry picked from commit 8d827ccc93)
Link: https://github.com/openwrt/openwrt/pull/23162
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
92 lines
3.5 KiB
Diff
92 lines
3.5 KiB
Diff
From c71a7a861ef02aa2bebb18c2f3385aa3f19094e0 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Fri, 17 Oct 2025 11:06:19 +0200
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Subject: [PATCH 09/12] net: airoha: Select default ppe cpu port in
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airoha_dev_init()
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Select the PPE default cpu port in airoha_dev_init routine.
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This patch allows to distribute the load between the two available cpu
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ports (FE_PSE_PORT_CDM1 and FE_PSE_PORT_CDM2) if the device is running a
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single PPE module (e.g. 7583) selecting the cpu port based on the use
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QDMA device. For multi-PPE device (e.g. 7581) assign FE_PSE_PORT_CDM1 to
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PPE1 and FE_PSE_PORT_CDM2 to PPE2.
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Reviewed-by: Simon Horman <horms@kernel.org>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Link: https://patch.msgid.link/20251017-an7583-eth-support-v3-10-f28319666667@kernel.org
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/ethernet/airoha/airoha_eth.c | 38 ++++++++++--------------
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1 file changed, 16 insertions(+), 22 deletions(-)
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--- a/drivers/net/ethernet/airoha/airoha_eth.c
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+++ b/drivers/net/ethernet/airoha/airoha_eth.c
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@@ -531,25 +531,6 @@ static int airoha_fe_init(struct airoha_
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/* disable IFC by default */
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airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK);
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- airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(0),
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- FIELD_PREP(DFT_CPORT_MASK(7), FE_PSE_PORT_CDM1) |
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- FIELD_PREP(DFT_CPORT_MASK(6), FE_PSE_PORT_CDM1) |
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- FIELD_PREP(DFT_CPORT_MASK(5), FE_PSE_PORT_CDM1) |
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- FIELD_PREP(DFT_CPORT_MASK(4), FE_PSE_PORT_CDM1) |
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- FIELD_PREP(DFT_CPORT_MASK(3), FE_PSE_PORT_CDM1) |
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- FIELD_PREP(DFT_CPORT_MASK(2), FE_PSE_PORT_CDM1) |
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- FIELD_PREP(DFT_CPORT_MASK(1), FE_PSE_PORT_CDM1) |
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- FIELD_PREP(DFT_CPORT_MASK(0), FE_PSE_PORT_CDM1));
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- airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(1),
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- FIELD_PREP(DFT_CPORT_MASK(7), FE_PSE_PORT_CDM2) |
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- FIELD_PREP(DFT_CPORT_MASK(6), FE_PSE_PORT_CDM2) |
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- FIELD_PREP(DFT_CPORT_MASK(5), FE_PSE_PORT_CDM2) |
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- FIELD_PREP(DFT_CPORT_MASK(4), FE_PSE_PORT_CDM2) |
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- FIELD_PREP(DFT_CPORT_MASK(3), FE_PSE_PORT_CDM2) |
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- FIELD_PREP(DFT_CPORT_MASK(2), FE_PSE_PORT_CDM2) |
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- FIELD_PREP(DFT_CPORT_MASK(1), FE_PSE_PORT_CDM2) |
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- FIELD_PREP(DFT_CPORT_MASK(0), FE_PSE_PORT_CDM2));
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-
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/* enable 1:N vlan action, init vlan table */
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airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK);
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@@ -1777,8 +1758,10 @@ static void airhoha_set_gdm2_loopback(st
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static int airoha_dev_init(struct net_device *dev)
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{
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struct airoha_gdm_port *port = netdev_priv(dev);
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- struct airoha_eth *eth = port->qdma->eth;
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- u32 pse_port;
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+ struct airoha_qdma *qdma = port->qdma;
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+ struct airoha_eth *eth = qdma->eth;
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+ u32 pse_port, fe_cpu_port;
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+ u8 ppe_id;
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airoha_set_macaddr(port, dev->dev_addr);
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@@ -1791,16 +1774,27 @@ static int airoha_dev_init(struct net_de
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fallthrough;
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case 2:
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if (airoha_ppe_is_enabled(eth, 1)) {
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+ /* For PPE2 always use secondary cpu port. */
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+ fe_cpu_port = FE_PSE_PORT_CDM2;
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pse_port = FE_PSE_PORT_PPE2;
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break;
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}
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fallthrough;
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- default:
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+ default: {
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+ u8 qdma_id = qdma - ð->qdma[0];
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+
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+ /* For PPE1 select cpu port according to the running QDMA. */
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+ fe_cpu_port = qdma_id ? FE_PSE_PORT_CDM2 : FE_PSE_PORT_CDM1;
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pse_port = FE_PSE_PORT_PPE1;
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break;
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}
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+ }
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airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(port->id), pse_port);
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+ ppe_id = pse_port == FE_PSE_PORT_PPE2 ? 1 : 0;
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+ airoha_fe_rmw(eth, REG_PPE_DFT_CPORT0(ppe_id),
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+ DFT_CPORT_MASK(port->id),
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+ fe_cpu_port << __ffs(DFT_CPORT_MASK(port->id)));
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return 0;
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}
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