mirror of
https://github.com/openwrt/openwrt.git
synced 2026-10-13 02:28:43 +04:00
Vitaliy Sochnev
56da8deffa
The AN7581 USB PHY driver can't be reused on AN7583: the SoC has a
single USB PHY block driving two U2 ports and one U3 port, and both the
PLL init sequence and the U3 calibration differ.
Add the AN7583 USB PHY driver from Christian Marangi, with the PCIe PHY
part dropped (the AN7583 PCIe serdes has no DT node yet) and five bugs
fixed: an uninitialized "ret" passed to dev_err_probe(); a NULL check on
syscon_regmap_lookup_by_phandle(), which returns an ERR_PTR on failure;
a missing per-instance offset in u2_set_mode(), which made it write the
first U2 port's register regardless of the PHY it was called on; an
off-by-one bound in parse_subnode() allowing a write past the end of
priv->phys[]; and a discarded return value in phy_init(), which
swallowed the U3 calibration failure reported by u3_init().
Enable the driver on the an7583 subtarget. The an7581 subtarget keeps
its own PHY_AIROHA_USB driver untouched.
Signed-off-by: Vitaliy Sochnev <sochnev.v.74@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24609
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 38ac788893)
Link: https://github.com/openwrt/openwrt/pull/25320
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>