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Chad Monroe 5684f0d174 mediatek: filogic: SDG-8733A: reset the radio through pcie3

GPIO 9 is the reset input of the MT7995 radio module, active low.
The old description used it as a PERST line on pcie0 with active
high polarity, so the port reset toggled the module reset at the
wrong time and with the wrong polarity.

Describe it as wifi-reset-gpios on pcie3, the port wired to the
module reset. The PCIe controller then releases the module from
reset before link training, with a 100 ms delay.

Signed-off-by: Chad Monroe <chad@monroe.io>
Link: https://github.com/openwrt/openwrt/pull/24352
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>

2026-08-11 22:13:11 +02:00

base-files

…

dts

mediatek: filogic: SDG-8733A: reset the radio through pcie3

2026-08-11 22:13:11 +02:00

files/drivers

treewide: remove fwnode_for_each_available_child_node

2026-07-09 09:33:41 +02:00

files-6.18

mediatek: filogic: replace mtd-eeprom with nvmem

2026-06-14 23:42:52 +02:00