Files
openwrt/target/linux/lantiq/dts/vr9_avm_fritz7430.dts
T
Shiji Yang 7ff96bf05c lantiq: use gpiod API for PCIe GPIO reset
This is the recommended way for the OF based platform. According to
the original patch, set GPIO to low level to assert the reset, set
GPIO to high level to deassert. Hence, adjust the dts GPIO polarity
to active-low.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18948
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
2026-07-12 00:12:30 +02:00

256 lines
4.1 KiB
Devicetree

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "vr9.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mips/lantiq_rcu_gphy.h>
/ {
compatible = "avm,fritz7430", "lantiq,xway", "lantiq,vr9";
model = "AVM FRITZ!Box 7430";
chosen {
bootargs = "console=ttyLTQ0,115200";
};
aliases {
led-boot = &led_power;
led-failsafe = &led_info_red;
led-running = &led_power;
led-upgrade = &led_info_green;
led-dsl = &led_info_green;
led-wifi = &led_wifi;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x8000000>;
};
keys {
compatible = "gpio-keys-polled";
poll-interval = <100>;
dect {
label = "dect";
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PHONE>;
};
wifi {
label = "wifi";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 31 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
led_info_green: info_green {
label = "green:info";
gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
};
led_info_red: info_red {
label = "red:info";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
led_wifi: wifi {
label = "green:wifi";
gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
};
dect {
label = "green:dect";
gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
};
fon {
label = "green:fon";
gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
};
};
usb0_vbus: regulator-usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "USB0_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&localbus {
flash@0 {
compatible = "lantiq,nand-xway";
bank-width = <2>;
reg = <0 0x0 0x8000000>;
lantiq,cs = <1>;
pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
pinctrl-names = "default";
nand-use-soft-ecc-engine;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "urlader";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "nand-tffs";
reg = <0x40000 0x400000>;
read-only;
};
partition@440000 {
label = "kernel";
reg = <0x440000 0x400000>;
};
partition@840000 {
label = "ubi";
reg = <0x840000 0x3000000>;
};
partition@3840000 {
label = "reserved-kernel";
reg = <0x3840000 0x400000>;
read-only;
};
partition@3c40000 {
label = "reserved-filesystem";
reg = <0x3c40000 0x3000000>;
read-only;
};
partition@6c40000 {
label = "config";
reg = <0x6c40000 0x200000>;
read-only;
};
partition@6e40000 {
label = "nand-filesystem";
reg = <0x6e40000 0x11c0000>;
read-only;
};
};
};
};
&pcie0 {
status = "okay";
reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
wifi@0,0 {
compatible = "pci168c,0030";
reg = <0 0 0 0 0>;
qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */
};
};
};
&gphy0 {
lantiq,gphy-mode = <GPHY_MODE_FE>;
};
&gphy1 {
lantiq,gphy-mode = <GPHY_MODE_FE>;
};
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
pcie-rst {
lantiq,pins = "io11";
lantiq,open-drain = <1>;
lantiq,output = <1>;
};
};
};
&gswip_mdio {
phy11: ethernet-phy@11 {
reg = <0x11>;
};
phy12: ethernet-phy@12 {
reg = <0x12>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
};
phy14: ethernet-phy@14 {
reg = <0x14>;
};
};
&gswip_ports {
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy11>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy12>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy13>;
};
port@5 {
reg = <5>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy14>;
};
};
&usb_phy0 {
status = "okay";
};
&usb0 {
status = "okay";
vbus-supply = <&usb0_vbus>;
};