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Alexandru Gagniuc
7656e74a95
The "old" QCA8084 PHY driver does not implement 10g-qxgmii support. This is blocking several devices which use the QCA8084 form being merged. Qualcomm has provided updated drivers for the MAC (ppe), PCS, and PHY via github. We only need to update the PHY driver. Update the QCA8084 PHY driver using the patches provided by Qualcomm. Re-organize the patches so that the changes go into the existing patches. The SERDES functionality is new, so it gets new patches. This is sufficient to enable 10g-qxgmii on ipq95xx platforms. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/20721 Signed-off-by: Robert Marko <robimarko@gmail.com>
163 lines
5.1 KiB
Diff
163 lines
5.1 KiB
Diff
From a7fe2c13f3188bf01b60fb15063d028c76dd2f1a Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Mon, 29 Jan 2024 10:51:38 +0800
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Subject: [PATCH] net: phy: qca808x: Add QCA8084 probe function
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Add the PHY package probe function. The MDIO slave address of
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PHY, PCS and XPCS can be optionally customized by configuring
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the PHY package level register.
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In addition, enable system clock of PHY and de-assert PHY in
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the probe function so that the register of PHY device can be
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accessed, and the features of PHY can be acquired.
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Change-Id: I2251b9c5c398a21a4ef547a727189a934ad3a44c
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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Alex G: include <linux/reset.h>
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include "phylib.h" for phy_package_*() declarations
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select PHY_PACKAGE in Kconfig
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use phy_package_get_node() instead of phylib->shared->np
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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freckup c89414adf2ec7c
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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---
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drivers/net/phy/qcom/Kconfig | 1 +
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drivers/net/phy/qcom/qca808x.c | 92 ++++++++++++++++++++++++++++++++++
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2 files changed, 93 insertions(+)
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--- a/drivers/net/phy/qcom/Kconfig
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+++ b/drivers/net/phy/qcom/Kconfig
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@@ -18,6 +18,7 @@ config QCA83XX_PHY
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config QCA808X_PHY
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tristate "Qualcomm QCA808x PHYs"
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select QCOM_NET_PHYLIB
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+ select PHY_PACKAGE
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help
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Currently supports the QCA8081 model
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--- a/drivers/net/phy/qcom/qca808x.c
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+++ b/drivers/net/phy/qcom/qca808x.c
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@@ -2,7 +2,11 @@
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#include <linux/phy.h>
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#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/reset.h>
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+#include <linux/clk.h>
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+#include "../phylib.h"
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#include "qcom.h"
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/* ADC threshold */
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@@ -127,6 +131,21 @@
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#define QCA8084_MII_SW_ADDR_MASK GENMASK(31, 24)
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#define QCA8084_MII_REG_DATA_UPPER_16_BITS BIT(1)
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+/* QCA8084 integrates 4 PHYs, PCS0 and PCS1(includes PCS and XPCS). */
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+#define QCA8084_MDIO_DEVICE_NUM 7
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+
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+#define QCA8084_PCS_CFG 0xc90f014
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+#define QCA8084_PCS_ADDR0_MASK GENMASK(4, 0)
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+#define QCA8084_PCS_ADDR1_MASK GENMASK(9, 5)
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+#define QCA8084_PCS_ADDR2_MASK GENMASK(14, 10)
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+
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+#define QCA8084_EPHY_CFG 0xc90f018
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+#define QCA8084_EPHY_ADDR0_MASK GENMASK(4, 0)
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+#define QCA8084_EPHY_ADDR1_MASK GENMASK(9, 5)
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+#define QCA8084_EPHY_ADDR2_MASK GENMASK(14, 10)
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+#define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15)
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+#define QCA8084_EPHY_LDO_EN GENMASK(21, 20)
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+
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MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
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MODULE_LICENSE("GPL");
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@@ -839,6 +858,78 @@ static void qca8084_link_change_notify(s
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QCA8084_IPG_10_TO_11_EN : 0);
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}
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+static int qca8084_phy_package_probe_once(struct phy_device *phydev)
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+{
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+ int addr[QCA8084_MDIO_DEVICE_NUM] = {0, 1, 2, 3, 4, 5, 6};
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+ struct device_node *np = phy_package_get_node(phydev);
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+ int ret, clear, set;
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+
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+ /* Program the MDIO address of PHY and PCS optionally, the MDIO
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+ * address 0-6 is used for PHY and PCS MDIO devices by default.
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+ */
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+ ret = of_property_read_u32_array(np, "qcom,phy-addr-fixup",
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+ addr, ARRAY_SIZE(addr));
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+ if (ret && ret != -EINVAL)
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+ return ret;
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+
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+ /* Configure the MDIO addresses for the four PHY devices. */
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+ clear = QCA8084_EPHY_ADDR0_MASK | QCA8084_EPHY_ADDR1_MASK |
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+ QCA8084_EPHY_ADDR2_MASK | QCA8084_EPHY_ADDR3_MASK;
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+ set = FIELD_PREP(QCA8084_EPHY_ADDR0_MASK, addr[0]);
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+ set |= FIELD_PREP(QCA8084_EPHY_ADDR1_MASK, addr[1]);
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+ set |= FIELD_PREP(QCA8084_EPHY_ADDR2_MASK, addr[2]);
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+ set |= FIELD_PREP(QCA8084_EPHY_ADDR3_MASK, addr[3]);
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+
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+ ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, clear, set);
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+ if (ret)
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+ return ret;
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+
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+ /* Configure the MDIO addresses for PCS0 and PCS1 including
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+ * PCS and XPCS.
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+ */
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+ clear = QCA8084_PCS_ADDR0_MASK | QCA8084_PCS_ADDR1_MASK |
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+ QCA8084_PCS_ADDR2_MASK;
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+ set = FIELD_PREP(QCA8084_PCS_ADDR0_MASK, addr[4]);
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+ set |= FIELD_PREP(QCA8084_PCS_ADDR1_MASK, addr[5]);
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+ set |= FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6]);
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+
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+ return qca8084_mii_modify(phydev, QCA8084_PCS_CFG, clear, set);
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+}
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+
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+static int qca8084_probe(struct phy_device *phydev)
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+{
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+ struct device *dev = &phydev->mdio.dev;
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+ struct reset_control *rstc;
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+ struct clk *clk;
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+ int ret;
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+
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+ ret = devm_of_phy_package_join(dev, phydev, 0);
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+ if (ret)
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+ return ret;
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+
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+ if (phy_package_probe_once(phydev)) {
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+ ret = qca8084_phy_package_probe_once(phydev);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ /* Enable clock of PHY device, so that the PHY register
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+ * can be accessed to get PHY features.
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+ */
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+ clk = devm_clk_get_enabled(dev, NULL);
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+ if (IS_ERR(clk))
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+ return dev_err_probe(dev, PTR_ERR(clk),
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+ "Enable PHY clock failed\n");
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+
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+ /* De-assert PHY reset after the clock of PHY enabled. */
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+ rstc = devm_reset_control_get_exclusive(dev, NULL);
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+ if (IS_ERR(rstc))
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+ return dev_err_probe(dev, PTR_ERR(rstc),
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+ "Get PHY reset failed\n");
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+
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+ return reset_control_deassert(rstc);
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+}
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+
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static struct phy_driver qca808x_driver[] = {
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{
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/* Qualcomm QCA8081 */
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@@ -889,6 +980,7 @@ static struct phy_driver qca808x_driver[
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.cable_test_get_status = qca808x_cable_test_get_status,
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.config_init = qca8084_config_init,
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.link_change_notify = qca8084_link_change_notify,
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+ .probe = qca8084_probe,
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}, };
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module_phy_driver(qca808x_driver);
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