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Kenneth Kasilag
c16ef4f318
Align the USXGMII configuration sequence with the vendor SSDK: - Reset the PCS PLL by programming the whole reset register with the documented assert and release values and 100ms holds, instead of toggling a single bit for 1ms and relying on the power-on state of the remaining analog enables. - Keep the uniphy port clocks disabled across the reconfiguration and re-enable them after calibration, before releasing the XPCS reset. - Select in-band link detection explicitly rather than the SFP loss-of-signal input, which does not exist on non-SFP ports. - Wait for the 10GBASE-R receiver to link before enabling the USXGMII adaptation layer. Best-effort, since the PHY SerDes may only come up later. Other interface modes keep the previous behaviour. Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me> Link: https://github.com/openwrt/openwrt/pull/24033 Signed-off-by: Robert Marko <robimarko@gmail.com>