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Markus Stockhausen
cbb365a77b
Setup of register PLL_CML_CTRL has two issues. - It clears out bits 4-31 due to a wrong mask - Setup of bits 0-3 is not generic but depends on the mode of serdes 0/1 Fix that by relocating the code and adapting the mask. The error exists for longer but it has survived the pcs refactoring. Thus blame the corresponding refactoring commit. Fixes:b670d48("realtek: pcs: rtl838x: refactor imported code") Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/21956 Signed-off-by: Robert Marko <robimarko@gmail.com> (cherry picked from commitfdc3776068) Link: https://github.com/openwrt/openwrt/pull/22087 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>