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Currently, Ralink SoCs use the default ARCH_DMA_MINALIGN value of 128 bytes defined in mach-generic. This is excessive for these platforms and leads to significant memory waste in kmalloc. Override ARCH_DMA_MINALIGN to use L1_CACHE_BYTES, which is 16 bytes for RT288X and 32 bytes for other Ralink SoCs. Signed-off-by: Qingfang Deng <dqfext@gmail.com> Link: https://github.com/openwrt/openwrt/pull/23314 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>