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realtek: table: separate table access from DSA
The Otto SoCs reach most of their switch state through indirect table access: a command word carrying table, index and direction goes into one register, and the entry itself appears in a window of data registers. That mechanism is not layer 2 and has no natural home in a DSA driver; it sits in common.c only because DSA happens to be its first consumer. Move the descriptor array, struct table_reg and the rtl_table_* functions verbatim into table.c and table.h. Nothing is renamed and no line of the implementation changes; rtl-otto.h includes the new header, so every consumer compiles unchanged. The consumers already called these symbols externally, so relocating the definitions only moves them from common.o to table.o. Built for realtek/rtl930x before and after: rtl838x.o, rtl839x.o, rtl930x.o, rtl931x.o and l3.o are identical once debug sections are stripped, and common.o loses 1536 bytes of code and data, 1004 of text and 532 of data. The raw objects do differ, because CONFIG_DEBUG_INFO records line numbers from rtl-otto.h. Assisted-by: Claude:claude-opus-5 Signed-off-by: Gennaro Cimmino <gcimmino@rayonra.net> Link: https://github.com/openwrt/openwrt/pull/25062 Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This commit is contained in:
Gennaro Cimmino authored and 
Markus Stockhausen committed
1 parent
870c10eb8f
commit
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5 files changed
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-166
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@@ -1,3 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_NET_DSA_RTL83XX) += rtl_otto_dsa.o
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rtl_otto_dsa-objs := common.o dsa.o rtl838x.o rtl839x.o rtl930x.o rtl931x.o debugfs.o qos.o tc.o l3.o
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rtl_otto_dsa-objs := common.o table.o dsa.o rtl838x.o rtl839x.o rtl930x.o rtl931x.o debugfs.o qos.o tc.o l3.o
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@@ -33,122 +33,6 @@ int rtldsa_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
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return state;
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}
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static struct table_reg rtl838x_tbl_regs[] = {
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TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), /* RTL8380_TBL_L2 */
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TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), /* RTL8380_TBL_0 */
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TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), /* RTL8380_TBL_1 */
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TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), /* RTL8390_TBL_L2 */
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TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), /* RTL8390_TBL_0 */
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TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), /* RTL8390_TBL_1 */
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TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), /* RTL8390_TBL_2 */
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TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), /* RTL9300_TBL_L2 */
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TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), /* RTL9300_TBL_0 */
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TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), /* RTL9300_TBL_1 */
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TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), /* RTL9300_TBL_2 */
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TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), /* RTL9300_TBL_HSB */
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TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), /* RTL9300_TBL_HSA */
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TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), /* RTL9310_TBL_0 */
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TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), /* RTL9310_TBL_1 */
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TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), /* RTL9310_TBL_2 */
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TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), /* RTL9310_TBL_3 */
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TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), /* RTL9310_TBL_4 */
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TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), /* RTL9310_TBL_5 */
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};
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void rtl_table_init(void)
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{
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for (int i = 0; i < RTL_TBL_END; i++)
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mutex_init(&rtl838x_tbl_regs[i].lock);
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}
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/* Request access to table t in table access register r
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* Returns a handle to a lock for that table
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*/
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struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
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{
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if (r >= RTL_TBL_END)
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return NULL;
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if (t >= BIT(rtl838x_tbl_regs[r].c_bit - rtl838x_tbl_regs[r].t_bit))
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return NULL;
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mutex_lock(&rtl838x_tbl_regs[r].lock);
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rtl838x_tbl_regs[r].tbl = t;
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return &rtl838x_tbl_regs[r];
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}
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/* Release a table r, unlock the corresponding lock */
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void rtl_table_release(struct table_reg *r)
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{
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if (!r)
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return;
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/* pr_info("Unlocking %08x\n", (u32)r); */
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mutex_unlock(&r->lock);
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/* pr_info("Unlock done\n"); */
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}
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static int rtl_table_exec(struct table_reg *r, bool is_write, int idx)
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{
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int ret = 0;
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u32 cmd, val;
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/* Read/write bit has inverted meaning on RTL838x */
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if (r->rmode)
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cmd = is_write ? 0 : BIT(r->c_bit);
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else
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cmd = is_write ? BIT(r->c_bit) : 0;
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cmd |= BIT(r->c_bit + 1); /* Execute bit */
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cmd |= r->tbl << r->t_bit; /* Table type */
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cmd |= idx & (BIT(r->t_bit) - 1); /* Index */
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sw_w32(cmd, r->addr);
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ret = readx_poll_timeout(sw_r32, r->addr, val,
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!(val & BIT(r->c_bit + 1)), 20, 10000);
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if (ret)
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pr_err("%s: timeout\n", __func__);
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return ret;
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}
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/* Reads table index idx into the data registers of the table */
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int rtl_table_read(struct table_reg *r, int idx)
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{
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return rtl_table_exec(r, false, idx);
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}
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/* Writes the content of the table data registers into the table at index idx */
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int rtl_table_write(struct table_reg *r, int idx)
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{
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return rtl_table_exec(r, true, idx);
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}
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/* Returns the address of the ith data register of table register r
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* the address is relative to the beginning of the Switch-IO block at 0xbb000000
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*/
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inline u16 rtl_table_data(struct table_reg *r, int i)
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{
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if (i >= r->max_data)
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i = r->max_data - 1;
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return r->data + i * 4;
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}
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inline u32 rtl_table_data_r(struct table_reg *r, int i)
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{
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return sw_r32(rtl_table_data(r, i));
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}
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inline void rtl_table_data_w(struct table_reg *r, u32 v, int i)
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{
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sw_w32(v, rtl_table_data(r, i));
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}
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/* Port register accessor functions for the RTL838x and RTL930X SoCs */
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void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
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{
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@@ -6,6 +6,8 @@
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#include <asm/mach-rtl-otto/mach-rtl-otto.h>
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#include <net/dsa.h>
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#include "table.h"
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/* Register definition */
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#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7)))
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#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7)))
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@@ -1634,55 +1636,6 @@ struct rtldsa_mib_desc {
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const struct rtldsa_mib_list_item *list;
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};
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/* API for switch table access */
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struct table_reg {
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u16 addr;
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u16 data;
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u8 max_data;
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u8 c_bit;
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u8 t_bit;
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u8 rmode;
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u8 tbl;
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struct mutex lock;
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};
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#define TBL_DESC(_addr, _data, _max_data, _c_bit, _t_bit, _rmode) \
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{ .addr = _addr, .data = _data, .max_data = _max_data, .c_bit = _c_bit, \
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.t_bit = _t_bit, .rmode = _rmode \
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}
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typedef enum {
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RTL8380_TBL_L2 = 0,
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RTL8380_TBL_0,
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RTL8380_TBL_1,
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RTL8390_TBL_L2,
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RTL8390_TBL_0,
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RTL8390_TBL_1,
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RTL8390_TBL_2,
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RTL9300_TBL_L2,
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RTL9300_TBL_0,
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RTL9300_TBL_1,
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RTL9300_TBL_2,
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RTL9300_TBL_HSB,
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RTL9300_TBL_HSA,
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RTL9310_TBL_0,
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RTL9310_TBL_1,
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RTL9310_TBL_2,
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RTL9310_TBL_3,
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RTL9310_TBL_4,
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RTL9310_TBL_5,
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RTL_TBL_END
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} rtl838x_tbl_reg_t;
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void rtl_table_init(void);
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struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t);
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void rtl_table_release(struct table_reg *r);
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int rtl_table_read(struct table_reg *r, int idx);
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int rtl_table_write(struct table_reg *r, int idx);
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inline u16 rtl_table_data(struct table_reg *r, int i);
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inline u32 rtl_table_data_r(struct table_reg *r, int i);
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inline void rtl_table_data_w(struct table_reg *r, u32 v, int i);
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int rtldsa_83xx_lag_setup_algomask(struct rtl838x_switch_priv *priv, int group,
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struct netdev_lag_upper_info *info);
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@@ -0,0 +1,123 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/iopoll.h>
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#include <linux/mutex.h>
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#include <asm/mach-rtl-otto/mach-rtl-otto.h>
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#include "table.h"
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static struct table_reg rtl838x_tbl_regs[] = {
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TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), /* RTL8380_TBL_L2 */
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TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), /* RTL8380_TBL_0 */
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TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), /* RTL8380_TBL_1 */
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TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), /* RTL8390_TBL_L2 */
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TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), /* RTL8390_TBL_0 */
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TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), /* RTL8390_TBL_1 */
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TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), /* RTL8390_TBL_2 */
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TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), /* RTL9300_TBL_L2 */
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TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), /* RTL9300_TBL_0 */
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TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), /* RTL9300_TBL_1 */
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TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), /* RTL9300_TBL_2 */
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TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), /* RTL9300_TBL_HSB */
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TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), /* RTL9300_TBL_HSA */
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TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), /* RTL9310_TBL_0 */
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TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), /* RTL9310_TBL_1 */
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TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), /* RTL9310_TBL_2 */
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TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), /* RTL9310_TBL_3 */
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TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), /* RTL9310_TBL_4 */
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TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), /* RTL9310_TBL_5 */
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};
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void rtl_table_init(void)
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{
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for (int i = 0; i < RTL_TBL_END; i++)
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mutex_init(&rtl838x_tbl_regs[i].lock);
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}
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/* Request access to table t in table access register r
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* Returns a handle to a lock for that table
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*/
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struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
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{
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if (r >= RTL_TBL_END)
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return NULL;
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if (t >= BIT(rtl838x_tbl_regs[r].c_bit - rtl838x_tbl_regs[r].t_bit))
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return NULL;
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mutex_lock(&rtl838x_tbl_regs[r].lock);
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rtl838x_tbl_regs[r].tbl = t;
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return &rtl838x_tbl_regs[r];
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}
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/* Release a table r, unlock the corresponding lock */
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void rtl_table_release(struct table_reg *r)
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{
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if (!r)
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return;
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/* pr_info("Unlocking %08x\n", (u32)r); */
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mutex_unlock(&r->lock);
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/* pr_info("Unlock done\n"); */
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}
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static int rtl_table_exec(struct table_reg *r, bool is_write, int idx)
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{
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int ret = 0;
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u32 cmd, val;
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/* Read/write bit has inverted meaning on RTL838x */
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if (r->rmode)
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cmd = is_write ? 0 : BIT(r->c_bit);
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else
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cmd = is_write ? BIT(r->c_bit) : 0;
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cmd |= BIT(r->c_bit + 1); /* Execute bit */
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cmd |= r->tbl << r->t_bit; /* Table type */
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cmd |= idx & (BIT(r->t_bit) - 1); /* Index */
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sw_w32(cmd, r->addr);
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ret = readx_poll_timeout(sw_r32, r->addr, val,
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!(val & BIT(r->c_bit + 1)), 20, 10000);
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if (ret)
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pr_err("%s: timeout\n", __func__);
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return ret;
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}
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/* Reads table index idx into the data registers of the table */
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int rtl_table_read(struct table_reg *r, int idx)
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{
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return rtl_table_exec(r, false, idx);
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}
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/* Writes the content of the table data registers into the table at index idx */
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int rtl_table_write(struct table_reg *r, int idx)
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{
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return rtl_table_exec(r, true, idx);
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}
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/* Returns the address of the ith data register of table register r
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* the address is relative to the beginning of the Switch-IO block at 0xbb000000
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*/
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inline u16 rtl_table_data(struct table_reg *r, int i)
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{
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if (i >= r->max_data)
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i = r->max_data - 1;
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return r->data + i * 4;
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}
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inline u32 rtl_table_data_r(struct table_reg *r, int i)
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{
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return sw_r32(rtl_table_data(r, i));
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}
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inline void rtl_table_data_w(struct table_reg *r, u32 v, int i)
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{
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sw_w32(v, rtl_table_data(r, i));
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}
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@@ -0,0 +1,58 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _OTTO_TABLE_H
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#define _OTTO_TABLE_H
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#include <linux/mutex.h>
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#include <linux/types.h>
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/* API for switch table access */
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struct table_reg {
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u16 addr;
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u16 data;
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u8 max_data;
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u8 c_bit;
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u8 t_bit;
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u8 rmode;
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u8 tbl;
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struct mutex lock;
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};
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#define TBL_DESC(_addr, _data, _max_data, _c_bit, _t_bit, _rmode) \
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{ .addr = _addr, .data = _data, .max_data = _max_data, .c_bit = _c_bit, \
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.t_bit = _t_bit, .rmode = _rmode \
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}
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typedef enum {
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RTL8380_TBL_L2 = 0,
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RTL8380_TBL_0,
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RTL8380_TBL_1,
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RTL8390_TBL_L2,
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RTL8390_TBL_0,
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RTL8390_TBL_1,
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RTL8390_TBL_2,
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RTL9300_TBL_L2,
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RTL9300_TBL_0,
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RTL9300_TBL_1,
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RTL9300_TBL_2,
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RTL9300_TBL_HSB,
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RTL9300_TBL_HSA,
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RTL9310_TBL_0,
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RTL9310_TBL_1,
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RTL9310_TBL_2,
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RTL9310_TBL_3,
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RTL9310_TBL_4,
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RTL9310_TBL_5,
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RTL_TBL_END
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} rtl838x_tbl_reg_t;
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void rtl_table_init(void);
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struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t);
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void rtl_table_release(struct table_reg *r);
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int rtl_table_read(struct table_reg *r, int idx);
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int rtl_table_write(struct table_reg *r, int idx);
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inline u16 rtl_table_data(struct table_reg *r, int i);
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inline u32 rtl_table_data_r(struct table_reg *r, int i);
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inline void rtl_table_data_w(struct table_reg *r, u32 v, int i);
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#endif /* _OTTO_TABLE_H */
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Reference in new issue
Block a user