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realtek: dts: adapt RTL839x mdio bus topology

Browse Source 
The RTL839x actually has two mdio busses.

- mdio bus 0 serves ports 0..23
- mdio bus 1 serves ports 24..51

This is baked into hardware and cannot be changed during mdio driver
setup with any register write. With the recent changes the driver
handles ports, phys and busses in a more logical way. So a port X
is assigned to a bus Y and a phy Z (on that bus). This gives a
mapping like

- port 16 <=> bus 0, address 16
- port 32 <=> bus 1, address 8

This unique assignment is used in the mdio driver as follows:

- Request to read bus 1, address 8
- Lookup corresponding port = 32
- Read from port 32

Looking at RTL839x it becomes clear that bus/phy => port lookup can
be achieved in multiple different ways. The simple reason is, that
for this device the driver cannot setup the smi topology. It is
baked into the hardware. So adding a "virtual" second bus does not
change the hardware access but allows to keep phy addresses below 32.
Making an example

mdio_bus0 {
  PHY_C22(40, 40)
}

resolves to port 40. But the same can be achieved with

mdio_bus1 {
  PHY_C22(40, 16)
}

In the first case the kernel sees bus/phy = 0/40 and in the second
case it sees bus/phy = 1/16. Both result in the access to the same
phy device on hardware port 40.

Use this analogy for RTL839x devices to match the real hardware
topology. For this change the existing dts and

- activate mdio bus 1 in rtl839x.dtsi
- rearrange devices with ports 24..51 to make use of bus 1

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23186
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Markus Stockhausen
2026-05-01 19:04:01 +02:00
committed by Robert Marko
parent 4c16b5766c
commit 593df57731
11 changed files with 186 additions and 167 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/linux/realtek/dts/rtl8392_zyxel_gs1920-24hp-v1.dts
+5 -5
View File
@@ -70,12 +70,12 @@
};
};
&mdio_bus0 {
&mdio_bus1 {
/* External phy RTL8214FC #1 */
PHY_C22_SFP(48, 48, 0)
PHY_C22_SFP(49, 49, 1)
PHY_C22_SFP(50, 50, 2)
PHY_C22_SFP(51, 51, 3)
PHY_C22_SFP(48, 24, 0)
PHY_C22_SFP(49, 25, 1)
PHY_C22_SFP(50, 26, 2)
PHY_C22_SFP(51, 27, 3)
};
&switch0 {
target/linux/realtek/dts/rtl8393_d-link_dgs-1210-52.dts
+30 -28
View File
@@ -40,42 +40,44 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&mdio_bus1 {
/* External phy RTL8218B #4 */
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
/* External phy RTL8218B #5 */
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* External phy RTL8218B #6 */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
/* External phy RTL8214FC */
PHY_C22_SFP(48, 48, 0)
PHY_C22_SFP(49, 49, 1)
PHY_C22_SFP(50, 50, 2)
PHY_C22_SFP(51, 51, 3)
PHY_C22_SFP(48, 24, 0)
PHY_C22_SFP(49, 25, 1)
PHY_C22_SFP(50, 26, 2)
PHY_C22_SFP(51, 27, 3)
};
&switch0 {
target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts
+6 -4
View File
@@ -180,12 +180,14 @@
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
};
&mdio_bus1 {
/* External phy RTL8214FC */
PHY_C22_SFP(48, 48, 0)
PHY_C22_SFP(49, 49, 1)
PHY_C22_SFP(50, 50, 2)
PHY_C22_SFP(51, 51, 3)
PHY_C22_SFP(48, 24, 0)
PHY_C22_SFP(49, 25, 1)
PHY_C22_SFP(50, 26, 2)
PHY_C22_SFP(51, 27, 3)
};
&spi0 {
target/linux/realtek/dts/rtl8393_hpe_1920-48g-poe.dts
+5 -5
View File
@@ -90,11 +90,11 @@
};
};
&mdio_bus0 {
PHY_C22_SFP(48, 48, 0)
PHY_C22_SFP(49, 49, 1)
PHY_C22_SFP(50, 50, 2)
PHY_C22_SFP(51, 51, 3)
&mdio_bus1 {
PHY_C22_SFP(48, 24, 0)
PHY_C22_SFP(49, 25, 1)
PHY_C22_SFP(50, 26, 2)
PHY_C22_SFP(51, 27, 3)
};
&switch0 {
target/linux/realtek/dts/rtl8393_hpe_1920-48g.dts
+5 -5
View File
@@ -80,11 +80,11 @@
};
&mdio_bus0 {
PHY_C22_SFP(48, 48, 1)
PHY_C22_SFP(49, 49, 3)
PHY_C22_SFP(50, 50, 0)
PHY_C22_SFP(51, 51, 2)
&mdio_bus1 {
PHY_C22_SFP(48, 24, 1)
PHY_C22_SFP(49, 25, 3)
PHY_C22_SFP(50, 26, 0)
PHY_C22_SFP(51, 27, 2)
};
target/linux/realtek/dts/rtl8393_hpe_1920.dtsi
+26 -24
View File
@@ -51,33 +51,35 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
&mdio_bus1 {
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8393_netgear_gs750e.dts
+26 -24
View File
@@ -135,36 +135,38 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&mdio_bus1 {
/* External phy RTL8218B #4 */
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
/* External phy RTL8218B #5 */
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* External phy RTL8218B #6 */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8393_panasonic_m48eg-pn28480k.dts
+26 -24
View File
@@ -269,34 +269,36 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
&mdio_bus1 {
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* RTL8218FB */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
+26 -24
View File
@@ -309,36 +309,38 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&mdio_bus1 {
/* External phy RTL8218B #4 */
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
/* External phy RTL8218B #5 */
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* External phy RTL8218B #6 */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl8393_zyxel_gs1900-48.dtsi
+26 -24
View File
@@ -274,36 +274,38 @@
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&mdio_bus1 {
/* External phy RTL8218B #4 */
PHY_C22(24, 24)
PHY_C22(25, 25)
PHY_C22(26, 26)
PHY_C22(27, 27)
PHY_C22(28, 28)
PHY_C22(29, 29)
PHY_C22(30, 30)
PHY_C22(31, 31)
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
/* External phy RTL8218B #5 */
PHY_C22(32, 32)
PHY_C22(33, 33)
PHY_C22(34, 34)
PHY_C22(35, 35)
PHY_C22(36, 36)
PHY_C22(37, 37)
PHY_C22(38, 38)
PHY_C22(39, 39)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* External phy RTL8218B #6 */
PHY_C22(40, 40)
PHY_C22(41, 41)
PHY_C22(42, 42)
PHY_C22(43, 43)
PHY_C22(44, 44)
PHY_C22(45, 45)
PHY_C22(46, 46)
PHY_C22(47, 47)
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
target/linux/realtek/dts/rtl839x.dtsi
+5
View File
@@ -236,6 +236,11 @@
#address-cells = <1>;
#size-cells = <0>;
};
mdio_bus1: mdio-bus@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
mdio_aux: mdio-aux {