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realtek: mdio: refactor register handling
Until now the driver works as follows: - low level functions do a bulk write - high level functions have device specific structures Turn this upside down and hide the register logic in the low level functions. To achieve this: - add a register map to each device - change the low level write to use this map - use only one common unique command structure - use the command structure in the high level functions While we are here fix the RTL838x access patterns. The read functions do not need to set the bitmask. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/23230 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Markus Stockhausen
committed by
Robert Marko
Robert Marko
parent
94c79aebe3
commit
834d2e51f4
@@ -51,6 +51,8 @@
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/* MDIO bus registers/fields */
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#define RTMDIO_C45_DATA(devnum, regnum) ((((devnum) & GENMASK(4, 0)) << 16) | \
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((regnum) & GENMASK(15, 0)))
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#define RTMDIO_DATA_IN_HI_OUT_LOW 16
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#define RTMDIO_DATA_IN_LOW_OUT_HI 0
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#define RTMDIO_RUN BIT(0)
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#define RTMDIO_838X_SMI_GLB_CTRL 0xa100
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@@ -63,25 +65,25 @@
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#define RTMDIO_838X_CMD_READ_C45 BIT(1)
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#define RTMDIO_838X_CMD_WRITE_C22 BIT(2)
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#define RTMDIO_838X_CMD_WRITE_C45 (BIT(1) | BIT(2))
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#define RTMDIO_838X_CMD_MASK GENMASK(2, 0)
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#define RTMDIO_838X_C22_DATA(page, reg) ((reg) << 20 | RTMDIO_PAGE_SELECT << 15 | (page) << 3)
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#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2 0xa1c0
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#define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3 0xa1c4
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#define RTMDIO_838X_SMI_POLL_CTRL 0xa17c
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#define RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL 0xa1c8
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#define RTMDIO_839X_BCAST_PHYID_CTRL 0x03ec
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#define RTMDIO_839X_PHYREG_ACCESS_CTRL 0x03dc
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#define RTMDIO_839X_CMD_FAIL BIT(1)
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#define RTMDIO_839X_CMD_READ_C22 0
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#define RTMDIO_839X_CMD_READ_C45 BIT(2)
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#define RTMDIO_839X_CMD_WRITE_C22 BIT(3)
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#define RTMDIO_839X_CMD_WRITE_C45 (BIT(2) | BIT(3))
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#define RTMDIO_839X_CMD_MASK GENMASK(3, 0)
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#define RTMDIO_839X_C22_DATA(page, reg) ((reg) << 5 | (page) << 10 | \
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(((page) == RTMDIO_RAW_PAGE(RTMDIO_839X_NUM_PAGES)) ? \
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RTMDIO_PAGE_SELECT : 0) << 23)
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#define RTMDIO_839X_PHYREG_CTRL 0x03e0
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#define RTMDIO_839X_C22_DATA(page, reg) ((reg) << 5 | (page) << 10)
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#define RTMDIO_839X_PHYREG_CTRL (0x03e0)
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#define RTMDIO_839X_PHYREG_SKIP_EXT_PAGE GENMASK(8, 0)
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#define RTMDIO_839X_PHYREG_DATA_CTRL 0x03f0
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#define RTMDIO_839X_PHYREG_MMD_CTRL 0x03f4
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#define RTMDIO_839X_PHYREG_PORT_CTRL(x) (0x03e4 + (x) * 4)
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#define RTMDIO_839X_SMI_PORT_POLLING_CTRL 0x03fc
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#define RTMDIO_839X_SMI_GLB_CTRL 0x03f8
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@@ -95,9 +97,9 @@
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#define RTMDIO_930X_CMD_READ_C45 BIT(1)
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#define RTMDIO_930X_CMD_WRITE_C22 BIT(2)
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#define RTMDIO_930X_CMD_WRITE_C45 (BIT(1) | BIT(2))
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#define RTMDIO_930X_CMD_MASK (GENMASK(2, 0) | BIT(25))
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#define RTMDIO_930X_C22_DATA(page, reg) ((reg) << 20 | RTMDIO_PAGE_SELECT << 15 | (page) << 3)
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#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2 0xcb78
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#define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3 0xcb7c
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#define RTMDIO_930X_SMI_PORT0_15_POLLING_SEL 0xca08
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#define RTMDIO_930X_SMI_PORT16_27_POLLING_SEL 0xca0c
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#define RTMDIO_930X_SMI_MAC_TYPE_CTRL 0xca04
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@@ -111,7 +113,8 @@
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#define RTMDIO_930X_SMI_PORT0_5_ADDR_CTRL 0xcb80
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#define RTMDIO_931X_SMI_PORT_POLLING_CTRL 0x0ccc
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#define RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL 0x0c14
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#define RTMDIO_931X_SMI_INDRT_ACCESS_BC 0x0c14
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#define RTMDIO_931X_SMI_INDRT_PORT(pn) ((pn) << 5)
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#define RTMDIO_931X_SMI_GLB_CTRL0 0x0cc0
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#define RTMDIO_931X_SMI_GLB_PRVTE0_POLL(bus) BIT(20 + (bus))
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#define RTMDIO_931X_SMI_GLB_PRVTE1_POLL(bus) BIT(24 + (bus))
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@@ -124,9 +127,11 @@
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#define RTMDIO_931X_CMD_READ_C45 BIT(3)
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#define RTMDIO_931X_CMD_WRITE_C22 BIT(4)
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#define RTMDIO_931X_CMD_WRITE_C45 (BIT(3) | BIT(4))
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#define RTMDIO_931X_CMD_MASK GENMASK(4, 0)
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#define RTMDIO_931X_C22_DATA(page, reg) ((reg) << 6 | (page) << 11)
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#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1 0x0c04
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#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2(x) (0x0c08 + (x) * 4)
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#define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3 0x0c10
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#define RTMDIO_931X_SMI_INDRT_ACCESS_MMD 0x0c18
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#define RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL(pn) (0x0cac + ((pn) / 16) * 4)
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#define RTMDIO_931X_SMI_PHY_ABLTY_MDIO 0x0
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#define RTMDIO_931X_SMI_PHY_ABLTY_SDS 0x2
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@@ -230,10 +235,20 @@ struct rtmdio_chan {
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u8 smi_bus;
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};
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struct rtmdio_command_data {
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u32 brdcast;
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u32 c22_adr;
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u32 c45_adr;
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u32 ex_page;
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u32 io_data;
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u32 mask_lo;
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u32 mask_hi;
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};
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struct rtmdio_config {
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u32 cmd_fail;
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u32 cmd_mask;
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u32 cmd_reg;
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u32 cmd_io_shift;
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struct rtmdio_command_data cmd_regs;
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int bus_map_base;
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u16 num_busses;
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u16 num_pages;
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@@ -242,12 +257,8 @@ struct rtmdio_config {
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int port_map_base;
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int (*read_c22)(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val);
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int (*read_c45)(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val);
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u32 ret_mask;
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u32 ret_reg;
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int (*setup_ctrl)(struct rtmdio_ctrl *ctrl);
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int (*setup_polling)(struct rtmdio_ctrl *ctrl);
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u32 smi_base;
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u32 smi_size;
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int (*write_c22)(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val);
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int (*write_c45)(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val);
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};
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@@ -262,40 +273,6 @@ struct rtmdio_phy_info {
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unsigned int poll_lpa_1000;
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};
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struct rtmdio_838x_smi_access {
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u32 ctrl_0;
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u32 ctrl_1;
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u32 ctrl_2;
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u32 ctrl_3;
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};
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struct rtmdio_839x_smi_access {
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u32 accs_ctrl;
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u32 main_ctrl;
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u32 prt0_ctrl;
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u32 prt1_ctrl;
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u32 bcst_ctrl;
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u32 data_ctrl;
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u32 mmd0_ctrl;
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};
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struct rtmdio_930x_smi_access {
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u32 ctrl_0;
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u32 ctrl_1;
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u32 ctrl_2;
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u32 ctrl_3;
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};
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struct rtmdio_931x_smi_access {
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u32 ctrl_0;
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u32 ctrl_1;
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u32 ctrl_2;
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u32 ctrl_x;
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u32 ctrl_3;
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u32 b_ctrl;
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u32 m_ctrl;
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};
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static inline struct rtmdio_ctrl *rtmdio_ctrl_from_bus(struct mii_bus *bus)
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{
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return ((struct rtmdio_chan *)bus->priv)->ctrl;
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@@ -314,23 +291,49 @@ static int rtmdio_phy_to_port(struct mii_bus *bus, int phy)
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return -ENOENT;
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}
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static int rtmdio_run_cmd(struct mii_bus *bus, int cmd, void *smi_access, u32 *val)
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static int rtmdio_run_cmd(struct mii_bus *bus, u32 cmd,
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struct rtmdio_command_data *cmd_data, u32 *val)
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{
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struct rtmdio_ctrl *ctrl = rtmdio_ctrl_from_bus(bus);
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int ret, cmdstate;
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u32 cmdstate;
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int ret;
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ret = regmap_bulk_write(ctrl->map, ctrl->cfg->smi_base,
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smi_access, ctrl->cfg->smi_size / sizeof(u32));
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if (ctrl->cfg->cmd_regs.mask_hi) {
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/* high port count models have 3 extra command registers */
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ret = regmap_write(ctrl->map, ctrl->cfg->cmd_regs.brdcast, cmd_data->brdcast);
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if (ret)
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return ret;
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ret = regmap_write(ctrl->map, ctrl->cfg->cmd_regs.ex_page, cmd_data->ex_page);
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if (ret)
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return ret;
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ret = regmap_write(ctrl->map, ctrl->cfg->cmd_regs.mask_hi, cmd_data->mask_hi);
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if (ret)
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return ret;
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}
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ret = regmap_write(ctrl->map, ctrl->cfg->cmd_regs.mask_lo, cmd_data->mask_lo);
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if (ret)
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return ret;
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/* Use masks as C22 data and command bits share the same register. */
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ret = regmap_update_bits(ctrl->map, ctrl->cfg->cmd_reg,
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ctrl->cfg->cmd_mask, cmd | RTMDIO_RUN);
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/* depending on model write output data to high or low word in I/O register */
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ret = regmap_write(ctrl->map, ctrl->cfg->cmd_regs.io_data,
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cmd_data->io_data << ctrl->cfg->cmd_io_shift);
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if (ret)
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return ret;
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ret = regmap_read_poll_timeout(ctrl->map, ctrl->cfg->cmd_reg,
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ret = regmap_write(ctrl->map, ctrl->cfg->cmd_regs.c45_adr, cmd_data->c45_adr);
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if (ret)
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return ret;
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/* C22 data and command bits share the same register. */
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ret = regmap_write(ctrl->map, ctrl->cfg->cmd_regs.c22_adr,
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cmd_data->c22_adr | cmd | RTMDIO_RUN);
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if (ret)
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return ret;
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ret = regmap_read_poll_timeout(ctrl->map, ctrl->cfg->cmd_regs.c22_adr,
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cmdstate, !(cmdstate & RTMDIO_RUN), 20, 500000);
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if (ret) {
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dev_warn_once(&bus->dev, "access timed out\n");
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@@ -345,187 +348,186 @@ static int rtmdio_run_cmd(struct mii_bus *bus, int cmd, void *smi_access, u32 *v
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if (!val)
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return 0;
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ret = regmap_read(ctrl->map, ctrl->cfg->ret_reg, val);
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/* read back data from opposite word in I/O register */
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ret = regmap_read(ctrl->map, ctrl->cfg->cmd_regs.io_data, val);
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if (!ret)
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*val = (*val & ctrl->cfg->ret_mask) >> __ffs(ctrl->cfg->ret_mask);
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*val = (*val >> (16 - ctrl->cfg->cmd_io_shift)) & GENMASK(15, 0);
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return ret;
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}
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static int rtmdio_838x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
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{
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struct rtmdio_838x_smi_access smi_access = {
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.ctrl_0 = BIT(pn),
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.ctrl_1 = RTMDIO_838X_C22_DATA(page, reg),
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.ctrl_2 = pn << 16,
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struct rtmdio_command_data cmd_data = {
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.c22_adr = RTMDIO_838X_C22_DATA(page, reg),
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.io_data = pn,
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};
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return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_READ_C22, &smi_access, val);
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return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_READ_C22, &cmd_data, val);
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}
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static int rtmdio_838x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
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{
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struct rtmdio_838x_smi_access smi_access = {
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.ctrl_0 = BIT(pn),
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.ctrl_1 = RTMDIO_838X_C22_DATA(page, reg),
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.ctrl_2 = val << 16,
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struct rtmdio_command_data cmd_data = {
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.c22_adr = RTMDIO_838X_C22_DATA(page, reg),
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.io_data = val,
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.mask_lo = BIT(pn),
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};
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return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C22, &smi_access, NULL);
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return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C22, &cmd_data, NULL);
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}
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static int rtmdio_838x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
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{
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struct rtmdio_838x_smi_access smi_access = {
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.ctrl_0 = BIT(pn),
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.ctrl_2 = pn << 16,
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.ctrl_3 = RTMDIO_C45_DATA(devnum, regnum),
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struct rtmdio_command_data cmd_data = {
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.c45_adr = RTMDIO_C45_DATA(devnum, regnum),
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.io_data = pn,
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};
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return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_READ_C45, &smi_access, val);
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return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_READ_C45, &cmd_data, val);
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}
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static int rtmdio_838x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
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{
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struct rtmdio_838x_smi_access smi_access = {
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.ctrl_0 = BIT(pn),
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.ctrl_2 = val << 16,
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.ctrl_3 = RTMDIO_C45_DATA(devnum, regnum),
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struct rtmdio_command_data cmd_data = {
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.c45_adr = RTMDIO_C45_DATA(devnum, regnum),
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.io_data = val,
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.mask_lo = BIT(pn),
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};
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return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C45, &smi_access, NULL);
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return rtmdio_run_cmd(bus, RTMDIO_838X_CMD_WRITE_C45, &cmd_data, NULL);
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}
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static int rtmdio_839x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
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{
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struct rtmdio_839x_smi_access smi_access = {
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.main_ctrl = RTMDIO_839X_PHYREG_SKIP_EXT_PAGE,
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.data_ctrl = pn << 16,
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.accs_ctrl = RTMDIO_839X_C22_DATA(page, reg),
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struct rtmdio_command_data cmd_data = {
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.c22_adr = RTMDIO_839X_C22_DATA(page, reg),
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.ex_page = RTMDIO_839X_PHYREG_SKIP_EXT_PAGE,
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.io_data = pn,
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};
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return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_READ_C22, &smi_access, val);
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return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_READ_C22, &cmd_data, val);
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}
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static int rtmdio_839x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
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{
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struct rtmdio_839x_smi_access smi_access = {
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.main_ctrl = RTMDIO_839X_PHYREG_SKIP_EXT_PAGE,
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.data_ctrl = val << 16,
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.prt0_ctrl = (u32)(BIT_ULL(pn)),
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.prt1_ctrl = (u32)(BIT_ULL(pn) >> 32),
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.accs_ctrl = RTMDIO_839X_C22_DATA(page, reg),
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struct rtmdio_command_data cmd_data = {
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.c22_adr = RTMDIO_839X_C22_DATA(page, reg),
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.ex_page = RTMDIO_839X_PHYREG_SKIP_EXT_PAGE,
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.io_data = val,
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.mask_lo = (u32)(BIT_ULL(pn)),
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.mask_hi = (u32)(BIT_ULL(pn) >> 32),
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};
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return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C22, &smi_access, NULL);
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return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C22, &cmd_data, NULL);
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}
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static int rtmdio_839x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
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{
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struct rtmdio_839x_smi_access smi_access = {
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.data_ctrl = pn << 16,
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.mmd0_ctrl = RTMDIO_C45_DATA(devnum, regnum),
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struct rtmdio_command_data cmd_data = {
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.c45_adr = RTMDIO_C45_DATA(devnum, regnum),
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.io_data = pn,
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};
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return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_READ_C45, &smi_access, val);
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return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_READ_C45, &cmd_data, val);
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}
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static int rtmdio_839x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
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{
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struct rtmdio_839x_smi_access smi_access = {
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.data_ctrl = val << 16,
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.prt0_ctrl = (u32)(BIT_ULL(pn)),
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.prt1_ctrl = (u32)(BIT_ULL(pn) >> 32),
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.mmd0_ctrl = RTMDIO_C45_DATA(devnum, regnum),
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struct rtmdio_command_data cmd_data = {
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||||
.c45_adr = RTMDIO_C45_DATA(devnum, regnum),
|
||||
.io_data = val,
|
||||
.mask_lo = (u32)(BIT_ULL(pn)),
|
||||
.mask_hi = (u32)(BIT_ULL(pn) >> 32),
|
||||
};
|
||||
|
||||
return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C45, &smi_access, NULL);
|
||||
return rtmdio_run_cmd(bus, RTMDIO_839X_CMD_WRITE_C45, &cmd_data, NULL);
|
||||
}
|
||||
|
||||
static int rtmdio_930x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
|
||||
{
|
||||
struct rtmdio_930x_smi_access smi_access = {
|
||||
.ctrl_1 = RTMDIO_930X_C22_DATA(page, reg),
|
||||
.ctrl_2 = pn << 16,
|
||||
struct rtmdio_command_data cmd_data = {
|
||||
.c22_adr = RTMDIO_930X_C22_DATA(page, reg),
|
||||
.io_data = pn,
|
||||
};
|
||||
|
||||
return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_READ_C22, &smi_access, val);
|
||||
return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_READ_C22, &cmd_data, val);
|
||||
}
|
||||
|
||||
static int rtmdio_930x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
|
||||
{
|
||||
struct rtmdio_930x_smi_access smi_access = {
|
||||
.ctrl_0 = BIT(pn),
|
||||
.ctrl_1 = RTMDIO_930X_C22_DATA(page, reg),
|
||||
.ctrl_2 = val << 16,
|
||||
struct rtmdio_command_data cmd_data = {
|
||||
.c22_adr = RTMDIO_930X_C22_DATA(page, reg),
|
||||
.io_data = val,
|
||||
.mask_lo = BIT(pn),
|
||||
};
|
||||
|
||||
return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C22, &smi_access, NULL);
|
||||
return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C22, &cmd_data, NULL);
|
||||
}
|
||||
|
||||
static int rtmdio_930x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
|
||||
{
|
||||
struct rtmdio_930x_smi_access smi_access = {
|
||||
.ctrl_2 = pn << 16,
|
||||
.ctrl_3 = RTMDIO_C45_DATA(devnum, regnum),
|
||||
struct rtmdio_command_data cmd_data = {
|
||||
.c45_adr = RTMDIO_C45_DATA(devnum, regnum),
|
||||
.io_data = pn,
|
||||
};
|
||||
|
||||
return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_READ_C45, &smi_access, val);
|
||||
return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_READ_C45, &cmd_data, val);
|
||||
}
|
||||
|
||||
static int rtmdio_930x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
|
||||
{
|
||||
struct rtmdio_930x_smi_access smi_access = {
|
||||
.ctrl_0 = BIT(pn),
|
||||
.ctrl_2 = val << 16,
|
||||
.ctrl_3 = RTMDIO_C45_DATA(devnum, regnum),
|
||||
struct rtmdio_command_data cmd_data = {
|
||||
.c45_adr = RTMDIO_C45_DATA(devnum, regnum),
|
||||
.io_data = val,
|
||||
.mask_lo = BIT(pn),
|
||||
};
|
||||
|
||||
return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C45, &smi_access, NULL);
|
||||
return rtmdio_run_cmd(bus, RTMDIO_930X_CMD_WRITE_C45, &cmd_data, NULL);
|
||||
}
|
||||
|
||||
static int rtmdio_931x_read_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 *val)
|
||||
{
|
||||
struct rtmdio_931x_smi_access smi_access = {
|
||||
.ctrl_0 = RTMDIO_931X_C22_DATA(page, reg),
|
||||
.b_ctrl = pn << 5,
|
||||
struct rtmdio_command_data cmd_data = {
|
||||
.brdcast = RTMDIO_931X_SMI_INDRT_PORT(pn),
|
||||
.c22_adr = RTMDIO_931X_C22_DATA(page, reg),
|
||||
};
|
||||
|
||||
return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_READ_C22, &smi_access, val);
|
||||
return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_READ_C22, &cmd_data, val);
|
||||
}
|
||||
|
||||
static int rtmdio_931x_write_c22(struct mii_bus *bus, u32 pn, u32 page, u32 reg, u32 val)
|
||||
{
|
||||
struct rtmdio_931x_smi_access smi_access = {
|
||||
.ctrl_0 = RTMDIO_931X_C22_DATA(page, reg),
|
||||
.ctrl_2 = (u32)(BIT_ULL(pn)),
|
||||
.ctrl_x = (u32)(BIT_ULL(pn) >> 32),
|
||||
.ctrl_3 = val,
|
||||
struct rtmdio_command_data cmd_data = {
|
||||
.c22_adr = RTMDIO_931X_C22_DATA(page, reg),
|
||||
.mask_lo = (u32)(BIT_ULL(pn)),
|
||||
.mask_hi = (u32)(BIT_ULL(pn) >> 32),
|
||||
.io_data = val,
|
||||
};
|
||||
|
||||
return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_WRITE_C22, &smi_access, NULL);
|
||||
return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_WRITE_C22, &cmd_data, NULL);
|
||||
}
|
||||
|
||||
static int rtmdio_931x_read_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 *val)
|
||||
{
|
||||
struct rtmdio_931x_smi_access smi_access = {
|
||||
.b_ctrl = pn << 5,
|
||||
.m_ctrl = RTMDIO_C45_DATA(devnum, regnum),
|
||||
struct rtmdio_command_data cmd_data = {
|
||||
.brdcast = RTMDIO_931X_SMI_INDRT_PORT(pn),
|
||||
.c45_adr = RTMDIO_C45_DATA(devnum, regnum),
|
||||
};
|
||||
|
||||
return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_READ_C45, &smi_access, val);
|
||||
return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_READ_C45, &cmd_data, val);
|
||||
}
|
||||
|
||||
static int rtmdio_931x_write_c45(struct mii_bus *bus, u32 pn, u32 devnum, u32 regnum, u32 val)
|
||||
{
|
||||
struct rtmdio_931x_smi_access smi_access = {
|
||||
.ctrl_2 = (u32)(BIT_ULL(pn)),
|
||||
.ctrl_x = (u32)(BIT_ULL(pn) >> 32),
|
||||
.ctrl_3 = val,
|
||||
.m_ctrl = RTMDIO_C45_DATA(devnum, regnum),
|
||||
struct rtmdio_command_data cmd_data = {
|
||||
.c45_adr = RTMDIO_C45_DATA(devnum, regnum),
|
||||
.mask_lo = (u32)(BIT_ULL(pn)),
|
||||
.mask_hi = (u32)(BIT_ULL(pn) >> 32),
|
||||
.io_data = val,
|
||||
};
|
||||
|
||||
return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_WRITE_C45, &smi_access, NULL);
|
||||
return rtmdio_run_cmd(bus, RTMDIO_931X_CMD_WRITE_C45, &cmd_data, NULL);
|
||||
}
|
||||
|
||||
static int rtmdio_read_c45(struct mii_bus *bus, int phy, int devnum, int regnum)
|
||||
@@ -1096,8 +1098,13 @@ static int rtmdio_probe(struct platform_device *pdev)
|
||||
|
||||
static const struct rtmdio_config rtmdio_838x_cfg = {
|
||||
.cmd_fail = RTMDIO_838X_CMD_FAIL,
|
||||
.cmd_mask = RTMDIO_838X_CMD_MASK,
|
||||
.cmd_reg = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1,
|
||||
.cmd_io_shift = RTMDIO_DATA_IN_HI_OUT_LOW,
|
||||
.cmd_regs = {
|
||||
.c22_adr = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1,
|
||||
.c45_adr = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3,
|
||||
.mask_lo = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0,
|
||||
.io_data = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2,
|
||||
},
|
||||
.num_busses = RTMDIO_838X_NUM_BUSSES,
|
||||
.num_pages = RTMDIO_838X_NUM_PAGES,
|
||||
.num_ports = RTMDIO_838X_NUM_PORTS,
|
||||
@@ -1105,38 +1112,43 @@ static const struct rtmdio_config rtmdio_838x_cfg = {
|
||||
.port_map_base = RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL,
|
||||
.read_c22 = rtmdio_838x_read_c22,
|
||||
.read_c45 = rtmdio_838x_read_c45,
|
||||
.ret_mask = GENMASK(15, 0),
|
||||
.ret_reg = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2,
|
||||
.setup_ctrl = rtmdio_838x_setup_ctrl,
|
||||
.setup_polling = rtmdio_838x_setup_polling,
|
||||
.smi_base = RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0,
|
||||
.smi_size = sizeof(struct rtmdio_838x_smi_access),
|
||||
.write_c22 = rtmdio_838x_write_c22,
|
||||
.write_c45 = rtmdio_838x_write_c45,
|
||||
};
|
||||
|
||||
static const struct rtmdio_config rtmdio_839x_cfg = {
|
||||
.cmd_fail = RTMDIO_839X_CMD_FAIL,
|
||||
.cmd_mask = RTMDIO_839X_CMD_MASK,
|
||||
.cmd_reg = RTMDIO_839X_PHYREG_ACCESS_CTRL,
|
||||
.cmd_io_shift = RTMDIO_DATA_IN_HI_OUT_LOW,
|
||||
.cmd_regs = {
|
||||
.brdcast = RTMDIO_839X_BCAST_PHYID_CTRL,
|
||||
.c22_adr = RTMDIO_839X_PHYREG_ACCESS_CTRL,
|
||||
.c45_adr = RTMDIO_839X_PHYREG_MMD_CTRL,
|
||||
.ex_page = RTMDIO_839X_PHYREG_CTRL,
|
||||
.mask_lo = RTMDIO_839X_PHYREG_PORT_CTRL(0),
|
||||
.mask_hi = RTMDIO_839X_PHYREG_PORT_CTRL(1),
|
||||
.io_data = RTMDIO_839X_PHYREG_DATA_CTRL,
|
||||
},
|
||||
.num_busses = RTMDIO_839X_NUM_BUSSES,
|
||||
.num_pages = RTMDIO_839X_NUM_PAGES,
|
||||
.num_ports = RTMDIO_839X_NUM_PORTS,
|
||||
.poll_ctrl = RTMDIO_839X_SMI_PORT_POLLING_CTRL,
|
||||
.read_c22 = rtmdio_839x_read_c22,
|
||||
.read_c45 = rtmdio_839x_read_c45,
|
||||
.ret_mask = GENMASK(15, 0),
|
||||
.ret_reg = RTMDIO_839X_PHYREG_DATA_CTRL,
|
||||
.smi_base = RTMDIO_839X_PHYREG_ACCESS_CTRL,
|
||||
.smi_size = sizeof(struct rtmdio_839x_smi_access),
|
||||
.write_c22 = rtmdio_839x_write_c22,
|
||||
.write_c45 = rtmdio_839x_write_c45,
|
||||
};
|
||||
|
||||
static const struct rtmdio_config rtmdio_930x_cfg = {
|
||||
.cmd_fail = RTMDIO_930X_CMD_FAIL,
|
||||
.cmd_mask = RTMDIO_930X_CMD_MASK,
|
||||
.cmd_reg = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1,
|
||||
.cmd_io_shift = RTMDIO_DATA_IN_HI_OUT_LOW,
|
||||
.cmd_regs = {
|
||||
.c22_adr = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1,
|
||||
.c45_adr = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3,
|
||||
.mask_lo = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0,
|
||||
.io_data = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2,
|
||||
},
|
||||
.bus_map_base = RTMDIO_930X_SMI_PORT0_15_POLLING_SEL,
|
||||
.num_busses = RTMDIO_930X_NUM_BUSSES,
|
||||
.num_pages = RTMDIO_930X_NUM_PAGES,
|
||||
@@ -1145,20 +1157,24 @@ static const struct rtmdio_config rtmdio_930x_cfg = {
|
||||
.port_map_base = RTMDIO_930X_SMI_PORT0_5_ADDR_CTRL,
|
||||
.read_c22 = rtmdio_930x_read_c22,
|
||||
.read_c45 = rtmdio_930x_read_c45,
|
||||
.ret_mask = GENMASK(15, 0),
|
||||
.ret_reg = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2,
|
||||
.setup_ctrl = rtmdio_930x_setup_ctrl,
|
||||
.setup_polling = rtmdio_930x_setup_polling,
|
||||
.smi_base = RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0,
|
||||
.smi_size = sizeof(struct rtmdio_930x_smi_access),
|
||||
.write_c22 = rtmdio_930x_write_c22,
|
||||
.write_c45 = rtmdio_930x_write_c45,
|
||||
};
|
||||
|
||||
static const struct rtmdio_config rtmdio_931x_cfg = {
|
||||
.cmd_fail = RTMDIO_931X_CMD_FAIL,
|
||||
.cmd_mask = RTMDIO_931X_CMD_MASK,
|
||||
.cmd_reg = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0,
|
||||
.cmd_io_shift = RTMDIO_DATA_IN_LOW_OUT_HI,
|
||||
.cmd_regs = {
|
||||
.brdcast = RTMDIO_931X_SMI_INDRT_ACCESS_BC,
|
||||
.c22_adr = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0,
|
||||
.c45_adr = RTMDIO_931X_SMI_INDRT_ACCESS_MMD,
|
||||
.ex_page = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1,
|
||||
.mask_lo = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2(0),
|
||||
.mask_hi = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2(1),
|
||||
.io_data = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3,
|
||||
},
|
||||
.bus_map_base = RTMDIO_931X_SMI_PORT_POLLING_SEL,
|
||||
.num_busses = RTMDIO_931X_NUM_BUSSES,
|
||||
.num_pages = RTMDIO_931X_NUM_PAGES,
|
||||
@@ -1167,12 +1183,8 @@ static const struct rtmdio_config rtmdio_931x_cfg = {
|
||||
.port_map_base = RTMDIO_931X_SMI_PORT_ADDR_CTRL,
|
||||
.read_c22 = rtmdio_931x_read_c22,
|
||||
.read_c45 = rtmdio_931x_read_c45,
|
||||
.ret_mask = GENMASK(31, 16),
|
||||
.ret_reg = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3,
|
||||
.setup_ctrl = rtmdio_931x_setup_ctrl,
|
||||
.setup_polling = rtmdio_931x_setup_polling,
|
||||
.smi_base = RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0,
|
||||
.smi_size = sizeof(struct rtmdio_931x_smi_access),
|
||||
.write_c22 = rtmdio_931x_write_c22,
|
||||
.write_c45 = rtmdio_931x_write_c45,
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user