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realtek: add support for Ubiquiti USW Pro XG 10 PoE
Add support for RTL9313-based Ubiquiti UniFi USW Pro XG 10 PoE switch
with 10x 10G RJ45 and 2x SFP+ ports.
Hardware
========
- RTL9313 switch SoC
- 512 MiB RAM
- 32 MiB SPI-NOR flash
- 10x 100M/1G/2.5G/5G/10G RJ45 ports via RTL8264B and RTL8261BE
- PoE: 10x 802.3bt, 90W per port, 400W total budget
- 2x 1G/2.5G/10G SFP+ ports
- Buttons: 1x Reset
- LEDs:
- System LED white/blue
- RGBW LED per port
- Console: TTL 3.3V, 115200 8N1, populated 4-pin header J19,
front to back: VCC, RX, TX and GND
(device must be opened to access header)
- Etherlighting feature (lighting patterns and color control)
- Vendor firmware: U-Boot + LEDE-based Ubiquiti OS
MAC address
===========
Single MAC address in EEPROM partition, applied to all ports.
Known issues
============
- Etherlighting not controllable, driver WIP. Port LEDs for link work
though. By default, the controller keeps the LEDs in a breathing
state, gated by the link state delivered by the Realtek SoC.
Disclaimer
==========
Stock firmware uses a dual-bank layout (kernel0/kernel1, ~15 MiB each).
OpenWrt replaces both banks with a single contiguous firmware partition.
Flashing OpenWrt overwrites both stock kernel slots; U-Boot remains
intact and can be used for recovery.
Installation
============
1. Enable SSH on the stock UniFi OS and log in with user account.
(at this stage you may make backups of the flash, just to be sure)
2. Copy the OpenWrt sysupgrade image to /tmp on the switch (e.g. via
scp).
3. Adjust IMG below to point at the copied file, then run the block as a
whole. It writes kernel0, splits into kernel1 if the image is larger
than that slot (otherwise invalidates kernel1 so U-Boot cannot pick
a stale bank), and reboots:
IMG=/tmp/openwrt-realtek-rtl931x-ubnt_usw-pro-xg-10-poe-squashfs-sysupgrade.bin
K0_BLOCKS=$((0xec0000 / 0x10000))
dd if="$IMG" of=/dev/mtdblock2 bs=64k count=$K0_BLOCKS conv=fsync
if [ "$(wc -c < "$IMG")" -gt $((0xec0000)) ]; then
dd if="$IMG" of=/dev/mtdblock3 bs=64k skip=$K0_BLOCKS conv=fsync
else
dd if=/dev/zero of=/dev/mtdblock3 bs=64k count=1 conv=fsync
fi
sync
reboot
Then it comes up in OpenWrt.
You may also install the image in any other way, just make sure to
write it to the kernel0 partition and if the image is larger than
15,104 kiB, write the rest to the kernel1 partition, otherwise invalidate
it so U-Boot cannot boot from the second bank.
4. It is recommended to modify the bootcmd to speedup the boot and prevent
any issues due to the dual-boot selection. Since U-Boot by default
uses bootubnt which does a lot of (unneeded) RTK initialization,
quite some time passes until Linux is started. Additionally, the
U-boot logic fiddles with some bits on flash which causes JFFS2
errors in OpenWrt. While this doesn't seem to cause issues yet, be
defensive and set the bootcmd to:
bootm 0xb4150000
This directly boots the uImage from flash, without doing all the
initialization. OpenWrt is able to bootstrap the networking completely
on its own.
It does not matter which bank stock booted from when the dd block
runs: both banks are touched in the same pass (kernel0 written, kernel1
either written or invalidated). With kernel1 invalidated, U-Boot's
internal fallback kicks in and permanently switches to kernel0 on the
next boot, so the device stays on OpenWrt as long as kernel0 is
bootable.
Recovery
========
Since the installation procedure invalidates or partially overwrites
the second bank, recovery requires serial console access (see Hardware
above for pinout).
1. Interrupt U-Boot autoboot by spamming the Escape key during early
boot to drop into the U-Boot prompt.
2. Bring up networking:
rtk network on
3. Transfer an OpenWrt initramfs image via TFTP and boot it:
setenv ipaddr <switch-ipaddr>
setenv serverip <tftpserver-ipaddr>
setenv bootfile openwrt-realtek-rtl931x-ubnt_usw-pro-xg-10-poe-initramfs-kernel.bin
tftpboot
bootm
4. From the running initramfs OpenWrt, do a sysupgrade to reflash
OpenWrt or whatever you want to recover. There is no need for the
complicated procedure from installation since OpenWrt sees the
firmware partition already as a whole.
Return to stock firmware
========================
There is no fully-supported revert path. The stock firmware blob is a
Ubiquiti UBNT archive (header + parts, see firmware-utils' fw.h) that
embeds a u-boot and a kernel0 uImage payload; only the latter is
relevant when writing back to the kernel partitions.
The snippet below extracts the kernel0 uImage from such a blob by
locating the uImage offset and size using binwalk. It is provided as a
best-effort starting point; verify the result before flashing,
otherwise you're on your own:
BLOB=US3.rtl93xx_7.4.1+X.Y.Z.bin
binwalk $BLOB | grep uImage > uimage-info.txt
OFF=$(cut -d\ -f1 uimage-info.txt)
SIZE=$(sed -nE 's/^.*image size: ([0-9]+) bytes,.*/\1/p' uimage-info.txt)
dd if="$BLOB" of=kernel0.uImage bs=1 skip="$OFF" count="$SIZE"
Once you have a clean uImage, it can be written to the kernel partition
from within OpenWrt. If you adjusted the bootcmd during installation,
make sure to restore it to the default "bootcmd=bootubnt". After a reboot,
Ubiquiti's firmware should boot.
Or, if you did backups of the flash before, just write the backup to the
flash.
(lightly modified from Jonas commit adding support for usw-pro-8-poe)
Signed-off-by: Russell Senior <russell@personaltelco.net>
Link: https://github.com/openwrt/openwrt/pull/25425
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
This commit is contained in:
Russell Senior authored and 
Jonas Jelonek committed
1 parent
7a29a6bf6b
commit
8635eeedc3
3 files changed
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@@ -103,6 +103,7 @@ realtek_setup_macs()
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sirivision,sr-st3808f|\
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sirivision,sr-st31212f|\
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ubnt,usw-pro-max-24-poe|\
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ubnt,usw-pro-xg-10-poe|\
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ubnt,usw-pro-xg-8-poe|\
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zyxel,gs1920-24-v1|\
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zyxel,gs1920-24hp-v2)
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@@ -0,0 +1,343 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl931x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/mux/mux.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "ubnt,usw-pro-xg-10-poe", "realtek,rtl9313-soc";
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model = "UniFi USW Pro XG 10 PoE";
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aliases {
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label-mac-device = ðernet0;
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led-boot = &led_sys_white;
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led-failsafe = &led_sys_white;
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led-running = &led_sys_blue;
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led-upgrade = &led_sys_white;
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};
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chosen {
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bootargs = "console=ttyS0,115200 earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>, /* first 256 MiB */
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<0x90000000 0x10000000>; /* remaining 256 MiB */
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};
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keys {
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compatible = "gpio-keys";
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key-reset {
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label = "reset";
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gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds: leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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led_sys_blue: led-0 {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_INDICATOR;
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gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
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};
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led_sys_white: led-1 {
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color = <LED_COLOR_ID_WHITE>;
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function = LED_FUNCTION_INDICATOR;
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gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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};
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};
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led_set: led_set@0 {
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compatible = "realtek,rtl9300-leds";
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clock-frequency = <1250000>;
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active-low;
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/*
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* selects all speed modes to trigger a LED, two slots. This doesn't correspond
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* fully to actual LED behavior. The serial stream is fed into the Etherlighting
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* MCU which translates that into the LEDs, managing color, behavior etc. in
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* addition.
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*/
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led_set0 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_5G | RTL93XX_LED_SET_2P5G |
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RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_5G | RTL93XX_LED_SET_2P5G |
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RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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};
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sfp1: sfp-p1 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp1>;
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los-gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio2 2 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
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};
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sfp2: sfp-p2 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp2>;
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los-gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x140000>;
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read-only;
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};
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partition@140000 {
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label = "u-boot-env";
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reg = <0x140000 0x10000>;
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};
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/*
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* Vendor layout has two kernel partitions:
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* (1) <0x150000 0xec0000> = "kernel0"
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* (2) <0x1010000 0xed0000> = "kernel1"
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*/
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partition@150000 {
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label = "firmware";
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reg = <0x150000 0x1d90000>;
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compatible = "openwrt,uimage", "denx,uimage";
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};
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partition@1ee0000 {
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label = "cdata";
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reg = <0x1ee0000 0x10000>;
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read-only;
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};
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partition@1ef0000 {
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label = "cfg";
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reg = <0x1ef0000 0x100000>;
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read-only;
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};
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partition@1ff0000 {
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label = "EEPROM";
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reg = <0x1ff0000 0x10000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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factory_macaddr: macaddr@0 {
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compatible = "mac-base";
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reg = <0x0 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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};
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};
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};
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ðernet0 {
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nvmem-cells = <&factory_macaddr 0>;
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nvmem-cell-names = "mac-address";
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};
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&gpio0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_jtag>;
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/*
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* GPIO 1 is the global reset pin shared by all PHYs across all MDIO
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* buses. It is intentionally not declared as reset-gpios on any bus:
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* the MDIO driver / phylink only support a reset GPIO per bus, not on
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* the parent controller. Attaching it to a single bus would still reset
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* the PHYs on the other buses as a side effect, leaving their software
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* state out of sync with the hardware and likely breaking them.
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*/
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phy_reset_hog {
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "phy-reset";
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};
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};
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&i2c_mst1 {
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status = "okay";
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i2c_sfp1: i2c@0 { reg = <0>; };
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i2c_sfp2: i2c@1 { reg = <1>; };
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i2c7: i2c@7 { reg = <7>; }; /* Etherlighting MCU at 0x66 */
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i2c8: i2c@8 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <8>;
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adt7475@2e {
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compatible = "adi,adt7475";
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reg = <0x2e>;
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};
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};
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};
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&i2c_mst2 {
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status = "okay";
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i2c5: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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gpio1: gpio@22 {
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compatible = "nxp,pca9555";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: gpio@24 {
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compatible = "nxp,pca9555";
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reg = <0x24>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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i2c_poe: i2c@6 {
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reg = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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pse: ethernet-pse@20 {
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compatible = "ubnt,usw-pro-xg-10-poe-pse", "realtek,pse-mcu-gen2-smbus";
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reg = <0x20>;
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reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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pse-pis {
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#address-cells = <1>;
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#size-cells = <0>;
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PSE_PI(0)
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PSE_PI(1)
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PSE_PI(2)
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PSE_PI(3)
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PSE_PI(4)
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PSE_PI(5)
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PSE_PI(6)
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PSE_PI(7)
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PSE_PI(8)
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PSE_PI(9)
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};
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};
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};
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};
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&mdio_ctrl {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_enable_mdc_mdio_0>,
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<&pinmux_enable_mdc_mdio_1>;
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};
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&mdio_bus0 {
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/* RTL8264B */
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ethernet-phy-package@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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PHY_C45(0, 0)
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PHY_C45(8, 1)
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PHY_C45(16, 2)
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PHY_C45(24, 3)
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};
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/* RTL8264B */
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ethernet-phy-package@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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PHY_C45(32, 4)
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PHY_C45(40, 5)
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PHY_C45(48, 6)
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PHY_C45(50, 7)
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};
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};
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&mdio_bus1 {
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PHY_C45(52, 0)
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PHY_C45(53, 1)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii)
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SWITCH_PORT_LED(8, 2, 3, 0, 0, usxgmii)
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SWITCH_PORT_LED(16, 3, 4, 0, 0, usxgmii)
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SWITCH_PORT_LED(24, 4, 5, 0, 0, usxgmii)
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SWITCH_PORT_LED(32, 5, 6, 0, 0, usxgmii)
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SWITCH_PORT_LED(40, 6, 7, 0, 0, usxgmii)
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SWITCH_PORT_LED(48, 7, 8, 0, 0, usxgmii)
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SWITCH_PORT_LED(50, 8, 9, 0, 0, usxgmii)
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SWITCH_PORT_LED(52, 9, 10, 0, 0, usxgmii)
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SWITCH_PORT_LED(53, 10, 11, 0, 0, usxgmii)
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SWITCH_PORT_SFP(54, 11, 12, 0, 1)
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SWITCH_PORT_SFP(55, 12, 13, 0, 2)
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/* CPU port */
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port@56 {
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ethernet = <ðernet0>;
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reg = <56>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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&phy0 { pses = <&pse_pi0>; };
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&phy8 { pses = <&pse_pi1>; };
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&phy16 { pses = <&pse_pi2>; };
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&phy24 { pses = <&pse_pi3>; };
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&phy32 { pses = <&pse_pi4>; };
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&phy40 { pses = <&pse_pi5>; };
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&phy48 { pses = <&pse_pi6>; };
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&phy50 { pses = <&pse_pi7>; };
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&phy52 { pses = <&pse_pi8>; };
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&phy53 { pses = <&pse_pi9>; };
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@@ -76,6 +76,16 @@ define Device/sirivision_sr-st31212f
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endef
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TARGET_DEVICES += sirivision_sr-st31212f
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define Device/ubnt_usw-pro-xg-10-poe
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SOC := rtl9313
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DEVICE_VENDOR := Ubiquiti
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DEVICE_MODEL := UniFi USW Pro XG 10 PoE
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IMAGE_SIZE := 30272k
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DEVICE_PACKAGES := rtl826x-firmware kmod-hwmon-adt7475 kmod-pse-realtek-mcu-i2c
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$(Device/kernel-lzma)
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endef
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TARGET_DEVICES += ubnt_usw-pro-xg-10-poe
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define Device/ubnt_usw-pro-xg-8-poe
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SOC := rtl9313
|
||||
DEVICE_VENDOR := Ubiquiti
|
||||
|
||||
Reference in new issue
Block a user