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qualcommax: qca_ppe: add tc-flower and ethtool n-tuple ACL offload
The ACL engine has 512 entries, and the driver uses two at fixed indices with no way to install a rule from userspace. Add an allocator that places a rule on the entry chains the hardware can merge, with range compares on even entries, move the two small-packet rules onto it, and implement cls_flower_add and cls_flower_del for MAC, IPv4, IPv6, L4 port and port range, ICMP, IP protocol, DSCP, TCP flag and fragment keys, refusing any other key. The actions are pass, drop, trap, skbedit priority, redirect, mirred mirror, which claims both of the port mirror's analyzers, pedit of the DSCP byte and police on one of the 512 ACL meters, and set_rxnfc gives ethtool -N the queue action, refusing queues 12 to 143, the CPU port queues the scheduler does not serve, and a VF or RSS context, which the switch does not have. The engine matches the highest PRI, so a rule's priority is the 9-bit span minus its tc preference. The address family comes from the control key, since cls_flower registers both address keys over one union, and from the registered address key where ethtool_rx_flow_rule_create() leaves the control key out. On IPQ8074 every accepted action installs in_hw, an ICMP drop filter drops in the switch, and a pedit to 0x88 moves the datagrams to another egress queue. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/25700 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Julius Bairaktaris authored and 
Robert Marko committed
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6 files changed
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@@ -271,39 +271,95 @@
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#define PPE_RSS_HASH_MIX_IPV4(i) (0x0b0000 + 0x4390 + (i) * 0x4)
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#define PPE_RSS_HASH_FIN_IPV4(i) (0x0b0000 + 0x43b0 + (i) * 0x4)
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/* --- ACL (rules in the IPO block, actions beside the L2 tables) ---
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* A rule, its mask and its action share one flat index. A rule whose RANGE_EN
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* is set must sit at an even index. There is no valid bit and no global
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* enable: a rule with an empty source bitmap matches nothing, one with ports
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* in it is live.
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/* --- ACL: rules and masks in the IPO block, actions beside the L2 tables,
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* hit counters in the ingress policer ---
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* A rule, its mask and its action share one flat index. The 512 indices are
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* 64 hardware lists of eight: a rule whose key is wider than one entry takes
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* several entries of one list and the list's RULE_EXT bits merge them into a
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* single match. A rule whose RANGE_EN is set compares one of its fields
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* against a range - that field's mask slot carries the maximum, the rest of
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* the mask stays a mask - and must sit at an even index. There is no valid
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* bit and no global enable: a rule with an empty source bitmap matches
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* nothing, one with ports in it is live.
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*/
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#define PPE_ACL_LISTS 64
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#define PPE_ACL_LIST_ENTRIES 8
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#define PPE_ACL_RULE(i) (0x0b0000 + (i) * 0x10)
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/* 3 implemented words in a 4-word slot; whole slots are written so the
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* latch on the slot's last word always fires (same for the mask below).
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* Words 0 and 1 carry a 53-bit key whose fields belong to the rule type.
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*/
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#define PPE_ACL_RULE_WORDS 4
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#define PPE_ACL_L3_LEN GENMASK(15, 0) /* word 0; range min */
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#define PPE_ACL_IS_IPV6 BIT(17) /* word 1 */
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#define PPE_ACL_RANGE_EN BIT(21) /* word 1 */
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#define PPE_ACL_RULE_TYPE GENMASK(26, 23) /* word 1 */
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#define PPE_ACL_MAC_HI GENMASK(15, 0) /* w1: bytes 1-0 */
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#define PPE_ACL_IP_PORT GENMASK(15, 0) /* w0: L4 or ICMP */
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#define PPE_ACL_IP_LO GENMASK(31, 16) /* w0 */
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#define PPE_ACL_IP_HI GENMASK(15, 0) /* w1 */
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#define PPE_ACL_L3_LEN GENMASK(15, 0) /* w0; range min */
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#define PPE_ACL_L3_PROT GENMASK(23, 16) /* w0 */
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#define PPE_ACL_L3_DSCP GENMASK(31, 24) /* w0 */
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#define PPE_ACL_TCP_FLAGS GENMASK(6, 1) /* w1 */
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#define PPE_ACL_L3_FRAG BIT(16) /* w1 */
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#define PPE_ACL_IS_IPV6 BIT(17) /* w1 */
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#define PPE_ACL_RANGE_EN BIT(21) /* w1 */
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#define PPE_ACL_RULE_TYPE GENMASK(26, 23) /* w1 */
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#define PPE_ACL_TYPE_MAC_DA 0
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#define PPE_ACL_TYPE_MAC_SA 1
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#define PPE_ACL_TYPE_IPV4_DIP 4
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#define PPE_ACL_TYPE_IPV4_SIP 5
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#define PPE_ACL_TYPE_IPV6_DIP0 6 /* +1, +2 for the rest */
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#define PPE_ACL_TYPE_IPV6_SIP0 9
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#define PPE_ACL_TYPE_IPMISC 12
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#define PPE_ACL_SRC_LO GENMASK(31, 29) /* word 1: ports 0-2 */
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#define PPE_ACL_SRC_HI GENMASK(4, 0) /* word 2: ports 3-7 */
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#define PPE_ACL_SRC_TYPE GENMASK(28, 27) /* w1 */
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#define PPE_ACL_SRC_PORT_BMP 0
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#define PPE_ACL_SRC_LO GENMASK(31, 29) /* w1: ports 0-2 */
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#define PPE_ACL_SRC_HI GENMASK(4, 0) /* w2: ports 3-7 */
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#define PPE_ACL_RULE_PRI GENMASK(13, 5) /* w2 */
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#define PPE_ACL_MASK(i) (0x0b2000 + (i) * 0x10)
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#define PPE_ACL_MASK_WORDS 4 /* 2 implemented; same field layout
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* as the rule, and under RANGE_EN
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* the length field carries the
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* range max
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* the ranged field's slot carries
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* its maximum
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*/
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/* One register per hardware list, one bit per mergeable pair of its entries:
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* EXT1 merges (0,1) (2,3) (4,5) (6,7), EXT2 merges (0,2) (4,6), EXT4 (0,4).
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* No other pairing exists, which is what limits a wide rule's placement.
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*/
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#define PPE_ACL_RULE_EXT1(l) (0x0b4000 + (l) * 0x4)
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#define PPE_ACL_RULE_EXT2(l) (0x0b4100 + (l) * 0x4)
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#define PPE_ACL_RULE_EXT4(l) (0x0b4200 + (l) * 0x4)
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#define PPE_ACL_ACTION(i) (0x068000 + (i) * 0x20)
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/* 5 implemented words in an 8-word slot; the entry latches on the write to
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* the slot's last word, so all 8 are written.
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*/
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#define PPE_ACL_ACTION_WORDS 8
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#define PPE_ACL_DEST_CHANGE_EN BIT(0) /* word 0 */
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#define PPE_ACL_FWD_CMD GENMASK(2, 1) /* word 0 */
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#define PPE_ACL_FWD_FORWARD 0
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#define PPE_ACL_FWD_DROP 1
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#define PPE_ACL_FWD_RDT_CPU 3
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/* The destination that replaces the one the lookup found: a twelve-bit
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* value under a two-bit type.
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*/
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#define PPE_ACL_DEST_VALUE GENMASK(14, 3) /* word 0 */
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#define PPE_ACL_DEST_TYPE GENMASK(16, 15) /* word 0 */
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#define PPE_ACL_DEST_PORT_BMP 3
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#define PPE_ACL_MIRROR_EN BIT(17) /* word 0 */
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#define PPE_ACL_DSCP_TC_CHANGE_EN BIT(14) /* word 2 */
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#define PPE_ACL_DSCP_TC GENMASK(22, 15) /* word 2 */
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#define PPE_ACL_PRI_CHANGE_EN BIT(3) /* word 3 */
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#define PPE_ACL_PRI GENMASK(7, 4) /* word 3 */
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#define PPE_ACL_POLICER_EN BIT(11) /* word 3 */
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#define PPE_ACL_POLICER_INDEX GENMASK(20, 12) /* word 3 */
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#define PPE_ACL_QID_EN BIT(21) /* word 3 */
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#define PPE_ACL_QID GENMASK(29, 22) /* word 3 */
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/* The counters live in the ingress policer block, not the IPO: the vendor
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* reaches them at its 0x100000 base plus the table's own 0x74000. Packets in
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* word 0, the low 32 bits of the byte count in word 1, its top 8 in word 2.
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*/
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#define PPE_ACL_CNT(i) (0x174000 + (i) * 0x10)
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#define PPE_ACL_CNT_ENTRIES 512
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#define PPE_ACL_CNT_WORDS 3
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/* Read-only, and counting whether or not any rule is installed. */
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#define PPE_ACL_GLB_HIT_CNT (0x0b0000 + 0x430c)
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#define PPE_ACL_GLB_MISS_CNT (0x0b0000 + 0x4310)
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@@ -466,6 +522,29 @@
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#define PPE_POLICER_TIME_SLOT (PPE_POLICER_BASE + 0x40)
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#define PPE_POLICER_SLOT_TIME GENMASK(9, 0)
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/* The refresh period every meter in the block shares, in units of 8 PPE
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* clocks, as ppe_rate_limit_init programs it.
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*/
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#define PPE_POLICER_SLOT 600
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/* One meter per classifier rule, bound by the rule's action. The fields are
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* the port meter's in a different order and without its frame-type filter,
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* and the two words past the rate carry the exceed and violate actions: left
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* at zero, a violation drops.
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*/
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#define PPE_ACL_METER(i) (PPE_POLICER_BASE + 0x4000 + (i) * 0x10)
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#define PPE_ACL_METER_ENTRIES 512
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#define PPE_ACL_METER_EN BIT(0) /* word 0 */
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#define PPE_ACL_METER_MODE BIT(3) /* word 0 */
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#define PPE_ACL_METER_TOKEN_UNIT GENMASK(6, 4) /* word 0 */
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#define PPE_ACL_METER_CBS GENMASK(23, 8) /* word 0 */
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#define PPE_ACL_METER_CIR_LO GENMASK(31, 24) /* word 0 */
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#define PPE_ACL_METER_CIR_HI GENMASK(9, 0) /* word 1 */
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/* The meter's token buckets, committed and excess, two words that commit on
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* the second - the port meter's table one block over, per meter index.
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*/
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#define PPE_ACL_METER_CRDT(i) (PPE_POLICER_BASE + 0x8000 + (i) * 0x10)
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#define PPE_PORT_METER_W0(p) (PPE_POLICER_BASE + 0xc000 + (p) * 0x10)
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#define PPE_METER_EN BIT(0)
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@@ -701,6 +780,10 @@
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#define PPE_MAX_SP_PRI 8
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#define PPE_L0_QUEUES 300
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#define PPE_L0_UCAST_QUEUES 256
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/* The CPU port's unicast queues the L0 scheduler serves (l0_port0[]). */
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#define PPE_CPU_UCAST_QUEUES 12
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/* First unicast queue of a user port. */
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#define PPE_PORT_UCAST_BASE 144
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#define PPE_BM_BUF_SIZE 256
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#define PPE_BM_PORTS 15
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@@ -825,6 +908,14 @@ struct qca_ppe_priv {
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* holds none.
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*/
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struct mutex vlan_lock;
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/* Free entries of every ACL hardware list. Guarded by its own lock
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* because the small-packet module parameters reach the table from a
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* writer that holds no rtnl.
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*/
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u8 acl_free[PPE_ACL_LISTS];
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DECLARE_BITMAP(acl_meter_used, PPE_ACL_METER_ENTRIES);
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struct list_head acl_rules;
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struct mutex acl_lock;
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/* Indexed by direction: egress 0, ingress 1. */
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u8 mirror_port[2];
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u16 mirror_ref[2];
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@@ -907,6 +998,7 @@ struct tc_ets_qopt_offload;
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struct tc_prio_qopt_offload;
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struct tc_query_caps_base;
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struct tc_mqprio_qopt_offload;
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struct flow_cls_offload;
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void ppe_scheduler_init(struct qca_ppe_priv *priv);
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int qca_ppe_setup_tc(struct dsa_switch *ds, int port, enum tc_setup_type type,
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@@ -938,6 +1030,8 @@ int qca_ppe_port_policer_add(struct dsa_switch *ds, int port,
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const struct flow_action_police *policer,
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struct netlink_ext_ack *extack);
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void qca_ppe_port_policer_del(struct dsa_switch *ds, int port);
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int ppe_token_bucket(unsigned long clk, u32 slot, u64 rate_bps, u32 burst,
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u32 cir_max, u32 cbs_max, u32 *cir, u32 *cbs);
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int ppe_vsi_alloc(struct qca_ppe_priv *priv);
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void ppe_vsi_free(struct qca_ppe_priv *priv, u32 vsi);
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@@ -959,4 +1053,17 @@ unsigned long ppe_clk_rate(struct qca_ppe_priv *priv);
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void ppe_debugfs_init(struct qca_ppe_priv *priv);
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void ppe_debugfs_exit(struct qca_ppe_priv *priv);
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void ppe_acl_init(struct qca_ppe_priv *priv);
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void ppe_acl_exit(struct qca_ppe_priv *priv);
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int qca_ppe_cls_flower_add(struct dsa_switch *ds, int port,
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struct flow_cls_offload *cls, bool ingress);
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int qca_ppe_cls_flower_del(struct dsa_switch *ds, int port,
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struct flow_cls_offload *cls, bool ingress);
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int qca_ppe_set_rxnfc(struct dsa_switch *ds, int port,
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struct ethtool_rxnfc *nfc);
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int qca_ppe_get_rxnfc(struct dsa_switch *ds, int port,
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struct ethtool_rxnfc *nfc, u32 *rule_locs);
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int ppe_mirror_analyzer_get(struct qca_ppe_priv *priv, int to_port);
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void ppe_mirror_analyzer_put(struct qca_ppe_priv *priv);
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#endif
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File diff suppressed because it is too large.
Load diff
@@ -1952,6 +1952,19 @@ static void ppe_mirror_put(struct qca_ppe_priv *priv, u8 dirs)
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ppe_mirror_analyzer_write(priv);
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}
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/* Which analyzer a classifier rule's mirror uses is not known, so it claims
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* both.
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*/
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int ppe_mirror_analyzer_get(struct qca_ppe_priv *priv, int to_port)
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{
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return ppe_mirror_get(priv, to_port, BIT(0) | BIT(1));
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}
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void ppe_mirror_analyzer_put(struct qca_ppe_priv *priv)
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{
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ppe_mirror_put(priv, BIT(0) | BIT(1));
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}
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int qca_ppe_port_mirror_add(struct dsa_switch *ds, int port,
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struct dsa_mall_mirror_tc_entry *mirror,
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bool ingress, struct netlink_ext_ack *extack)
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@@ -1995,6 +2008,10 @@ void qca_ppe_port_mirror_del(struct dsa_switch *ds, int port,
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static const struct dsa_switch_ops qca_ppe_ops = {
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.port_setup_tc = qca_ppe_setup_tc,
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.cls_flower_add = qca_ppe_cls_flower_add,
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.cls_flower_del = qca_ppe_cls_flower_del,
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.get_rxnfc = qca_ppe_get_rxnfc,
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.set_rxnfc = qca_ppe_set_rxnfc,
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.port_mirror_add = qca_ppe_port_mirror_add,
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.port_mirror_del = qca_ppe_port_mirror_del,
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.port_policer_add = qca_ppe_port_policer_add,
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@@ -2250,19 +2267,24 @@ static int qca_ppe_probe(struct platform_device *pdev)
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ppe_mac_hw_init(priv);
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ppe_ctrlpkt_init(priv);
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ppe_acl_init(priv);
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if (data->type == PPE_TYPE_IPQ6018)
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ppe_ipq6018_mux_setup(priv);
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ret = dsa_register_switch(ds);
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if (ret)
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return ret;
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goto err_acl;
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ppe_debugfs_init(priv);
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platform_set_drvdata(pdev, priv);
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return 0;
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err_acl:
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ppe_acl_exit(priv);
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return ret;
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}
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static void qca_ppe_remove(struct platform_device *pdev)
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@@ -2271,6 +2293,7 @@ static void qca_ppe_remove(struct platform_device *pdev)
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ppe_debugfs_exit(priv);
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dsa_unregister_switch(&priv->ds);
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ppe_acl_exit(priv);
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}
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static const struct ppe_data ipq6018_ppe_data = {
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@@ -1066,7 +1066,6 @@ static void ppe_rss_hash_init(struct qca_ppe_priv *priv)
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* the one that gets programmed, exactly as qca-ssdk picks it.
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*/
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#define PPE_SHAPER_SLOT 8
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#define PPE_POLICER_SLOT 600
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#define PPE_TOKEN_UNIT_MAX 16384
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#define PPE_BUCKET_UNIT 65536
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/* 12 byte inter-packet gap plus the 8 byte preamble and start delimiter: what
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@@ -1083,9 +1082,8 @@ unsigned long ppe_clk_rate(struct qca_ppe_priv *priv)
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return clk_get_rate(priv->ppe_clk);
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}
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static int ppe_token_bucket(unsigned long clk, u32 slot, u64 rate_bps,
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u32 burst, u32 cir_max, u32 cbs_max,
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u32 *cir, u32 *cbs)
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int ppe_token_bucket(unsigned long clk, u32 slot, u64 rate_bps, u32 burst,
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u32 cir_max, u32 cbs_max, u32 *cir, u32 *cbs)
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{
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int sel;
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@@ -21,7 +21,7 @@
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obj-$(CONFIG_QCA7000_UART) += qcauart.o
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qcauart-objs := qca_uart.o
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+obj-$(CONFIG_QCOM_80211AX_PPE) += qca_ppe.o
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+qca_ppe-objs := qca_ppe_main.o qca_ppe_vlan.o qca_ppe_scheduler.o qca_ppe_debugfs.o
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+qca_ppe-objs := qca_ppe_main.o qca_ppe_vlan.o qca_ppe_scheduler.o qca_ppe_debugfs.o qca_ppe_acl.o
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obj-y += emac/
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@@ -17,7 +17,7 @@
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@@ -10,6 +10,7 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
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qcauart-objs := qca_uart.o
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obj-$(CONFIG_QCOM_80211AX_PPE) += qca_ppe.o
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qca_ppe-objs := qca_ppe_main.o qca_ppe_vlan.o qca_ppe_scheduler.o qca_ppe_debugfs.o
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qca_ppe-objs := qca_ppe_main.o qca_ppe_vlan.o qca_ppe_scheduler.o qca_ppe_debugfs.o qca_ppe_acl.o
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+obj-$(CONFIG_QCOM_EDMA) += qca_edma.o
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obj-y += emac/
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