qualcommax: fix gpll0_main clock disable hang on ipq5018

Add upstream patch marking the 'gpll0_main' clock as critical on
IPQ5018 (gcc-ipq5018 driver), backported from upstream commit
33f9cb56cc28 ("clk: qcom: gcc-ipq5018: mark 'gpll0_main' clock as
critical").

During boot the APCS core clock feeding the CPUs can use GPLL0 as
its parent. On some boards (e.g. TP-Link Archer AX55 v1 using the
in-tree DTS since v6.18), the ipq-cmn-pll driver's pm_runtime_put()
call in its probe function asynchronously disables
'gcc_cmn_blk_ahb_clk', which in turn disables 'gpll0_main' as well,
hanging the system until the hardware watchdog restarts the board.

Marking gpll0_main as CLK_IS_CRITICAL fixes the underlying issue
directly in the GCC driver, making the previous workaround in
0191-clk-qcom-ipq-cmn-pll-keep-the-CMN-block-bus-clocks-enabled.patch
unnecessary. Drop that patch, as it addressed the same symptom by
keeping the CMN PLL block's bus clocks permanently enabled via a
devres-managed runtime PM reference instead of fixing the actual
critical clock.

Refresh the context in
0721-clk-gcc-ipq5018-remove-the-unsupported-clk-combinati.patch and
0723-clk-qcom-gcc-ipq5018-fix-uniphy-soft-reset-issue.patch, whose
hunks shifted by 9 lines due to the newly inserted patch.

Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/25386
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Mieczyslaw Nalewaj authored and Robert Marko committed 2026-09-25 11:14:05 +02:00
1 parent d733b2148c
commit bbe5cbb665
4 files changed
+60 -70

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@@ -0,0 +1,57 @@
From 33f9cb56cc28d002511e471be74f8ff241984178 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <j4g8y7@gmail.com>
Date: Fri, 18 Sep 2026 11:27:49 +0200
Subject: clk: qcom: gcc-ipq5018: mark 'gpll0_main' clock as critical
On IPQ5018, the APCS core clock feeds the CPUs. It can use
different clocks as its parent, but during system boot it
utilizes GPLL0.
Under some cicumstances, the 'gpll0_main' clock is getting
disabled during kernel start which results in a system hang
then the hardware watchdog restarts the board after a while.
This can happen when a driver gets a clock in its probe function,
then releases it either directly or by devres cleanup on probe
failure.
For example, since v6.18 the kernel often fails to boot on the
TP-Link Archer AX55 v1 board by using the in-tree dts. In the
failing configuration, the 'ipq-cmn-pll' driver is built into
the kernel and the problem is caused by the pm_runtim_put()
call in the ipq_cmn_pll_clk_probe() function. Due to this call,
runtime pm disables the 'gcc_cmn_blk_ahb_clk' clock asynchronously
which results in disabling 'gpll0_main' as well.
Mark the clock as critical in order to avoid such hangs.
Cc: stable@vger.kernel.org
Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Link: https://lore.kernel.org/r/20260918-ipq5018-mark-gpll0_main-critical-v1-1-fbe8f27a0106@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/clk/qcom/gcc-ipq5018.c | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq5018.c
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -69,6 +69,15 @@ static struct clk_alpha_pll gpll0_main =
.parent_data = gcc_xo_data,
.num_parents = ARRAY_SIZE(gcc_xo_data),
.ops = &clk_alpha_pll_stromer_ops,
+ /*
+ * During system boot, this PLL feeds the CPUs.
+ * Mark it as critical to ensure that CCF does
+ * not disable it, even if there are no active
+ * consumers. This is needed to avoid a system
+ * hang caused by turning off the clock driving
+ * the CPUs.
+ */
+ .flags = CLK_IS_CRITICAL,
},
},
};
@@ -1,67 +0,0 @@
From bd6a3f8a0ee98d465d83863b4e80efcae0b1d24c Mon Sep 17 00:00:00 2001
From: Stanislaw Pal <kuncy7@gmail.com>
Date: Thu, 13 Aug 2026 11:38:12 +0200
Subject: [PATCH] clk: qcom: ipq-cmn-pll: keep the CMN block bus clocks enabled
The probe function takes a runtime PM reference to enable the GCC AHB &
SYS clocks of the CMN PLL block, registers the clocks, and then drops
the reference, letting pm_clk gate both clocks asynchronously a few
milliseconds after probe has returned.
On IPQ5018 that gate races with early-boot activity on the bus and can
hang the SoC: boards die silently right after the CMN PLL probe, before
the next initcall gets to run, and the watchdog resets them. Whether a
given kernel binary survives depends on micro-timing, ranging from an
occasional hang to a 100% reproducible boot loop. The failure has been
reported independently on three boards from three vendors (TP-Link
Archer AX55 v1, GL.iNet GL-B3000, Cudy P5).
Isolation on the Cudy P5 (by Georg Seema) shows the failure is a
matter of timing against boot activity, not a steady-state clock
dependency: the probe completes in ~628 us and the board dies before
the next initcall starts; stretching the end of probe by ~15 ms makes
the same kernel boot reliably; an enabled UNIPHY0 node is what arms
the failure there. The armed configuration differs per board (on the
GL-B3000 the failure persists with UNIPHY0 disabled), and so does the
window: the same 15 ms stretch - or a 2 s one - still dies 8 of 8
boots on the GL-B3000, so a delay is a diagnostic, not a workaround.
Gating the same clocks on an idle, fully booted system is harmless.
The window between the CMN PLL probe and the first reference taken by
any consumer is exactly where the gate lands, so no consumer-side
scheme can cover it.
Take a devres-managed runtime PM reference in probe, so the bus clocks
stay enabled for as long as the driver is bound and the reference is
released again on unbind.
Upstream submission (v4):
https://lore.kernel.org/linux-clk/20260813093351.178419-1-kuncy7@gmail.com/
Fixes: f81715a4c87c ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC")
Signed-off-by: Stanislaw Pal <kuncy7@gmail.com>
Tested-by: Georg Seema <georgseema@gmail.com>
---
drivers/clk/qcom/ipq-cmn-pll.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/drivers/clk/qcom/ipq-cmn-pll.c
+++ b/drivers/clk/qcom/ipq-cmn-pll.c
@@ -433,6 +433,18 @@ static int ipq_cmn_pll_clk_probe(struct
if (ret)
return dev_err_probe(dev, ret, "Failed to add SYS clock\n");
+ /*
+ * Gating the CMN block AHB & SYS clocks is only safe on an idle
+ * system: without this reference the gate lands asynchronously a
+ * few milliseconds after probe, in the middle of the early-boot
+ * probe activity, and on IPQ5018 that races with other bus
+ * traffic and hangs the SoC. Hold the reference for as long as
+ * the driver is bound so that the bus clocks stay enabled.
+ */
+ ret = devm_pm_runtime_get_noresume(dev);
+ if (ret)
+ return ret;
+
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
@@ -15,7 +15,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
--- a/drivers/clk/qcom/gcc-ipq5018.c
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -678,7 +678,7 @@ static const struct freq_tbl ftbl_gmac1_
@@ -687,7 +687,7 @@ static const struct freq_tbl ftbl_gmac1_
F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
@@ -24,7 +24,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
F(125000000, P_UNIPHY_RX, 1, 0, 0),
F(312500000, P_UNIPHY_RX, 1, 0, 0),
{ }
@@ -718,7 +718,7 @@ static const struct freq_tbl ftbl_gmac1_
@@ -727,7 +727,7 @@ static const struct freq_tbl ftbl_gmac1_
F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
F(24000000, P_XO, 1, 0, 0),
F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
@@ -11,7 +11,7 @@ Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/036b
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
--- a/drivers/clk/qcom/gcc-ipq5018.c
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -3648,7 +3648,7 @@ static const struct qcom_reset_map gcc_i
@@ -3657,7 +3657,7 @@ static const struct qcom_reset_map gcc_i
[GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
[GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
[GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },