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realtek: pcs: rtl930x: combine USXGMII/XSGMII config

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Right now, the config sequences for XSGMII and USXGMII have been
stripped down to their essential parts. Still, they have redundancies.
The XSGMII sequences are 99% equal to the generic ANA_10G sequences
(except for a single write which is DFE/LEQ-related and changed during
calibration later anyway), thus we can drop them completely.

The USXGMII sequences contain the same sequences so they can be removed
there too, all being covered by applying the ANA_10G sequence for those
modes too. One different write (register [0x2e, 0x01]) is integrated into
the ANA_10G sequence since testing has shown that the value is either the
default for that register anyway, or set during SDK setup too for 10GR.

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Jonas Jelonek
2026-03-18 15:03:07 +00:00
committed by Robert Marko
parent c9f5723558
commit c1feb4d798
1 changed files with 19 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files
target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
+19 -56
View File
@@ -2760,13 +2760,13 @@ static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_ana_3g_odd[] = {
};
static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_ana_10g_even[] = {
{0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
{0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
{0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400},
{0x2F, 0x01, 0x0300}, {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
{0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4}, {0x2F, 0x0A, 0x7C2F},
{0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840},
{0x2F, 0x14, 0xE008},
{0x2E, 0x00, 0xA668}, {0x2E, 0x01, 0x2088}, {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000},
{0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
{0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
{0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300}, {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF},
{0x2F, 0x05, 0x7F7C}, {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
{0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, {0x2F, 0x10, 0x0020},
{0x2F, 0x11, 0x8840},
};
static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_ana_10g_odd[] = {
@@ -2779,47 +2779,8 @@ static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_ana_10g_odd[] = {
{0x2F, 0x11, 0x8840},
};
static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_xsgmii_even[] =
{
{0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
{0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0484}, {0x2E, 0x13, 0x027F},
{0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400},
{0x2F, 0x01, 0x0300}, {0x2F, 0x02, 0x1017}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
{0x2F, 0x07, 0x8104}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4}, {0x2F, 0x0A, 0x7C2F},
{0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840},
};
static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_xsgmii_odd[] =
{
{0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
{0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0484}, {0x2E, 0x13, 0x027F},
{0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400},
{0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300}, {0x2F, 0x02, 0x1017}, {0x2F, 0x03, 0xFFDF},
{0x2F, 0x05, 0x7F7C}, {0x2F, 0x07, 0x8104}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
{0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, {0x2F, 0x10, 0x0020},
{0x2F, 0x11, 0x8840},
};
static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_usxgmii_sx_even[] =
{
{0x2E, 0x00, 0xA668}, {0x2E, 0x01, 0x2088}, {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000},
{0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0484},
{0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
{0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300}, {0x2F, 0x02, 0x1017}, {0x2F, 0x03, 0xFFDF},
{0x2F, 0x05, 0x7F7C}, {0x2F, 0x07, 0x8104}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
{0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, {0x2F, 0x10, 0x0020},
{0x2F, 0x11, 0x8840},
};
static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_usxgmii_sx_odd[] =
{
{0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
{0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0484}, {0x2E, 0x13, 0x027F},
{0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400},
{0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300}, {0x2F, 0x02, 0x1017}, {0x2F, 0x03, 0xFFDF},
{0x2F, 0x05, 0x7F7C}, {0x2F, 0x07, 0x8104}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
{0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, {0x2F, 0x10, 0x0020},
{0x2F, 0x11, 0x8840},
static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_usxgmii_xsgmii[] = {
{0x2E, 0x12, 0x0484}, {0x2F, 0x02, 0x1017}, {0x2F, 0x07, 0x8104}
};
static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_5g_qsgmii[] =
@@ -2939,6 +2900,8 @@ static int rtpcs_930x_sds_config_hw_mode(struct rtpcs_serdes *sds, enum rtpcs_sd
rtpcs_930x_sds_cfg_ana_3g_odd);
APPLY_EO(sds, is_even_sds, rtpcs_930x_sds_cfg_ana_10g_even,
rtpcs_930x_sds_cfg_ana_10g_odd);
rtpcs_sds_write(sds, 0x2F, 0x14, 0xE008);
break;
case RTPCS_SDS_MODE_2500BASEX:
@@ -2949,16 +2912,16 @@ static int rtpcs_930x_sds_config_hw_mode(struct rtpcs_serdes *sds, enum rtpcs_sd
break;
case RTPCS_SDS_MODE_XSGMII:
APPLY_EO(sds, is_even_sds, rtpcs_930x_sds_cfg_xsgmii_even,
rtpcs_930x_sds_cfg_xsgmii_odd);
break;
case RTPCS_SDS_MODE_USXGMII_10GSXGMII:
APPLY_EO(sds, is_even_sds, rtpcs_930x_sds_cfg_usxgmii_sx_even,
rtpcs_930x_sds_cfg_usxgmii_sx_odd);
APPLY_EO(sds, is_even_sds, rtpcs_930x_sds_cfg_ana_10g_even,
rtpcs_930x_sds_cfg_ana_10g_odd);
/* opcode 0x03: standard/generic USXGMII mode */
rtpcs_930x_sds_usxgmii_config(sds, true, 0x03, 0xa4, 0, 1, 0x1);
apply_fn(sds, rtpcs_930x_sds_cfg_usxgmii_xsgmii,
ARRAY_SIZE(rtpcs_930x_sds_cfg_usxgmii_xsgmii));
if (hw_mode == RTPCS_SDS_MODE_USXGMII_10GSXGMII)
/* opcode 0x03: standard/generic USXGMII mode */
rtpcs_930x_sds_usxgmii_config(sds, true, 0x03, 0xa4, 0, 1, 0x1);
break;
default: