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econet: add PCIe driver for EN751221 and enable wifi
Extend the EN7528 PCIe driver to EN751221 with a specific PHY tuning ritual. Also enable wifi drivers on SmartFiber XP8421-B, TpLink Archer VR1200V v2 and Zyxel PMG5617GA. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Link: https://github.com/openwrt/openwrt/pull/22208 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Caleb James DeLisle
committed by
Hauke Mehrtens
Hauke Mehrtens
parent
07f140f633
commit
c6bec81528
@@ -1,6 +1,7 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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#include <dt-bindings/reset/econet,en751221-scu.h>
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#include <dt-bindings/clock/econet,en751221-scu.h>
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/dts-v1/;
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@@ -53,6 +54,18 @@
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reg = <0x1fa20000 0x388>;
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};
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pcie_phy1: pcie-phy@1fac0000 {
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compatible = "econet,en751221-pcie-phy1";
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reg = <0x1fac0000 0x1000>;
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#phy-cells = <0>;
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};
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pcie_phy0: pcie-phy@1faf2000 {
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compatible = "econet,en751221-pcie-phy0";
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reg = <0x1faf2000 0x1000>;
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#phy-cells = <0>;
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};
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intc: interrupt-controller@1fb40000 {
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compatible = "econet,en751221-intc";
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reg = <0x1fb40000 0x100>;
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@@ -167,6 +180,94 @@
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};
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};
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pciecfg: pciecfg@1fb80000 {
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compatible = "mediatek,generic-pciecfg", "syscon";
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reg = <0x1fb80000 0x1000>;
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};
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pcie0: pcie@1fb81000 {
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compatible = "econet,en7528-pcie";
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device_type = "pci";
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reg = <0x1fb81000 0x1000>;
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reg-names = "port0";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <23>;
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interrupt-names = "pcie_irq";
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clocks = <&scuclk EN751221_CLK_PCIE>;
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clock-names = "sys_ck0";
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phys = <&pcie_phy0>;
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phy-names = "pcie-phy0";
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bus-range = <0x00 0xff>;
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ranges = <0x01000000 0 0x00000000 0x1f600000 0 0x00008000>,
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<0x82000000 0 0x20000000 0x20000000 0 0x08000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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slot0: pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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pcie1: pcie@1fb83000 {
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compatible = "econet,en7528-pcie";
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device_type = "pci";
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reg = <0x1fb83000 0x1000>;
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reg-names = "port1";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <24>;
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interrupt-names = "pcie_irq";
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clocks = <&scuclk EN751221_CLK_PCIE>;
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clock-names = "sys_ck1";
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phys = <&pcie_phy1>;
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phy-names = "pcie-phy1";
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0 0x00000000 0x1f608000 0 0x00008000>,
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<0x82000000 0 0x28000000 0x28000000 0 0x08000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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slot1: pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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usb: usb@1fb90000 {
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compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
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reg = <0x1fb90000 0x4000>,
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@@ -110,3 +110,28 @@
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nvmem-cells = <&macaddr_bootloader_ff48 0>;
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nvmem-cell-names = "mac-address";
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};
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&pcie0 {
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status = "okay";
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};
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&slot0 {
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wifi@0,0 {
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/* MT7612E */
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_reserve_180040>, <&macaddr_bootloader_ff48 1>;
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nvmem-cell-names = "eeprom", "mac-address";
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};
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};
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&pcie1 {
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status = "okay";
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};
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&slot1 {
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wifi@0,0 {
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/* MT7592 */
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_reserve_140000>, <&macaddr_bootloader_ff48 2>;
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nvmem-cell-names = "eeprom", "mac-address";
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};
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};
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@@ -102,3 +102,28 @@
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nvmem-cells = <&macaddr_misc_8f100 0>;
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nvmem-cell-names = "mac-address";
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};
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&pcie0 {
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status = "okay";
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};
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&slot0 {
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wifi@0,0 {
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/* MT7592 */
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_misc_80000>, <&macaddr_misc_8f100 1>;
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nvmem-cell-names = "eeprom", "mac-address";
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};
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};
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&pcie1 {
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status = "okay";
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};
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&slot1 {
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wifi@0,0 {
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/* MT7613BE */
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_misc_a0000>, <&macaddr_misc_8f100 2>;
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nvmem-cell-names = "eeprom", "mac-address";
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};
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};
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@@ -77,6 +77,49 @@
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partition@7540000 {
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label = "reservearea";
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reg = <0x007540000 0x000080000>;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_reserve_60000: eeprom@60000 {
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/* MT7592 */
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/* This overlaps the MT7612E EEPROM, but MT7603E demands
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* 1024 bytes of EEPROM even though only 512 bytes are used.
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*/
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reg = <0x60000 0x400>;
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};
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eeprom_reserve_60200: eeprom@60200 {
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/* MT7612E */
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reg = <0x60200 0x200>;
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};
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};
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};
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};
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};
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&pcie0 {
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status = "okay";
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};
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&slot0 {
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wifi@0,0 {
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/* MT7592 */
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_reserve_60000>;
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nvmem-cell-names = "eeprom";
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};
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};
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&pcie1 {
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status = "okay";
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};
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&slot1 {
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wifi@0,0 {
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/* MT7612E */
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_reserve_60200>;
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nvmem-cell-names = "eeprom";
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};
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};
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@@ -2,6 +2,7 @@ CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MMAP_RND_BITS_MAX=15
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
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CONFIG_BLK_MQ_PCI=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_COMMON_CLK=y
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@@ -69,7 +70,9 @@ CONFIG_GENERIC_LIB_ASHRDI3=y
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CONFIG_GENERIC_LIB_CMPDI2=y
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CONFIG_GENERIC_LIB_LSHRDI3=y
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CONFIG_GENERIC_LIB_UCMPDI2=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PHY=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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@@ -84,6 +87,7 @@ CONFIG_HZ_PERIODIC=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_MIPS_CPU=y
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CONFIG_IRQ_WORK=y
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@@ -119,7 +123,6 @@ CONFIG_NET_EGRESS=y
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CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NET_INGRESS=y
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CONFIG_NET_XGRESS=y
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
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CONFIG_NR_CPUS=2
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CONFIG_NVMEM=y
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CONFIG_NVMEM_LAYOUTS=y
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@@ -135,15 +138,27 @@ CONFIG_PADATA=y
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CONFIG_PAGE_POOL=y
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CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
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CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
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CONFIG_PCI_DRIVERS_LEGACY=y
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CONFIG_PCI=y
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CONFIG_PCIEAER=y
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CONFIG_PCIEPORTBUS=y
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CONFIG_PCIE_MEDIATEK=y
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CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PCI_DOMAINS_GENERIC=y
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CONFIG_PCI_DRIVERS_GENERIC=y
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CONFIG_PCI_MSI=y
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CONFIG_PCI_MSI_ARCH_FALLBACKS=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PGTABLE_LEVELS=2
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# CONFIG_PHY_EN7528_PCIE is not set
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CONFIG_PHY_EN7528_PCIE=y
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CONFIG_PTP_1588_CLOCK_OPTIONAL=y
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CONFIG_QUEUED_RWLOCKS=y
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CONFIG_QUEUED_SPINLOCKS=y
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CONFIG_RANDSTRUCT_NONE=y
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CONFIG_RAS=y
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CONFIG_RATIONAL=y
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CONFIG_REGMAP=y
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CONFIG_REGMAP_MMIO=y
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CONFIG_RESET_CONTROLLER=y
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CONFIG_RFS_ACCEL=y
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CONFIG_RPS=y
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@@ -25,7 +25,7 @@ define Device/smartfiber_xp8421-b
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DEVICE_DTS := en751221_smartfiber_xp8421-b
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IMAGES := tclinux.trx
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IMAGE/tclinux.trx := append-kernel | lzma | tclinux-trx
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DEVICE_PACKAGES := kmod-usb3
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DEVICE_PACKAGES := kmod-usb3 kmod-mt7603 kmod-mt76x2
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endef
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TARGET_DEVICES += smartfiber_xp8421-b
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@@ -41,6 +41,7 @@ define Device/tplink_archer-vr1200v-v2
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TPLINK_HWREVADD := 0x0
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TPLINK_HVERSION := 3
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DEVICE_DTS := en751221_tplink_archer-vr1200v-v2
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DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7663-firmware-ap
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IMAGES := sysupgrade.bin
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IMAGE/sysupgrade.bin := append-kernel | lzma | pad-to 4193792 | append-rootfs | \
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tplink-v2-header -R 0x400000
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@@ -53,6 +54,6 @@ define Device/zyxel_pmg5617ga
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DEVICE_DTS := en751221_zyxel_pmg5617ga
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IMAGES := tclinux.trx
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IMAGE/tclinux.trx := append-kernel | lzma | tclinux-trx
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DEVICE_PACKAGES := kmod-usb3
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DEVICE_PACKAGES := kmod-usb3 kmod-mt7603 kmod-mt76x2
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endef
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TARGET_DEVICES += zyxel_pmg5617ga
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@@ -11,7 +11,17 @@
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help
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--- a/arch/mips/econet/Kconfig
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+++ b/arch/mips/econet/Kconfig
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@@ -28,9 +28,11 @@ choice
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@@ -14,7 +14,9 @@ choice
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select COMMON_CLK
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select CPU_BIG_ENDIAN
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select ECONET_EN751221_INTC
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+ select HAVE_PCI
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select IRQ_MIPS_CPU
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+ select PCI_DRIVERS_GENERIC
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select SMP
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select SMP_UP
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select SYS_SUPPORTS_SMP
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@@ -28,9 +30,11 @@ choice
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bool "EN7528 family"
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select COMMON_CLK
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select CPU_LITTLE_ENDIAN
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@@ -205,7 +215,7 @@
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broadcom/ \
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--- /dev/null
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+++ b/drivers/phy/phy-en7528-pcie.c
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@@ -0,0 +1,119 @@
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@@ -0,0 +1,155 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2026 Ahmed Naseef <naseefkm@gmail.com>
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@@ -220,41 +230,71 @@
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+#include <linux/platform_device.h>
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+#include <linux/regmap.h>
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+
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+struct en7528_pcie_phy_data {
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+struct en7528_pcie_phy_op {
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+ u32 reg;
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+ u32 mask;
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+ u32 val;
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+ u32 max_reg;
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+};
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+
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+struct en7528_pcie_phy {
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+ struct regmap *regmap;
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+ const struct en7528_pcie_phy_data *data;
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+ const struct en7528_pcie_phy_op *data;
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+};
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+
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+/* Port 0 PHY: set LCDDS_CLK_PH_INV for PLL operation */
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+static const struct en7528_pcie_phy_data en7528_phy_port0 = {
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+ .reg = 0x4a0,
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+ .mask = BIT(5),
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+ .val = BIT(5),
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+ .max_reg = 0x4a0,
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+static const struct en7528_pcie_phy_op en7528_phy_port0[] = {
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+ {
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+ .reg = 0x4a0,
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+ .mask = BIT(5),
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+ .val = BIT(5),
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+ },
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+ { /* sentinel */ }
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+};
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+
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+/* Port 1 PHY: Rx impedance tuning, target R -5 Ohm */
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+static const struct en7528_pcie_phy_data en7528_phy_port1 = {
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+ .reg = 0xb2c,
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+ .mask = GENMASK(13, 12),
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+ .val = BIT(12),
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+ .max_reg = 0xb2c,
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+static const struct en7528_pcie_phy_op en7528_phy_port1[] = {
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+ {
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+ .reg = 0xb2c,
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+ .mask = GENMASK(13, 12),
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+ .val = BIT(12),
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+ },
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+ { /* sentinel */ }
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+};
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+
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+/* EN751221 Port 1 PHY */
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+static const struct en7528_pcie_phy_op en751221_phy_port1[] = {
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+ /* Rx Detection Timing for 7512 E1, 16*8 clock cycles */
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+ {
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+ .reg = 0xa28,
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+ .mask = GENMASK(17, 9),
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+ .val = 16 << 9,
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+ },
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+ /* Same for different power mode */
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+ {
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+ .reg = 0xa2c,
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+ .mask = GENMASK(8, 0),
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+ .val = 16,
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+ },
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+ { /* sentinel */ }
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+};
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+
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+static int en7528_pcie_phy_init(struct phy *phy)
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+{
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+ struct en7528_pcie_phy *ephy = phy_get_drvdata(phy);
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+ const struct en7528_pcie_phy_data *data = ephy->data;
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+ const struct en7528_pcie_phy_op *data = ephy->data;
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+ int i, ret;
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+
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+ return regmap_update_bits(ephy->regmap, data->reg,
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+ data->mask, data->val);
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+ for (i = 0; data[i].mask || data[i].val; i++) {
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+ if (i)
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+ usleep_range(1000, 2000);
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+
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+ ret = regmap_update_bits(ephy->regmap, data[i].reg,
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+ data[i].mask, data[i].val);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct phy_ops en7528_pcie_phy_ops = {
|
||||
@@ -265,7 +305,7 @@
|
||||
+static int en7528_pcie_phy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ const struct en7528_pcie_phy_data *data;
|
||||
+ const struct en7528_pcie_phy_op *data;
|
||||
+ struct regmap_config regmap_config = {
|
||||
+ .reg_bits = 32,
|
||||
+ .val_bits = 32,
|
||||
@@ -275,6 +315,7 @@
|
||||
+ struct en7528_pcie_phy *ephy;
|
||||
+ void __iomem *base;
|
||||
+ struct phy *phy;
|
||||
+ int i;
|
||||
+
|
||||
+ data = of_device_get_match_data(dev);
|
||||
+ if (!data)
|
||||
@@ -290,7 +331,10 @@
|
||||
+ if (IS_ERR(base))
|
||||
+ return PTR_ERR(base);
|
||||
+
|
||||
+ regmap_config.max_register = data->max_reg;
|
||||
+ for (i = 0; data[i].mask || data[i].val; i++)
|
||||
+ if (data[i].reg > regmap_config.max_register)
|
||||
+ regmap_config.max_register = data[i].reg;
|
||||
+
|
||||
+ ephy->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
|
||||
+ if (IS_ERR(ephy->regmap))
|
||||
+ return PTR_ERR(ephy->regmap);
|
||||
@@ -307,8 +351,10 @@
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id en7528_pcie_phy_ids[] = {
|
||||
+ { .compatible = "econet,en7528-pcie-phy0", .data = &en7528_phy_port0 },
|
||||
+ { .compatible = "econet,en7528-pcie-phy1", .data = &en7528_phy_port1 },
|
||||
+ { .compatible = "econet,en7528-pcie-phy0", .data = en7528_phy_port0 },
|
||||
+ { .compatible = "econet,en7528-pcie-phy1", .data = en7528_phy_port1 },
|
||||
+ { .compatible = "econet,en751221-pcie-phy0", .data = en7528_phy_port0 },
|
||||
+ { .compatible = "econet,en751221-pcie-phy1", .data = en751221_phy_port1 },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, en7528_pcie_phy_ids);
|
||||
|
||||
Reference in New Issue
Block a user