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realtek: mdio: backport upstream patches
Another round of MDIO driver patches was accepted upstream. Not production relevant as OpenWrt still uses the downstream driver. Link: https://github.com/openwrt/openwrt/pull/23768 Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This commit is contained in:
Markus Stockhausen
+147
@@ -0,0 +1,147 @@
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From 474400cf3f9faec064a35a7725c72a52f5ec6e5f Mon Sep 17 00:00:00 2001
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From: Markus Stockhausen <markus.stockhausen@gmx.de>
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Date: Sun, 7 Jun 2026 09:10:20 +0200
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Subject: [PATCH 04/15] net: mdio: realtek-rtl9300: Add prefix to register
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field defines
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The current Realtek Otto MDIO driver has some define leftovers without
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a SoC prefix. When adding new devices there will be an overlap for some
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of them. Sort this out as follows:
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- PHY_CTRL_CMD/PHY_CTRL_MMD_DEVAD/PHY_CTRL_MMD_REG are common for all
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series. Leave them as is but move them into a separate block.
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- Add RTL9300 prefix to all other defines and adapt the callers.
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
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---
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drivers/net/mdio/mdio-realtek-rtl9300.c | 63 +++++++++++++------------
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1 file changed, 32 insertions(+), 31 deletions(-)
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--- a/drivers/net/mdio/mdio-realtek-rtl9300.c
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+++ b/drivers/net/mdio/mdio-realtek-rtl9300.c
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@@ -59,23 +59,24 @@
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#define RTL9300_SMI_PORT0_15_POLLING_SEL 0xca08
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#define RTL9300_SMI_ACCESS_PHY_CTRL_0 0xcb70
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#define RTL9300_SMI_ACCESS_PHY_CTRL_1 0xcb74
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-#define PHY_CTRL_REG_ADDR GENMASK(24, 20)
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-#define PHY_CTRL_PARK_PAGE GENMASK(19, 15)
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-#define PHY_CTRL_MAIN_PAGE GENMASK(14, 3)
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-#define PHY_CTRL_WRITE BIT(2)
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-#define PHY_CTRL_READ 0
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-#define PHY_CTRL_TYPE_C45 BIT(1)
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-#define PHY_CTRL_TYPE_C22 0
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-#define PHY_CTRL_CMD BIT(0)
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-#define PHY_CTRL_FAIL BIT(25)
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+#define RTL9300_PHY_CTRL_REG_ADDR GENMASK(24, 20)
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+#define RTL9300_PHY_CTRL_PARK_PAGE GENMASK(19, 15)
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+#define RTL9300_PHY_CTRL_MAIN_PAGE GENMASK(14, 3)
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+#define RTL9300_PHY_CTRL_WRITE BIT(2)
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+#define RTL9300_PHY_CTRL_READ 0
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+#define RTL9300_PHY_CTRL_TYPE_C45 BIT(1)
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+#define RTL9300_PHY_CTRL_TYPE_C22 0
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+#define RTL9300_PHY_CTRL_FAIL BIT(25)
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#define RTL9300_SMI_ACCESS_PHY_CTRL_2 0xcb78
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-#define PHY_CTRL_INDATA GENMASK(31, 16)
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-#define PHY_CTRL_DATA GENMASK(15, 0)
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+#define RTL9300_PHY_CTRL_INDATA GENMASK(31, 16)
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+#define RTL9300_PHY_CTRL_DATA GENMASK(15, 0)
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#define RTL9300_SMI_ACCESS_PHY_CTRL_3 0xcb7c
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-#define PHY_CTRL_MMD_DEVAD GENMASK(20, 16)
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-#define PHY_CTRL_MMD_REG GENMASK(15, 0)
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#define RTL9300_SMI_PORT0_5_ADDR_CTRL 0xcb80
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+#define PHY_CTRL_CMD BIT(0)
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+#define PHY_CTRL_MMD_DEVAD GENMASK(20, 16)
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+#define PHY_CTRL_MMD_REG GENMASK(15, 0)
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+
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#define MAP_ADDRS_PER_REG 6
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#define MAP_BITS_PER_ADDR 5
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#define MAP_BITS_PER_BUS 2
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@@ -204,7 +205,7 @@ static int otto_emdio_read_cmd(struct mi
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if (ret)
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return ret;
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- *value = FIELD_GET(PHY_CTRL_DATA, *value);
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+ *value = FIELD_GET(RTL9300_PHY_CTRL_DATA, *value);
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return 0;
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}
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@@ -223,27 +224,27 @@ static int otto_emdio_9300_read_c22(stru
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{
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struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
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struct otto_emdio_cmd_regs cmd_data = {
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- .c22_data = FIELD_PREP(PHY_CTRL_REG_ADDR, regnum) |
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- FIELD_PREP(PHY_CTRL_PARK_PAGE, 0x1f) |
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- FIELD_PREP(PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
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- .io_data = FIELD_PREP(PHY_CTRL_INDATA, port),
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+ .c22_data = FIELD_PREP(RTL9300_PHY_CTRL_REG_ADDR, regnum) |
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+ FIELD_PREP(RTL9300_PHY_CTRL_PARK_PAGE, 0x1f) |
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+ FIELD_PREP(RTL9300_PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
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+ .io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, port),
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};
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- return otto_emdio_read_cmd(bus, PHY_CTRL_TYPE_C22, &cmd_data, value);
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+ return otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, &cmd_data, value);
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}
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static int otto_emdio_9300_write_c22(struct mii_bus *bus, int port, int regnum, u16 value)
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{
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struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
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struct otto_emdio_cmd_regs cmd_data = {
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- .c22_data = FIELD_PREP(PHY_CTRL_REG_ADDR, regnum) |
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- FIELD_PREP(PHY_CTRL_PARK_PAGE, 0x1f) |
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- FIELD_PREP(PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
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- .io_data = FIELD_PREP(PHY_CTRL_INDATA, value),
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+ .c22_data = FIELD_PREP(RTL9300_PHY_CTRL_REG_ADDR, regnum) |
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+ FIELD_PREP(RTL9300_PHY_CTRL_PARK_PAGE, 0x1f) |
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+ FIELD_PREP(RTL9300_PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
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+ .io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, value),
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.port_mask_low = BIT(port),
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};
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- return otto_emdio_write_cmd(bus, PHY_CTRL_TYPE_C22, &cmd_data);
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+ return otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, &cmd_data);
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}
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static int otto_emdio_9300_read_c45(struct mii_bus *bus, int port,
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@@ -252,10 +253,10 @@ static int otto_emdio_9300_read_c45(stru
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struct otto_emdio_cmd_regs cmd_data = {
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.c45_data = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
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FIELD_PREP(PHY_CTRL_MMD_REG, regnum),
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- .io_data = FIELD_PREP(PHY_CTRL_INDATA, port),
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+ .io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, port),
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};
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- return otto_emdio_read_cmd(bus, PHY_CTRL_TYPE_C45, &cmd_data, value);
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+ return otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, &cmd_data, value);
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}
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static int otto_emdio_9300_write_c45(struct mii_bus *bus, int port,
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@@ -264,11 +265,11 @@ static int otto_emdio_9300_write_c45(str
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struct otto_emdio_cmd_regs cmd_data = {
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.c45_data = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
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FIELD_PREP(PHY_CTRL_MMD_REG, regnum),
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- .io_data = FIELD_PREP(PHY_CTRL_INDATA, value),
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+ .io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, value),
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.port_mask_low = BIT(port),
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};
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- return otto_emdio_write_cmd(bus, PHY_CTRL_TYPE_C45, &cmd_data);
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+ return otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, &cmd_data);
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}
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static int otto_emdio_read_c22(struct mii_bus *bus, int phy_id, int regnum)
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@@ -582,9 +583,9 @@ static int otto_emdio_probe(struct platf
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static const struct otto_emdio_info otto_emdio_9300_info = {
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.addr_map_base = RTL9300_SMI_PORT0_5_ADDR_CTRL,
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.bus_map_base = RTL9300_SMI_PORT0_15_POLLING_SEL,
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- .cmd_fail = PHY_CTRL_FAIL,
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- .cmd_read = PHY_CTRL_READ,
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- .cmd_write = PHY_CTRL_WRITE,
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+ .cmd_fail = RTL9300_PHY_CTRL_FAIL,
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+ .cmd_read = RTL9300_PHY_CTRL_READ,
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+ .cmd_write = RTL9300_PHY_CTRL_WRITE,
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.cmd_regs = {
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.c22_data = RTL9300_SMI_ACCESS_PHY_CTRL_1,
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.c45_data = RTL9300_SMI_ACCESS_PHY_CTRL_3,
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+63
@@ -0,0 +1,63 @@
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From 2b24f54b8751e483a67443f93941a81c05ccce67 Mon Sep 17 00:00:00 2001
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From: Markus Stockhausen <markus.stockhausen@gmx.de>
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Date: Sun, 7 Jun 2026 10:12:51 +0200
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Subject: [PATCH 05/15] net: mdio: realtek-rtl9300: Make otto_emdio_read_cmd()
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generic
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The otto_emdio_read_cmd() helper still uses RTL9300 specific properties.
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This cannot be made generic as the I/O register has different layouts for
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the different SoCs. E.g.
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- RTL930x: data in bits 31-16, data out bits 15-0
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- RTL931x: data in bits 15-0, data out bits 31-16
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Add a mask parameter to the function signature and fill it properly
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in the callers. As the masks will always have bits set from constant
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defines, there is no need for a consistency check.
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Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
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Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
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---
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drivers/net/mdio/mdio-realtek-rtl9300.c | 10 ++++++----
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1 file changed, 6 insertions(+), 4 deletions(-)
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--- a/drivers/net/mdio/mdio-realtek-rtl9300.c
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+++ b/drivers/net/mdio/mdio-realtek-rtl9300.c
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@@ -191,7 +191,7 @@ static int otto_emdio_run_cmd(struct mii
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}
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static int otto_emdio_read_cmd(struct mii_bus *bus, u32 cmd,
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- struct otto_emdio_cmd_regs *cmd_data, u32 *value)
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+ struct otto_emdio_cmd_regs *cmd_data, u32 mask, u32 *value)
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{
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struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
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int ret;
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@@ -205,7 +205,7 @@ static int otto_emdio_read_cmd(struct mi
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if (ret)
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return ret;
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- *value = FIELD_GET(RTL9300_PHY_CTRL_DATA, *value);
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+ *value = field_get(mask, *value);
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return 0;
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}
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@@ -230,7 +230,8 @@ static int otto_emdio_9300_read_c22(stru
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.io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, port),
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};
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- return otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, &cmd_data, value);
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+ return otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C22, &cmd_data,
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+ RTL9300_PHY_CTRL_DATA, value);
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}
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static int otto_emdio_9300_write_c22(struct mii_bus *bus, int port, int regnum, u16 value)
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@@ -256,7 +257,8 @@ static int otto_emdio_9300_read_c45(stru
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.io_data = FIELD_PREP(RTL9300_PHY_CTRL_INDATA, port),
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};
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- return otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, &cmd_data, value);
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+ return otto_emdio_read_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, &cmd_data,
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+ RTL9300_PHY_CTRL_DATA, value);
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}
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static int otto_emdio_9300_write_c45(struct mii_bus *bus, int port,
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+58
@@ -0,0 +1,58 @@
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From 2628d4b57215ff57c062644523badbabeb22a095 Mon Sep 17 00:00:00 2001
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From: Markus Stockhausen <markus.stockhausen@gmx.de>
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Date: Sun, 7 Jun 2026 09:24:09 +0200
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Subject: [PATCH 06/15] net: mdio: realtek-rtl9300: Add registers for high port
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count models
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The high port count models of the Realtek Otto switches have additional
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registers to instrument the MDIO controller. These are:
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- High port mask: A bitfield that extends the already existing low port
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mask to select ports starting from 32.
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- Broadcast: This takes the port number during reads on the RTL931x.
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- Extended page: Some additional page info. The SDK does not give much
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information about this. Basically some fixed value must be written
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into it during access.
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
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---
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drivers/net/mdio/mdio-realtek-rtl9300.c | 20 ++++++++++++++++++++
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1 file changed, 20 insertions(+)
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--- a/drivers/net/mdio/mdio-realtek-rtl9300.c
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+++ b/drivers/net/mdio/mdio-realtek-rtl9300.c
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@@ -91,6 +91,10 @@ struct otto_emdio_cmd_regs {
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u32 c45_data;
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u32 io_data;
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u32 port_mask_low;
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+ /* additional registers for high port count models RTL839x/RTL931x */
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+ u32 port_mask_high;
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+ u32 broadcast;
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+ u32 ext_page;
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};
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struct otto_emdio_priv {
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@@ -164,6 +168,22 @@ static int otto_emdio_run_cmd(struct mii
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return ret;
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/* Fill all registers. Hardware will read only the needed bits depending on command */
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+ if (info->cmd_regs.port_mask_high) {
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+ /* Fill extra registers for high port count models */
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+ ret = regmap_write(priv->regmap, info->cmd_regs.broadcast, cmd_data->broadcast);
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+ if (ret)
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+ return ret;
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+
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+ ret = regmap_write(priv->regmap, info->cmd_regs.ext_page, cmd_data->ext_page);
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+ if (ret)
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+ return ret;
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+
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+ ret = regmap_write(priv->regmap,
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+ info->cmd_regs.port_mask_high, cmd_data->port_mask_high);
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+ if (ret)
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+ return ret;
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+ }
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+
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ret = regmap_write(priv->regmap, info->cmd_regs.port_mask_low, cmd_data->port_mask_low);
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if (ret)
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return ret;
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+187
@@ -0,0 +1,187 @@
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From 390dfbbd1ead27523853a21fd587b1285006a4ef Mon Sep 17 00:00:00 2001
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From: Markus Stockhausen <markus.stockhausen@gmx.de>
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Date: Sun, 7 Jun 2026 10:09:44 +0200
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Subject: [PATCH 07/15] net: mdio: realtek-rtl9300: Add support for RTL931x
|
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The MDIO driver has been prepared for multiple device support. Add all
|
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required bits for the RTL931x (aka mango) series. This is straightforward
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but some things are worth to be mentioned.
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- In contrast to RTL930x the I/O register has the input/output fields
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swapped. Upper 16 bits are for read/outputs, and the lower 16 bits
|
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are for write/inputs.
|
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- The supported "pages" are 8192 and thus the raw page is 8191
|
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- The devices support up to 56 ports. Thus the MAX_PORTS definition
|
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is increased by this commit.
|
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- There are multiple global SMI controller registers with a different
|
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layout from RTL930x devices. Therefore a separate setup_controller()
|
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callback is added.
|
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
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---
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drivers/net/mdio/mdio-realtek-rtl9300.c | 123 +++++++++++++++++++++++-
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1 file changed, 122 insertions(+), 1 deletion(-)
|
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|
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--- a/drivers/net/mdio/mdio-realtek-rtl9300.c
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+++ b/drivers/net/mdio/mdio-realtek-rtl9300.c
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@@ -73,6 +73,31 @@
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#define RTL9300_SMI_ACCESS_PHY_CTRL_3 0xcb7c
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#define RTL9300_SMI_PORT0_5_ADDR_CTRL 0xcb80
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+#define RTL9310_NUM_BUSES 4
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+#define RTL9310_NUM_PAGES 8192
|
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+#define RTL9310_NUM_PORTS 56
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+#define RTL9310_SMI_GLB_CTRL1 0x0cbc
|
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+#define RTL9310_SMI_GLB_FMT_SEL_C45(intf) BIT((intf) * 2 + 1)
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+#define RTL9310_SMI_INDRT_ACCESS_CTRL_0 0x0c00
|
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+#define RTL9310_PHY_CTRL_REG_ADDR GENMASK(10, 6)
|
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+#define RTL9310_PHY_CTRL_MAIN_PAGE GENMASK(23, 11)
|
||||
+#define RTL9310_PHY_CTRL_READ 0
|
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+#define RTL9310_PHY_CTRL_WRITE BIT(4)
|
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+#define RTL9310_PHY_CTRL_TYPE_C45 BIT(3)
|
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+#define RTL9310_PHY_CTRL_TYPE_C22 0
|
||||
+#define RTL9310_PHY_CTRL_FAIL BIT(1)
|
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+#define RTL9310_SMI_INDRT_ACCESS_BC_PHYID_CTRL 0x0c14
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+#define RTL9310_BC_PORT_ID GENMASK(10, 5)
|
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+#define RTL9310_SMI_INDRT_ACCESS_CTRL_1 0x0c04
|
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+#define RTL9310_SMI_INDRT_ACCESS_CTRL_2_LOW 0x0c08
|
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+#define RTL9310_SMI_INDRT_ACCESS_CTRL_2_HIGH 0x0c0c
|
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+#define RTL9310_SMI_INDRT_ACCESS_CTRL_3 0x0c10 /* I/O fields flipped */
|
||||
+#define RTL9310_PHY_CTRL_DATA GENMASK(31, 16)
|
||||
+#define RTL9310_PHY_CTRL_INDATA GENMASK(15, 0)
|
||||
+#define RTL9310_SMI_INDRT_ACCESS_MMD_CTRL 0x0c18
|
||||
+#define RTL9310_SMI_PORT_ADDR_CTRL 0x0c74
|
||||
+#define RTL9310_SMI_PORT_POLLING_SEL 0x0c9c
|
||||
+
|
||||
#define PHY_CTRL_CMD BIT(0)
|
||||
#define PHY_CTRL_MMD_DEVAD GENMASK(20, 16)
|
||||
#define PHY_CTRL_MMD_REG GENMASK(15, 0)
|
||||
@@ -81,7 +106,7 @@
|
||||
#define MAP_BITS_PER_ADDR 5
|
||||
#define MAP_BITS_PER_BUS 2
|
||||
#define MAP_BUSES_PER_REG 16
|
||||
-#define MAX_PORTS 28
|
||||
+#define MAX_PORTS 56
|
||||
#define MAX_SMI_BUSSES 4
|
||||
#define RAW_PAGE(priv) ((priv)->info->num_pages - 1)
|
||||
|
||||
@@ -294,6 +319,60 @@ static int otto_emdio_9300_write_c45(str
|
||||
return otto_emdio_write_cmd(bus, RTL9300_PHY_CTRL_TYPE_C45, &cmd_data);
|
||||
}
|
||||
|
||||
+static int otto_emdio_9310_read_c22(struct mii_bus *bus, int port, int regnum, u32 *value)
|
||||
+{
|
||||
+ struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
|
||||
+ struct otto_emdio_cmd_regs cmd_data = {
|
||||
+ .broadcast = FIELD_PREP(RTL9310_BC_PORT_ID, port),
|
||||
+ .c22_data = FIELD_PREP(RTL9310_PHY_CTRL_REG_ADDR, regnum) |
|
||||
+ FIELD_PREP(RTL9310_PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
|
||||
+ };
|
||||
+
|
||||
+ return otto_emdio_read_cmd(bus, RTL9310_PHY_CTRL_TYPE_C22, &cmd_data,
|
||||
+ RTL9310_PHY_CTRL_DATA, value);
|
||||
+}
|
||||
+
|
||||
+static int otto_emdio_9310_write_c22(struct mii_bus *bus, int port, int regnum, u16 value)
|
||||
+{
|
||||
+ struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
|
||||
+ struct otto_emdio_cmd_regs cmd_data = {
|
||||
+ .c22_data = FIELD_PREP(RTL9310_PHY_CTRL_REG_ADDR, regnum) |
|
||||
+ FIELD_PREP(RTL9310_PHY_CTRL_MAIN_PAGE, RAW_PAGE(priv)),
|
||||
+ .io_data = FIELD_PREP(RTL9310_PHY_CTRL_INDATA, value),
|
||||
+ .port_mask_high = (u32)(BIT_ULL(port) >> 32),
|
||||
+ .port_mask_low = (u32)(BIT_ULL(port)),
|
||||
+ };
|
||||
+
|
||||
+ return otto_emdio_write_cmd(bus, RTL9310_PHY_CTRL_TYPE_C22, &cmd_data);
|
||||
+}
|
||||
+
|
||||
+static int otto_emdio_9310_read_c45(struct mii_bus *bus, int port,
|
||||
+ int dev_addr, int regnum, u32 *value)
|
||||
+{
|
||||
+ struct otto_emdio_cmd_regs cmd_data = {
|
||||
+ .broadcast = FIELD_PREP(RTL9310_BC_PORT_ID, port),
|
||||
+ .c45_data = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
|
||||
+ FIELD_PREP(PHY_CTRL_MMD_REG, regnum),
|
||||
+ };
|
||||
+
|
||||
+ return otto_emdio_read_cmd(bus, RTL9310_PHY_CTRL_TYPE_C45, &cmd_data,
|
||||
+ RTL9310_PHY_CTRL_DATA, value);
|
||||
+}
|
||||
+
|
||||
+static int otto_emdio_9310_write_c45(struct mii_bus *bus, int port,
|
||||
+ int dev_addr, int regnum, u16 value)
|
||||
+{
|
||||
+ struct otto_emdio_cmd_regs cmd_data = {
|
||||
+ .c45_data = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
|
||||
+ FIELD_PREP(PHY_CTRL_MMD_REG, regnum),
|
||||
+ .io_data = FIELD_PREP(RTL9310_PHY_CTRL_INDATA, value),
|
||||
+ .port_mask_high = (u32)(BIT_ULL(port) >> 32),
|
||||
+ .port_mask_low = (u32)(BIT_ULL(port)),
|
||||
+ };
|
||||
+
|
||||
+ return otto_emdio_write_cmd(bus, RTL9310_PHY_CTRL_TYPE_C45, &cmd_data);
|
||||
+}
|
||||
+
|
||||
static int otto_emdio_read_c22(struct mii_bus *bus, int phy_id, int regnum)
|
||||
{
|
||||
struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
|
||||
@@ -413,6 +492,22 @@ static int otto_emdio_9300_setup_control
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int otto_emdio_9310_setup_controller(struct otto_emdio_priv *priv)
|
||||
+{
|
||||
+ int i, err;
|
||||
+
|
||||
+ /* Put the interfaces into C45 mode if required */
|
||||
+ for (i = 0; i < priv->info->num_buses; i++) {
|
||||
+ err = regmap_assign_bits(priv->regmap, RTL9310_SMI_GLB_CTRL1,
|
||||
+ RTL9310_SMI_GLB_FMT_SEL_C45(i),
|
||||
+ priv->smi_bus_is_c45[i]);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int otto_emdio_probe_one(struct device *dev, struct otto_emdio_priv *priv,
|
||||
struct fwnode_handle *node)
|
||||
{
|
||||
@@ -624,8 +719,34 @@ static const struct otto_emdio_info otto
|
||||
.write_c45 = otto_emdio_9300_write_c45,
|
||||
};
|
||||
|
||||
+static const struct otto_emdio_info otto_emdio_9310_info = {
|
||||
+ .addr_map_base = RTL9310_SMI_PORT_ADDR_CTRL,
|
||||
+ .bus_map_base = RTL9310_SMI_PORT_POLLING_SEL,
|
||||
+ .cmd_fail = RTL9310_PHY_CTRL_FAIL,
|
||||
+ .cmd_read = RTL9310_PHY_CTRL_READ,
|
||||
+ .cmd_write = RTL9310_PHY_CTRL_WRITE,
|
||||
+ .cmd_regs = {
|
||||
+ .broadcast = RTL9310_SMI_INDRT_ACCESS_BC_PHYID_CTRL,
|
||||
+ .c22_data = RTL9310_SMI_INDRT_ACCESS_CTRL_0,
|
||||
+ .c45_data = RTL9310_SMI_INDRT_ACCESS_MMD_CTRL,
|
||||
+ .ext_page = RTL9310_SMI_INDRT_ACCESS_CTRL_1,
|
||||
+ .io_data = RTL9310_SMI_INDRT_ACCESS_CTRL_3,
|
||||
+ .port_mask_low = RTL9310_SMI_INDRT_ACCESS_CTRL_2_LOW,
|
||||
+ .port_mask_high = RTL9310_SMI_INDRT_ACCESS_CTRL_2_HIGH,
|
||||
+ },
|
||||
+ .num_buses = RTL9310_NUM_BUSES,
|
||||
+ .num_pages = RTL9310_NUM_PAGES,
|
||||
+ .num_ports = RTL9310_NUM_PORTS,
|
||||
+ .setup_controller = otto_emdio_9310_setup_controller,
|
||||
+ .read_c22 = otto_emdio_9310_read_c22,
|
||||
+ .read_c45 = otto_emdio_9310_read_c45,
|
||||
+ .write_c22 = otto_emdio_9310_write_c22,
|
||||
+ .write_c45 = otto_emdio_9310_write_c45,
|
||||
+};
|
||||
+
|
||||
static const struct of_device_id otto_emdio_ids[] = {
|
||||
{ .compatible = "realtek,rtl9301-mdio", .data = &otto_emdio_9300_info },
|
||||
+ { .compatible = "realtek,rtl9311-mdio", .data = &otto_emdio_9310_info },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, otto_emdio_ids);
|
||||
Reference in New Issue
Block a user