realtek: dsa: add the L2 table ids to the family config

The L2 debugfs dump walks fib_entries rows of the hash table and a
fixed 64 rows of the CAM. That covers both tables on RTL838x, RTL839x
and RTL930x, but not on RTL931x: otto_table.c maps the RTL9310 L2 table
with 32768 rows and its CAM with 128, while fib_entries stays at 16384
there (its TODO says the code cannot handle 32K). fib_entries also
sizes l2_uc_map and bounds the fdb_dump walk, so raising it is a change
of its own.

Record which otto_table ids hold the L2 hash table and the CAM of each
family, so a dump can take the row counts from otto_table_rows()
instead. Nothing reads the new fields yet, so this is a no-op on all
four families.

Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Gennaro Cimmino <gcimmino@rayonra.net>
Link: https://github.com/openwrt/openwrt/pull/25394
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This commit is contained in:
Gennaro Cimmino authored and Markus Stockhausen committed 2026-09-27 22:07:24 +02:00
1 parent 48b6665b17
commit fb9c8bf5ef
5 files changed
+10

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@@ -1148,6 +1148,8 @@ struct rtldsa_config {
u8 l2_bucket_size;
u16 n_mst;
u32 fib_entries;
enum otto_table_id l2_uc_tbl;
enum otto_table_id l2_cam_tbl;
int trk_ctrl;
int trk_hash_ctrl;
void (*stp_init)(void);
@@ -281,6 +281,8 @@ const struct rtldsa_config rtldsa_838x_cfg = {
.num_lag_ids = 8,
.cpu_port = RTL838X_CPU_PORT,
.fib_entries = 8192,
.l2_uc_tbl = RTL8380_TBL_L2_UC,
.l2_cam_tbl = RTL8380_TBL_L2_CAM_UC,
.mask_port_reg_be = rtl838x_mask_port_reg,
.set_port_reg_be = rtl838x_set_port_reg,
.get_port_reg_be = rtl838x_get_port_reg,
@@ -280,6 +280,8 @@ const struct rtldsa_config rtldsa_839x_cfg = {
.num_lag_ids = 16,
.cpu_port = RTL839X_CPU_PORT,
.fib_entries = 16384,
.l2_uc_tbl = RTL8390_TBL_L2_UC,
.l2_cam_tbl = RTL8390_TBL_L2_CAM_UC,
.mask_port_reg_be = rtl839x_mask_port_reg_be,
.set_port_reg_be = rtl839x_set_port_reg_be,
.get_port_reg_be = rtl839x_get_port_reg_be,
@@ -707,6 +707,8 @@ const struct rtldsa_config rtldsa_930x_cfg = {
.num_lag_ids = 16,
.cpu_port = RTL930X_CPU_PORT,
.fib_entries = 16384,
.l2_uc_tbl = RTL9300_TBL_L2_UC,
.l2_cam_tbl = RTL9300_TBL_L2_CAM_UC,
.mask_port_reg_be = rtl838x_mask_port_reg,
.set_port_reg_be = rtl838x_set_port_reg,
.get_port_reg_be = rtl838x_get_port_reg,
@@ -480,6 +480,8 @@ const struct rtldsa_config rtldsa_931x_cfg = {
.num_lag_ids = 16,
.cpu_port = RTL931X_CPU_PORT,
.fib_entries = 16384, /* TODO: has 32K but code cannot handle that */
.l2_uc_tbl = RTL9310_TBL_L2_UC,
.l2_cam_tbl = RTL9310_TBL_L2_CAM_UC,
.mask_port_reg_be = rtl839x_mask_port_reg_be,
.set_port_reg_be = rtl839x_set_port_reg_be,
.get_port_reg_be = rtl839x_get_port_reg_be,