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realtek: dsa: add the L2 table ids to the family config
The L2 debugfs dump walks fib_entries rows of the hash table and a fixed 64 rows of the CAM. That covers both tables on RTL838x, RTL839x and RTL930x, but not on RTL931x: otto_table.c maps the RTL9310 L2 table with 32768 rows and its CAM with 128, while fib_entries stays at 16384 there (its TODO says the code cannot handle 32K). fib_entries also sizes l2_uc_map and bounds the fdb_dump walk, so raising it is a change of its own. Record which otto_table ids hold the L2 hash table and the CAM of each family, so a dump can take the row counts from otto_table_rows() instead. Nothing reads the new fields yet, so this is a no-op on all four families. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Gennaro Cimmino <gcimmino@rayonra.net> Link: https://github.com/openwrt/openwrt/pull/25394 Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
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@@ -1148,6 +1148,8 @@ struct rtldsa_config {
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u8 l2_bucket_size;
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u16 n_mst;
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u32 fib_entries;
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enum otto_table_id l2_uc_tbl;
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enum otto_table_id l2_cam_tbl;
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int trk_ctrl;
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int trk_hash_ctrl;
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void (*stp_init)(void);
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@@ -281,6 +281,8 @@ const struct rtldsa_config rtldsa_838x_cfg = {
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.num_lag_ids = 8,
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.cpu_port = RTL838X_CPU_PORT,
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.fib_entries = 8192,
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.l2_uc_tbl = RTL8380_TBL_L2_UC,
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.l2_cam_tbl = RTL8380_TBL_L2_CAM_UC,
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.mask_port_reg_be = rtl838x_mask_port_reg,
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.set_port_reg_be = rtl838x_set_port_reg,
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.get_port_reg_be = rtl838x_get_port_reg,
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@@ -280,6 +280,8 @@ const struct rtldsa_config rtldsa_839x_cfg = {
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.num_lag_ids = 16,
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.cpu_port = RTL839X_CPU_PORT,
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.fib_entries = 16384,
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.l2_uc_tbl = RTL8390_TBL_L2_UC,
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.l2_cam_tbl = RTL8390_TBL_L2_CAM_UC,
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.mask_port_reg_be = rtl839x_mask_port_reg_be,
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.set_port_reg_be = rtl839x_set_port_reg_be,
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.get_port_reg_be = rtl839x_get_port_reg_be,
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@@ -707,6 +707,8 @@ const struct rtldsa_config rtldsa_930x_cfg = {
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.num_lag_ids = 16,
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.cpu_port = RTL930X_CPU_PORT,
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.fib_entries = 16384,
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.l2_uc_tbl = RTL9300_TBL_L2_UC,
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.l2_cam_tbl = RTL9300_TBL_L2_CAM_UC,
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.mask_port_reg_be = rtl838x_mask_port_reg,
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.set_port_reg_be = rtl838x_set_port_reg,
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.get_port_reg_be = rtl838x_get_port_reg,
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@@ -480,6 +480,8 @@ const struct rtldsa_config rtldsa_931x_cfg = {
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.num_lag_ids = 16,
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.cpu_port = RTL931X_CPU_PORT,
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.fib_entries = 16384, /* TODO: has 32K but code cannot handle that */
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.l2_uc_tbl = RTL9310_TBL_L2_UC,
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.l2_cam_tbl = RTL9310_TBL_L2_CAM_UC,
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.mask_port_reg_be = rtl839x_mask_port_reg_be,
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.set_port_reg_be = rtl839x_set_port_reg_be,
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.get_port_reg_be = rtl839x_get_port_reg_be,
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