- Fix RTL8261N 10GbE PHY `reset-deassert-us` from 100ms to 221ms to meet datasheet minimum SMI-ready timing (t7 >= 150ms), fixing intermittent boot stalls caused by MDIO bus instability
- Add missing WLAN toggle button (GPIO 34) present in stock firmware but absent from OpenWrt DTS
- Fix memory size from 1 GB to the actual 512 MB
Fix 1: The RTL8261N 10GbE PHY's `reset-deassert-us` was set to 100ms (100000us), but the **RTL8261N datasheet (Table 108, parameter t7)** specifies a minimum **SMI-ready time of 150ms** after nRESET release before the MDIO (SMI) bus can be used.
With only 100ms, the kernel attempts MDIO bus access before the RTL8261N's SMI interface is stable. Since the RTL8261N (mdio-bus:00) and the internal MT7988 2.5GbE PHY (mdio-bus:0f) share the same MDIO bus, a not-yet-ready RTL8261N disrupts all MDIO traffic, causing the 2.5GbE PHY firmware loading (`mt798x_2p5ge_phy_config_init`) to stall.
Observed symptoms on warm reboot:
- Sometimes `mt798x_2p5ge_phy_config_init` hangs for 5+ minutes or indefinitely
- RCU CPU stalls (`rcu: INFO: rcu_sched detected stalls on CPUs`)
- mt7996e WiFi chip message timeouts cascading to `chip full reset failed`
- System appears hung with only power LED blinking slowly
UART serial log evidence (warm reboot with 100ms):
```
[ 73.041756] rcu: INFO: rcu_sched self-detected stall on CPU
[ 73.048341] rcu: 2-....: (8 ticks this GP)
[ 73.061641] pc : mt798x_2p5ge_phy_config_init+0x258/0xbb0
[ 73.061653] lr : mt798x_2p5ge_phy_config_init+0x238/0xbb0
...
[ 334.771280] MediaTek MT7988 2.5GbE PHY mdio-bus:0f: Firmware date code: 2024/10/30
```
The 2.5GbE PHY firmware loading, which normally takes ~3 seconds, took **325 seconds** due to MDIO bus instability. In the worst case, the system never recovers.
GPL DTS uses 221ms (`reset-deassert-us = <221000>`), providing 71ms of margin above the 150ms datasheet minimum. All MediaTek MT7988 reference board DTS files in the GPL use this same 221ms value.
Fix 2: Missing WLAN button (GPIO 34)
The BE450 has a physical WLAN toggle button on GPIO 34, defined in the stock TP-Link GPL DTS but missing from the OpenWrt DTS. Without this definition, the button is non-functional under OpenWrt.
The pin name for GPIO 34 in the MT7988 pinctrl is `SPI2_MISO`, confirmed by the kernel pinctrl driver (`pinctrl-mt7988.c`: `MT7988_PIN(34, "SPI2_MISO")`) and the official devicetree binding (`mediatek,mt7988-pinctrl.yaml`).
Note: GPIO 34 is also used by the BE450's First U-Boot as a recovery button (web recovery 192.168.1.1). Registering it in the DTS ensures the kernel claims the pin.
Fix 3: Incorrect memory size in DTS
The OpenWrt DTS declares 1 GB (`0x40000000`) of RAM, but the BE450 has 512 MB (`0x20000000`).
Run tested.
Signed-off-by: Semih Baskan <strst.gs@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22386
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit f2699cce13)
RTL838x devices cannot reboot if the flash controller is driven in
4 byte mode. Unitl fdc3776 ("realtek: pcs: fix PLL_CML_CTRL for
serdes 0/1") this bit was luckily cleared by a coding error. Since
then the device cannot be rebooted anymore.
Looking at the SDK one can see that this bit is reset short before
the reboot happens. But we might need that in critical situations
where there is no chance to do it right in time. As the RTL838x
always ran with the bit disabled restore the old behaviour. This
time implement it as a documented quirk so it does not get lost.
Fixes: fdc3776 ("realtek: pcs: fix PLL_CML_CTRL for serdes 0/1")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
(cherry-pick from commit b995f318b2)
Link: https://github.com/openwrt/openwrt/pull/22384
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SFP I2C buses for ports 1 and 3 were swapped as order changed on production
boards.
So, swap them around to fix SFP 1 and 3 failed to read EEPROM errors.
Fixes: 29b3d929a6 ("microchipsw: lan969x: add Novarq Tactical 1000")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
(cherry picked from commit 55f1f2c1c4)
Fix two hardware initialization issues in the EN7581 PCIe controller
and add support for x2 (2-lane) link mode.
Fixes:
The upstream EN7581 PCIe initialization writes EQ presets and PIPE
configuration registers before clk_bulk_prepare_enable(). Since the
MAC clocks are not yet running at that point, these register writes
are silently dropped, leaving the hardware with default values. This
can cause link training failures or suboptimal equalization.
Additionally, after link training the MAC may only advertise Gen1-Gen2
capability in the Link Capabilities 2 register despite the PHY being
configured for Gen3. A serdes reset toggle forces the MAC to re-read
PHY capability, recovering Gen3 8GT/s link speed.
Both issues are addressed by separating PERST from the clock callbacks
(patch 911), allowing the PCIe controller driver to properly sequence
PERST, clock enable, and register writes (patch 912).
New feature:
PCIe x2 mode support for EN7581 using the NP_SCU system controller
for serdes mux routing, PERST management, and lane configuration.
Both bonded MACs are configured for x2 operation with proper EQ
presets before link training begins.
Signed-off-by: Ryan Chen <rchen14b@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21978
Link: https://github.com/openwrt/openwrt/pull/22336
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MeshPoint.One was disabled during the DSA migration with the
comment "Missing DSA Setup". However, this device inherits its
entire network configuration from 8dev Jalapeno via the
Device/8dev_jalapeno-common template, and shares the same DSA
network setup in 02_network.
The Jalapeno has been working with DSA since the migration. All
MeshPoint.One board support files (DTS, network config, LED config)
are already in place and reference the same QCA8072 switch
configuration as the Jalapeno.
Hardware: Qualcomm IPQ4018, QCA8072 switch, same as 8dev Jalapeno.
Tested: Built firmware from current main branch, boots and network
functions correctly.
Signed-off-by: Valent Turkovic <valent@meshpointone.com>
Link: https://github.com/openwrt/openwrt/pull/22258
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit a75cc4f18c)
Link: https://github.com/openwrt/openwrt/pull/22279
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SerDes attached ports that are connected during switch
boot might not be able to transmit any data after SerDes
setup. Especially ports that passed traffic before (e.g.
for tftp initramfs boot) seem to be affected. Ports that
are connected later do not show this issue.
It turns out that the old SerDes setup never really worked
on RTL8382 and the pcs refactoring (with dynamic SerDes
start and stop) totally changed the order of network bringup
in contrast to Realtek SDK.
Fix this by restaring the switch queue whenever a SerDes
goes up for the first time.
Fixes: e956adf ("realtek: rtl838x: setup SDS in PCS driver")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21956
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 0839c5c9f2)
Manually resolved merge conflicts.
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22087
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The write protection register (0x1b000058) is opened up in prom init
but closed later in rtl838x_pie_init(). From that moment no more
special register writes are possible.
Only unlock the write protection register once during prom init.
Remove all other references. The error has been active since ages
but was not visible until pcs refactoring. For reference blame the
refactoring commit.
Fixes: e956adf ("realtek: rtl838x: setup SDS entirely in PCS driver")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21956
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 8bf37836d6)
Manually resolved merge conflicts of prom.c
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22087
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Setup of register PLL_CML_CTRL has two issues.
- It clears out bits 4-31 due to a wrong mask
- Setup of bits 0-3 is not generic but depends on the mode of
serdes 0/1
Fix that by relocating the code and adapting the mask. The error
exists for longer but it has survived the pcs refactoring. Thus
blame the corresponding refactoring commit.
Fixes: b670d48 ("realtek: pcs: rtl838x: refactor imported code")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21956
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit fdc3776068)
Link: https://github.com/openwrt/openwrt/pull/22087
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The device has 1 100MBit/s port. By default the PHY firmware is running
in 1GBit/s mode. The driver will try to load the 1GBit/s firmware and
fail if it is not there. Set the GPHY0 also to 100MBit/s mode.
The driver uses all nodes independent of the status attribute.
Do the same fix for AVM FRITZ!Box 7412 too.
Reported-by: Achelon in OpenWrt forum
Fixes: https://github.com/openwrt/openwrt/issues/21836
Link: https://github.com/openwrt/openwrt/pull/22188
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 296b286a67)
On MT7620-class platforms (CONFIG_NET_RALINK_MT7620) we observe sporadic
wrong-jump-targets, kernel oopses, hanging, corrupted backtraces or even
"half-written" instructions when the compiler emits a direct 'jal imm26'
call.
This is triggered in:
- the small random helpers inside get_random_u32_below(), and
- the blkcg_maybe_throttle_current() call in resume_user_mode_work().
This patch forces those two call sites to use an indirect call via
a volatile function pointer (load into register + jalr) when building
for MT7620, avoiding embedding a 26-bit immediate jump target.
Additionally, on MT7620 builds the exec path in fs/exec.c is modified:
- skip arch_align_stack() + PAGE_ALIGN() in setup_arg_pages()
because the micro-randomization (< PAGE_SIZE) implemented by many
ports (including MT7620) is negated immediately by PAGE_ALIGN().
Skipping the redundant PAGE_ALIGN() reduces exposure to the
problematic code pattern.
These changes are targeted workarounds for MT7620; behavioral logic is unchanged.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/20553
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 22ccb445e6)
This reverts commit 9dbd45c187.
Compared to ralink,mtd-eeprom , the nvmewm binding ends up byteswapping
the data on big endian hosts. Meaning on big endian, the nvmwem binding
is equivalent to:
ralink,mtd-eeprom +
ralink,eeprom-wrap
Revert as a result since there's no eeprom-swap here.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22192
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit d4845bf618)
The configuration for the dlink,dir-1360-a1 also changed the settings
for the devices defined on top of it. "lan1 lan2 lan3 lan4" "wan" is
the default configuration, no need to add it here.
Fixes: 7a8e2efed5 ("ramips: add support for D-Link DIR-1360 A1")
Reported-by: schmars in IRC
Link: https://github.com/openwrt/openwrt/pull/22179
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 758c8a26e9)
Mikrotik RBM33G has got a USB-A port and mPCIe slots with USB 3.0 and USB
2.0 interfaces in use. The MediaTek MT7621 SoC has got an xHCI to provide
these interfaces. Therefore, enable kmod-usb3 to support them.
Fixes: 5684d08741 ("ramips: Add support for Mikrotik RouterBOARD RBM33g")
Signed-off-by: Chester A. Unal <chester.a.unal@arinc9.com>
(cherry picked from commit 61c9337d80)
The GPIO line connecting to the reset signals of the GS1900-24E(A1)'s
external ICs (RTL8218B phys and RTL8231 expander) cannot be asserted by
the MDIO subsystem, as the reset is shared between busses.
To prevent users from accidentally asserting the reset line, a GPIO hog
is created to permanently de-assert the signal, reliably keeping the
phys and GPIO expanders on.
Tested-by: Simon Fischer <simi.fischa@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit ba57225066)
The reset line wired to the RTL8231 on the GS1900 series may also
connect to other external ICs on the board. On the GS1900-24E, the
reset line is wired (via buffers) to the board's RTL8231 expanders and
the RTL8218 phys. As these external devices (phys) are on different
busses, the reset line shouldn't be specified on one bus or the other.
Drop the reset specification from the generic GPIO description, so it
can be added back on a per-device basis after confirming the behavior.
Link: https://github.com/openwrt/openwrt/issues/18620
Fixes: fd978c2e80 ("realtek: Enable Zyxel GS1900's RTL8231 reset line")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit cdbd9eb448)
The KSZ9477 driver was added to the cortexa53 kernel to support the
Gateworks Venice product family which has a board with this switch. Now
that the kmod-dsa-ksz9477 driver is available as a package remove the
static configuration ad add the package.
This resolves an issue caused by having the switch driver static and the
PHY driver as a module such that the PHY driver was not registered early
enough to be used causing some errata to not be worked around.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Link: https://github.com/openwrt/openwrt/pull/22120
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 231553b280)
The TP-Link EAP683-UR is identical to the EAP683-LR. Add it as ALT0
variant.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
(cherry picked from commit 708dcca80a)
Add support for the TP-Link EAP683-LR, an AX6000 Ceiling Mount WiFi 6
AP.
Hardware:
* SoC: MediaTek MT7896AV
* RAM: 1GiB DDR4 (Samsung K4A8G165WC-BCTD)
* Flash: 128MiB SPI-NAND (ESMT F50L1G41LB)
* Ethernet: 1x 10/100/1000/2500 Mbps PoE-PD (MaxLinear GPY211C)
* WiFi: MT7976AN/MT7976GN 2.4/5GHz 4T4R
* LEDS: 3x blue connected to a single GPIO line
* Buttons: 1x reset
* BLE/Thread/Zigbee: CC2652
Stock firmware uses a random MAC address for ethernet, label MAC for
2.4 and label MAC + for 5GHz.
Installation via bootloader:
* Solder JST??? connector on J255, alternatively solder wires on the
TP13-TP15 pads. Pinout: TP13: TX, TP14: RX, TP15: GND, TP16: VCC.
The pins for J255 are in the same order.
* Interrupt boot process by repeatedly pressing Ctrl+b during boot
* In the boot menu, select U-Boot console
* Ensure the U-Boot environment variable "tp_boot_idx" is not set:
# setenv tp_boot_idx
# saveenv
* Boot the OpenWrt initramfs:
# tftpboot openwrt-mediatek-filogic-tplink_eap683-lr-initramfs-kernel.bin
# bootm
* copy openwrt-mediatek-filogic-tplink_eap683-lr-squashfs-sysupgrade.bin
to /tmp and install it using sysupgrade
Flashing via OEM firmware is currently not supported. The
tplink-safeloader utility does not recognize the OEM firmware:
DEBUG: can not find fwuphdr
Firmware image partitions:
base size name
Segmentation fault (core dumped)
To revert to the OEM firmware, you can set the U-Boot environment
variable "tp_boot_idx" to 1 via bootloader, or using fw_setenv via
OpenWrt. This should result in booting from the ubi1 partition, which
OpenWrt should not touch. Then use the web interface to upgrade
firmware: System > Firmware Update.
The OEM firmware uses 0x800000 for the runtime_backup partition size.
This causes the following warning:
mtd: partition "runtime_backup" extends beyond the end of device "nmbm_spim_nand" -- size truncated to 0x600000
This is due to the NMBM reserved blocks. Use 0x600000 in our DTS.
Thanks to init Lab's user890104, who soldered jumper wires on the TTL
pads for me so I could have serial console. My soldering skills just
aren't good enough to pull that off without risk damaging things.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
(cherry picked from commit f1749142ca)
This reverts commit 72f43ac220.
The NVMEM codepath does not perform automatic byte conversion. It can be
fixed but the upstream version is quite different from the local
mac80211 patch. Revert until mac80211 gets updated and the whole mess
can get squared away.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22091
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit b270580dea)
Remove incomplete SPI flash definitions from affected device tree files.
These fragments only defined address-cells and size-cells without any
actual flash configuration (partitions, compatible string, etc.).
After applying openwrt/openwrt#20942 ("kernel: of: fix bad cell count error
for SPI flash node"), the kernel properly handles SPI flash nodes without
requiring these incomplete definitions in device-specific DTS files.
This cleanup eliminates unnecessary code that was likely a workaround for
the previous kernel issue.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/22036
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 313d563664)
The target name of meraki_mx64-a0 in
target/linux/bcm53xx/image/Makefile used not to be consistent with the
one defined in target/linux/bcm53xx/base-files/lib/upgrade/platform.sh
and generates warning for "Image check failed" during sysupgrade.
This commit would also make the target name for meraki_mx64-a0 to
conform to the openwrt standard.
Signed-off-by: Edward Chow <equu@openmail.cc>
Link: https://github.com/openwrt/openwrt/pull/22034
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 625f01cd80)
The Linux kernel assumes that the u-boot environment covers the full
partition, but it only covers 0x1000 bytes. Linux checks the CRC and
does this over the full partition. This fails like this:
```
u-boot-env-layout 1f000000.spi:flash@0:partitions:partition@30000:nvmem-layout: Invalid calculated CRC32: 0xfcac8c41 (expected: 0x14e6335a)
u-boot-env-layout 1f000000.spi:flash@0:partitions:partition@30000:nvmem-layout: probe with driver u-boot-env-layout failed with error -22
```
Define the u-boot environment with a length of 0x1000 bytes to calculate
the CRC only over this area.
When replicating the u-boot environment with these parameters it
generates the same CRC:
```
mkenvimage -p 0 -b -s 0x1000 -o output.bin input.txt
```
Fixes: https://github.com/openwrt/openwrt/issues/21696
Fixes: 5e3a602def ("ath79: sitecom,wlrx100: use nvmem")
Link: https://github.com/openwrt/openwrt/pull/22030
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 68a466b698)
RIPE Atlas Probe v5 is a network measurement device based on Turris MOX.
u-boot bootscript supports booting both from the original Turris BTRFS
layout and default OpenWrt ext4 boot + root partition layout.
Specifications:
* SoC: Marvell ARMADA 3720
* RAM: 512 MiB, DDR3
* eMMC: 4G
* Ethernet: 1x 1GbE
MAC:
LAN MAC: label on board
Flash instructions:
* For using the default ext4 layout, boot into a live system using
tftpboot in u-boot and flash an OpenWrt SD image onto /dev/mmcblk0.
* For the Turris layout, put the new rootfs into subvolume '@', not
forgetting to add Image, device tree, and boot.scr to /boot.
Misc:
* USB connection is only for power. For UART access use the pin header:
1: GND
2: +1.8V
5: TX
6: RX
* Flashing the image onto Turris Shield won't work. Use Turris MOX image
instead.
Signed-off-by: Tomáš Macholda <tomas.macholda@nic.cz>
Link: https://github.com/openwrt/openwrt/pull/20031
(cherry picked from commit 0271f2ee36)
Signed-off-by: Trix Taiclet <git@trix.moe>
Link: https://github.com/openwrt/openwrt/pull/22048
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Mark T4240RDB u-boot variants as device-built and avoid installing them into rootfs.
Without this buildbot crashes during package install with:
ERROR: unable to select packages:
u-boot-fsl_T4240RDB-nor (no such package):
required by: world[u-boot-fsl_T4240RDB-nor]
u-boot-fsl_T4240RDB-sdboot (no such package):
required by: world[u-boot-fsl_T4240RDB-sdboot]
Fixes: c5d3d5fe28 ("package: u-boot: initial support for qoriq arch")
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21514
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 20727f89d5)
Link: https://github.com/openwrt/openwrt/pull/21477
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Jakub Vaněk
Semih Baskan
Markus Stockhausen
Robert Marko
Rosen Penev
Ryan Chen
Ivan Diaz
Jonas Köppeler
John Audia
Álvaro Fernández Rojas
Valent Turkovic
Robert Marko
Tim Harvey
Rafał Miłecki
Hauke Mehrtens
Mieczyslaw Nalewaj
Chester A. Unal
Sander Vanheule
Shiji Yang
Stijn Tintel
Edward Chow
Tomáš Macholda
Goetz Goerisch
Fil Dunsky
Pawel Dembicki