The profiles.json[1] in generated and used during ASU sysupgrades takes
DEVICE_NAME as profile name which break ASU sysupgrades, use BOARD_NAME
which serves the same goal as overwriting DEVICE_NAME, allowing
sysupgrade-tar's checks be succesfully passed using the old name used in
older installations. Without affecting the generated profiles.json, thus
recovering ASU support.
*Keep the non-stardand device name with suffix "-mtd"(replaced underscore
by hyphen) to remark that this device is also supported in the armsr
(armvirt) target as originally intented[2].
*I think I have fully checked the sysupgrade path to confirm this change
does not have side effects.
[1]: https://downloads.openwrt.org/releases/25.12.0/targets/layerscape/armv8_64b/profiles.json
[2]: https://github.com/openwrt/openwrt/pull/12828
Fixes: af0546da34 ("layerscape: armv8_64b: add Traverse Ten64 NAND variant")
Fixes: https://github.com/openwrt/asu/issues/1583
Reported-by: DanaGoyette (github)
Co-developed-by: Eric Fahlgren <ericfahlgren@gmail.com>
Signed-off-by: Mario Andrés Pérez <mapb_@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22359
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add missing patch description, so all patches of the mediatek target can
be applied to a kernel tree using 'git am'.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add missing patch description, so all generic patches can be applied
to a kernel tree using 'git am'.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The XMG1915-10E is a switch with 8 copper ports and 2 SFP+ cages.
Specifications:
---------------
* SoC: RTL9302C
* Flash: 32 MiB SPI NOR flash
* RAM: 256 MiB
* Ethernet: 8x 10/100/1000/2500 Mbps (RTL8224)
* SFP: 2x SFP+ cages
* UART: 1x 4 pins serial header, 115200 bauds, 8n1, 3.3v logic levels,
pinout: unused (top), TX, RX, GND (bottom)
* Buttons: 1x "Reset" button
Works:
------
- 2 SFP+ cages either 1G/10G or 2.5G
- 8*2.5G Ethernet ports
- Switch function
- LEDs
- Boot from flash
- Assigning MAC addresses from flash
Ethernet ports:
---------------
The 8x 2.5Gbps ethernet ports are provided by two RTL8224 chips. The
ports are supported by the upstream realtek PHY driver plus a local
initialization patch for the 10g-qxgmii mode.
Installation:
-------------
This device uses ZyNOS instead of Linux which makes the installation a
bit cumbersome. OpenWRT will be installed on the slot of the second
firmware image, thus the switch original firmware can be booted with a
little change. The serial console is required.
1. Set the switch to boot from the first image. This is required to
be sure not to be blocked in the middle of the installation
procedure.
2. Connect to the switch using the serial adapter and interrupt the boot
process by pressing "Enter" repeatedly.
3. Load the OpenWRT initramfs image using xmodem. From bootext console
(use ATHE to get the list of commands):
> ATUP 81800000,file_length
> ATGO 81800000
4. Wait for OpenWRT to boot, once this is done transfer the loader
binary and the sysupgrade image to /tmp using scp.
5. Install OpenWRT permanently by writing the images on the flash:
> mtd write /tmp/loader.bin loader
> mtd write /tmp/sysupgrade.bin firmware
6. Reboot the switch and from the stock firmware set the configuration
to boot from the second image (Maintenance > Firmware upgrade > Boot
image).
7. Reboot again and enjoy OpenWRT.
Recovery/Return to stock:
-------------------------
1. Connect the switch using the serial adapter and interrupt the boot
process during the "DRAM POST: Testing:" sequence by pressing '$'
until the "XMG1915$" prompt appears.
2. Start an ymodem upgrade using the following command and use an xmodem
upload tool to send the .bin file provided in an OEM upgrade package.
XMG1915$ upgradeY image2 81000000 115200
## Ready for binary (ymodem) download to 0x081000000 at 115200 bps...
3. Wait for the upgrade process to finish and reboot the switch.
Signed-off-by: Damien Dejean <dam.dejean@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21341
Signed-off-by: Robert Marko <robimarko@gmail.com>
This refactoring is a little bit of all ...
For access to the ring counter and size registers there exist currently
separate helpers. These are only for the register number but not the
bit position inside the register. Register definitions still use the
old prefix. Resolve this mix by
- Changing the prefixes of the register defines
- replacing the helpers with the register addresses
- just calculating register & offset manually where needed.
This might be a little step back but at least aligns with the rest of
the register access code. A future commit might bring an even better
version.
While we are here convert the main consumer rteth_93xx_hw_reset() to
regmap and fix a bug. Until now this function only clears the first
counter in a register because of a missing bit shift during writeback.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22920
Signed-off-by: Robert Marko <robimarko@gmail.com>
Commit b4d7263bc3 ("kernel: of: avoid some unnecessary bad cell count
warnings") backported Linux commit 6e5773d52f4a ("of/address: Fix WARN
when attempting translating non-translatable addresses"), which started
requiring #address-cells for a device's parent if we want to use the
reg resource in a device node.
Many Chromium devices use a /firmware/coreboot device node that is
patched in by the boot firmware. These structures look something like:
# find /sys/firmware/devicetree/base/firmware/
/sys/firmware/devicetree/base/firmware/
/sys/firmware/devicetree/base/firmware/scm
/sys/firmware/devicetree/base/firmware/scm/compatible
/sys/firmware/devicetree/base/firmware/scm/name
/sys/firmware/devicetree/base/firmware/ranges
/sys/firmware/devicetree/base/firmware/chromeos
/sys/firmware/devicetree/base/firmware/chromeos/fmap-offset
/sys/firmware/devicetree/base/firmware/chromeos/compatible
/sys/firmware/devicetree/base/firmware/chromeos/readonly-firmware-version
/sys/firmware/devicetree/base/firmware/chromeos/nonvolatile-context-storage
/sys/firmware/devicetree/base/firmware/chromeos/hardware-id
/sys/firmware/devicetree/base/firmware/chromeos/firmware-type
/sys/firmware/devicetree/base/firmware/chromeos/vboot-shared-data
/sys/firmware/devicetree/base/firmware/chromeos/nonvolatile-context-offset
/sys/firmware/devicetree/base/firmware/chromeos/firmware-version
/sys/firmware/devicetree/base/firmware/chromeos/nonvolatile-context-size
/sys/firmware/devicetree/base/firmware/chromeos/name
/sys/firmware/devicetree/base/firmware/coreboot
/sys/firmware/devicetree/base/firmware/coreboot/compatible
/sys/firmware/devicetree/base/firmware/coreboot/board-id
/sys/firmware/devicetree/base/firmware/coreboot/reg
/sys/firmware/devicetree/base/firmware/coreboot/name
/sys/firmware/devicetree/base/firmware/name
Notably, there is no #{address,size}-cells in /firmware.
This breaks any driver relying on a device under /firmware, such as the
coreboot_table driver.
This is technically an ill-formatted FDT, and so we might as well just
add the properties ourselves.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22951
Signed-off-by: Robert Marko <robimarko@gmail.com>
There are currently two header files for the dsa driver. rtl83xx.h
and rtl838x.h. It is unclear for what reason they are separated.
Especially as one always includes the other. Merge those two files
into one.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22931
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fixes:
ifxmips_aes.c: In function 'gcm_aes_decrypt':
ifxmips_aes.c:1803:14: error: assignment discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
1803 | temp = walk.src.virt.addr;
| ^
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22921
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fixes:
ltq_atm.c: In function 'ltq_atm_probe':
ltq_atm.c:1840:36: error: passing argument 2 of 'platform_set_drvdata' discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
1840 | platform_set_drvdata(pdev, ops);
| ^~~
In file included from ltq_atm.c:40:
/workspaces/openwrt/build_dir/target-mips_24kc_musl/linux-lantiq_xway/linux-6.18.21/include/linux/platform_device.h:276:47: note: expected 'void *' but argument is of type 'const struct ltq_atm_ops *'
276 | void *data)
| ~~~~~~^~~~
Fixes: c1fa85f659 ("treewide: use of_device_get_match_data")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22921
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport patch merged upstream that optimize the QDMA rx queue descriptor
setup by configuring the CPU IDX only when needed.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
It seems that upstream one of the patch had a compilation erro caused by
merging net and net-next and it was fixed silently in a merge commit.
Fix this error in the affected patch.
Fixes: 155c610962 ("airoha: backport additional patch for memory leak and multi-serdes rework")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport upstream memory leak patch merged upstream and even more
preliminary patch for multi-serdes rewrk.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Previous commits carved out some TX configuration from different places
into a dedicated function. A cause of this is a behavioral change where
the TX amplifier values aren't applied anymore if it isn't a "fiber
mode". To restore this behavior and make the media/TX-RX configuration
more generic, we need a dedicated media type. The existing ones only
cover fiber and DACs, but not the other left case where a PHY is
attached to the SerDes. This now calls set_media for USXGMII and XSGMII
modes intentionally, both to prepare for future changes and to restore
previous behavior.
We do not have a reliable way to distinct between the actually used
media types, this is still a TODO. But several parts of the code already
have different values applied based on this information. Moreover, this
is especially needed for DAC cables to work properly. While this is
missing, we need to rely on inferring the media from the SerDes mode.
While at it, improve the call site of media handling since there's a
media type for all cases now. This allows to reduce the number of
function calls by moving it out and just have the media type in the
decision block.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22814
Signed-off-by: Robert Marko <robimarko@gmail.com>
Proceed with the consolidation of TX/RX path config by carving out some
TX configuration out into a separate function. For now, this only
affects TX amplifier config. But it already slims down other polluted
call sites and brings some structure into the TX/RX path config.
While at it, already provide a similar function for RX configuration.
This does nothing yet but should be filled with RX path config later.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22814
Signed-off-by: Robert Marko <robimarko@gmail.com>
Shed some light into the darkness by giving a part of the setup a
dedicated name. This applies to the magic data blocks in the generic
setup entrypoint and some writes in the media handling. This was just
copied from the SDK which doesn't annotate this properly with
information. But we can clearly connect this with some other functions
of the SDK and extract meaningful information.
The mentioned magic blocks and register writes set coefficients of three
amplifiers in the TX path, a pre-amp, a main-amp and a post-amp. They
are used to tune the signal for different kinds of media. Generic values
are applied for all SerDes and further special values for different media
types depending on the needs.
Provide a dedicated function that sets these amplifier coefficients.
Replace the mystic register writes with the function call so one can see
at a glance what's happening. Also replace the magic TX values with the
coefficients organized into a separate struct. This might be extended
further and is also applicable for RTL930x.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22814
Signed-off-by: Robert Marko <robimarko@gmail.com>
Within RTL931x set_media, two writes are applied in general for all modes
but later again changed depending on the mode. This is a confusing
pattern. To fix this, move those generic writes into the switch-block as
a default case. To maintain behavior, pull the 10G guard into the fiber
media case.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22814
Signed-off-by: Robert Marko <robimarko@gmail.com>
Relocate the analog reset code within set_media for RTL931X to have it
in one place at the very top of the function, running all reset actions
before further real configuration is done. Also drop a separate call to
rx_reset because a subsequent sequence already includes this
functionality.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22814
Signed-off-by: Robert Marko <robimarko@gmail.com>
eip93_hmac_setkey() allocates a temporary ahash transform for
computing HMAC ipad/opad key material. The allocation uses the
driver-specific cra_driver_name (e.g. "sha256-eip93") but passes
CRYPTO_ALG_ASYNC as the mask, which excludes async algorithms.
Since the EIP93 hash algorithms are the only ones registered
under those driver names and they are inherently async, the
lookup is self-contradictory and always fails with -ENOENT.
When called from the AEAD setkey path, this failure leaves the
SA record partially initialized with zeroed digest fields. A
subsequent crypto operation then dereferences a NULL pointer in
the request context, resulting in a kernel panic:
```
pc : eip93_aead_handle_result+0xc8c/0x1240 [crypto_hw_eip93]
lr : eip93_aead_handle_result+0xbec/0x1240 [crypto_hw_eip93]
sp : ffffffc082feb820
x29: ffffffc082feb820 x28: ffffff8011043980 x27: 0000000000000000
x26: 0000000000000000 x25: ffffffc078da0bc8 x24: 0000000091043980
x23: ffffff8004d59e50 x22: ffffff8004d59410 x21: ffffff8004d593c0
x20: ffffff8004d593c0 x19: ffffff8004d4f300 x18: 0000000000000000
x17: 0000000000000000 x16: 0000000000000000 x15: 0000007fda7aa498
x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000
x11: 0000000000000000 x10: fffffffff8127a80 x9 : 0000000000000000
x8 : ffffff8004d4f380 x7 : 0000000000000000 x6 : 000000000000003f
x5 : 0000000000000040 x4 : 0000000000000008 x3 : 0000000000000009
x2 : 0000000000000008 x1 : 0000000028000003 x0 : ffffff8004d388c0
Code: 910142b6 f94012e0 f9002aa0 f90006d3 (f9400740)
```
The reported symbol eip93_aead_handle_result+0xc8c is a
resolution artifact from static functions being merged under
the nearest exported symbol. Decoding the faulting sequence:
```
910142b6 ADD X22, X21, #0x50
f94012e0 LDR X0, [X23, #0x20]
f9002aa0 STR X0, [X21, #0x50]
f90006d3 STR X19, [X22, #0x8]
f9400740 LDR X0, [X26, #0x8]
```
The faulting LDR at [X26, #0x8] is loading ctx->flags
(offset 8 in eip93_hash_ctx), where ctx has been resolved
to NULL from a partially initialized or unreachable
transform context following the failed setkey.
Fix this by dropping the CRYPTO_ALG_ASYNC mask from the
crypto_alloc_ahash() call. The code already handles async
completion correctly via crypto_wait_req(), so there is no
requirement to restrict the lookup to synchronous algorithms.
Note that hashing a single 64-byte block through the hardware
is likely slower than doing it in software due to the DMA
round-trip overhead, but offloading it may still spare CPU
cycles on the slower embedded cores where this IP is found.
Fixes: 9739f5f93b78 ("crypto: eip93 - Add Inside Secure SafeXcel EIP-93 crypto engine support")
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
[Detailed investigation report of this bug]
Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/22886
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MCU (GD32E230G8) which controls the RTL8239 POE++ PSE chips can
sometimes hang. In this case, it is necessary to to reset the chip using
the nRESET pin which is connected to the GPIO1 of the RTL8231 GPIO
expander.
For a reset, the `/sys/class/gpio/poe_mcu_reset/value` file must be set to
1 for a short period and then back to 0. After that, the poemgr must be
"restarted" to the MCU back in the expected state.
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/22916
Signed-off-by: Robert Marko <robimarko@gmail.com>
Mario Andrés Pérez
Daniel Golle
Zoltan HERPAI
Damien Dejean
Markus Stockhausen
Mieczyslaw Nalewaj
Brian Norris
Shiji Yang
Linus Walleij
Hauke Mehrtens
Christian Marangi
Rosen Penev
Eric Fahlgren
Ziyang Huang
Jonas Jelonek
Kenneth Kasilag
Sven Eckelmann