This refreshes the configuration for Linux kernel 6.12.
I first selected the cortexa7 subtarget and then refreshed the target
kernel configuration using this command:
make kernel_oldconfig CONFIG_TARGET=target
Then I selected one subtarget after the other and refreshed their
configuration using this command:
make kernel_oldconfig CONFIG_TARGET=subtarget
After this, I had to manually enable CONFIG_PCI_IMX6_HOST for the
cortexa9 subtarget.
I compared the kernel configuration used to compile the kernel from the
build directory for each subtarget before and after this task and it was
still the same.
Also rename the subtarget config files to config-6.12 as a preparation
for linux 6.18 testing support.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
[for imx6 (on Toradex i.MX6D)]
Tested-by: Zoltan HERPAI <wigyori@uid0.hu>
If input, drm or video support is enabled on imx targets, then these
will pop up.
We add them to the generic configs, because they will be dropped again
if we add them to the target config and call `make kernel_oldconfig
CONFIG_TARGET=target`.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
[for imx6 (on Toradex i.MX6D)]
Tested-by: Zoltan HERPAI <wigyori@uid0.hu>
The global flow control thresholds are left at their reset values, so
the switch starts to drop frames once 984 pages of the packet buffer
are in use. The vendor SDK raises them at initialisation, to 2592 pages
in its 8x10G profile and to 2192 pages in its larger ones.
Program the SDK values in the four global threshold registers: those of
the 8x10G profile on switches with up to 8 user ports, the others above
that.
RTL9303, pause off, TCP for 20 seconds through a port limited to
100 Mbit/s on egress: one flow is retransmitted 164 and 149 times
before and 56 and 72 times after, four flows 1480 and 1473 times
before and 291 and 294 times after, at 0.7 to 0.8 Mbit/s more
throughput. The deeper buffer raises the queueing delay at that port
from at most 20 ms to at most 58 ms.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Quinn O'Shea <qoshea@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25970
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The legacy debugfs implementation selects private diagnostic registers by
family at read time. Move these switch-wide counters into stats.c and
select immutable counter descriptors through priv->r->drop_desc.
Keep an explicit register offset for each of the 246 retained counters.
Omit the RTL838x bridge learned-entry discard counter at 0x6a9c and the
four reserved slots on RTL930x/RTL931x. All retained counters are 16-bit,
so a single OTTO_DROP macro and a common read path suffice. Correct two
RTL930x counter labels.
Expose a read-only realtek_otto_stats/drop_counters file. Serialize register
reads with reg_mutex, propagate regmap failures, and remove the debugfs
interface before switch teardown. A devm action also covers resource
cleanup; unavailable debugfs does not prevent switch operation. The fixed
root is owned by one device and is never reused by another instance.
Remove the legacy drop-counter data, reader and registrations. Other
legacy debugfs features and existing MIB exports are unchanged.
Assisted-by: ChatGPT (OpenAI GPT-6 Astra)
Link: https://github.com/openwrt/openwrt/pull/25931
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Add the stateful V4L2 encoder driver for the RKVENC v1 of the RV1126 and
RK3568 as patches 183: its binding, the PD_VEPU clock tree, the driver
and the device tree node, followed by the frequency scaling with a
cooling device and the operating points that go with it. The operating
points carry the vendor voltages, which apply once a board names the
supply of the encoder. The NPU thermal zone gets two passive trips and
cools the encoder, which lowers its clock and voltage and then its frame
rate. The zone is polled every second, since the temperature trend
decides when the cooling device is released.
Build the devfreq core and the simple_ondemand governor into the ARMv7
kernel for the frequency scaling, and let the 38x38 v10 board name
vdd_logic_npu_vepu as the supply of the encoder.
Add kmod-video-rockchip-rkvenc and install it on the Herospeed RV1126
board.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add the rkisp2 driver for the image signal processor of the RK3588 and
the RV1126, in three groups of patches:
- 180: the posted series of Xu Hongfei and Paul Elder, a driver with the
parameters and statistics nodes, its binding and the RK3588 device
tree nodes;
- 181: fixes for that series, for example the media bus code of the YUV
formats, the missing V4L2_ISP selection, the chroma resizing for 4:2:0
output, the third histogram block, the DMA segment size, the colour
space defaults and range, the reset bits of SWS_CFG and the interrupts
of the 3A blocks;
- 182: support for the ISP 2.0 of the RV1126, with its binding, the ISPP
clock tree and device tree nodes, the raw frames from the VICAP, the
white balance means of the ISP core and an IOMMU change that maps the
MMU registers non-exclusively since they lie inside the ISP range.
Add kmod-video-rockchip-isp2 and install it on the Herospeed RV1126 board.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Backport the V4L2 generic ISP types and the v4l2-isp helpers that ISP
drivers use for their parameters and statistics buffers: the two v6.19
commits and a rename that followed them, and the four v7.3 commits that
add the extensible statistics buffer, the per-block validation callback
and the statistics helpers.
Add kmod-video-v4l2-isp for the v4l2-isp module.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add two rkcif kernel patches. The first masks the MIPI interrupts that
come out of reset enabled, which kept the interrupt line asserted at
about a thousand interrupts per second until the kernel disabled it.
The second lets the RV1126 ISP take the raw frames of the VICAP without
user space: it writes the unpacked raw formats MSB aligned, keeps a
larger sizeimage set by the application and offers the MIPI stream to a
consumer through a V4L2 subdevice.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Interface naming currently depends on registration order between
stmmac instances, which is non-deterministic when multiple probes
race at boot (e.g. two independent GMACs with no shared switch).
This causes eth0/eth1 to swap randomly across reboots on some
platforms.
Force the netdev name to match the "ethernetN" DT alias when one is
present. plat->bus_id cannot be used for this: stmmac_platform.c
falls back to a driver-global counter when of_alias_get_id() finds
no alias, so plat->bus_id is never negative and every stmmac netdev
would be forced, including boards with no alias at all. Re-read the
alias directly from the device's OF node instead, and only force the
name when it actually resolves. Fall back to the original
auto-numbering template if the forced name collides.
unifi-ac-hd already has a correct alias mapping, so the preinit
eth0/eth1 swap hack for it is no longer needed. Drop it.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/25143
Signed-off-by: Robert Marko <robimarko@gmail.com>
G10 and WPQ864 alias ethernet1 to &gmac0, which is never enabled on
either board; the GMAC that actually is enabled, gmac2, has no
alias. The following commit will force netdev naming from the DT alias,
so point ethernet1 at gmac2 to keep both active GMACs aliased.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/25143
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add the TX completion, RX fill and RX descriptor interrupts of ring
sets 22/6/14, 21/5/13 and 20/4/12. The lines count down from the first
set's: TX completion ring n is SPI 355 + n, RX fill ring n SPI 347 + n
and RX descriptor ring n SPI 331 + n, each read from the GIC pending
state on a Linksys MR7350 with only that ring's interrupt unmasked.
Link: https://github.com/openwrt/openwrt/pull/25663#issuecomment-6194790602
Assisted-by: Claude:claude-opus-5
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/25663
Signed-off-by: Robert Marko <robimarko@gmail.com>
The PPE spreads unicast to the CPU by its RSS hash over four switch
queues from each of three bases, and the EDMA queue-to-ring table
decides which receive ring each hash bucket feeds. Offer that table as
the ethtool RSS indirection table, so that "ethtool -X" can weight or
narrow the spread. The hash key is not offered: the PPE hash is not
Toeplitz and its seed is a PPE register.
On IPQ8074 with four rings and 3000 datagrams in 64 flows to the CPU,
"equal 2" leaves rings 2 and 3 and "weight 1 0 0 1" leaves rings 1 and
2 without a receive interrupt (n=3).
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/25663
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add the TX completion, RX fill and RX descriptor interrupts of ring
sets 6/6/14, 5/5/13 and 4/4/12. The lines count down from the first
set's: TX completion ring n is SPI 352 - n, RX fill ring n SPI 360 - n
and RX descriptor ring n SPI 376 - n, each read from the GIC pending
state with only that ring's interrupt unmasked.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/25663
Signed-off-by: Robert Marko <robimarko@gmail.com>
The driver uses one RX and one TX ring set, so all traffic through the
host is handled by one CPU. Use up to four ring sets, as many as the
device tree gives interrupts for, counting down from the rings in the
SoC data. Each set has one NAPI context for its TX completions and RX,
its own page pool and TX queue; XPS maps TX queue n to CPU n, and the
switch queues map onto the RX rings through QID2RID. The regmap runs
without its lock, since a ring's registers are only touched from its
own NAPI or under its TX lock, and threaded NAPI starts at the first
open so that packet steering can pair each NAPI thread with its queue.
ethtool -l/-L reports and changes the number of ring sets.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/25663
Signed-off-by: Robert Marko <robimarko@gmail.com>
Out of reset the RSS hash puts every flow in the same bucket, so the
RX hash qca_edma reports is the same for every frame and RPS cannot
spread the receive work. Program the hash, and spread unicast to the
CPU port over four queues from each of its queue bases 0, 4 and 8 by it.
Queues 0 to 11 share one priority and one DRR node. Only queues 0, 4 and
8 carried unicast before.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/25663
Signed-off-by: Robert Marko <robimarko@gmail.com>
A port that joins an 802.1ad bridge on a switch with the provider role
now takes that role: S-TAGs are parsed, frames are switched on the outer
VID, the VLAN table controls the outer tag and the customer's inner tag
crosses the switch unchanged. Leaving the bridge restores the 802.1Q
role, and enabling the port reapplies its role instead of resetting it.
The bridge protocol is fixed while switch ports are offloaded: a change
is refused through port_vlan_protocol, as mlxsw does, instead of leaving
the hardware on the old protocol. The VLAN table is shared by all
bridges, so a VID belongs to the protocol of the first bridge that adds
a user port to it, and the other protocol is refused until no user port
is left in it.
Switches without the provider role still refuse 802.1ad bridges, now
at join as well, and refuse a change to 802.1ad of a bridge that holds
their ports.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Quinn O'Shea <qoshea@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25927
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
DSA ignores SWITCHDEV_ATTR_ID_BRIDGE_VLAN_PROTOCOL, so a bridge that
changes its VLAN protocol while switch ports are offloaded keeps them
running the old one without telling the driver. Carry a kernel patch
that adds an optional port_vlan_protocol operation for that attribute;
drivers without it behave as before.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Quinn O'Shea <qoshea@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25927
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
RTL930x classifies and tags with a pool of four outer/inner TPID pairs
and per-port compare masks. The driver never programs them and keeps
what reset or the boot loader left: on RTL9303 every pair reads 0x88a8
outside and 0x8100 inside, but no port compares outer TPIDs, so the
switch never recognises an S-TAG.
Set every TPID pair to 0x88a8 outside and 0x8100 inside, parse only
C-TAGs on user ports, and parse S-TAGs on the CPU port as well, so a
frame the CPU injects with an S-TAG is switched on its outer VID. Add a
provider role for a port: S-TAG parsing, forwarding on the outer VID,
the outer tag taken from the VLAN table on egress with the 0x88a8 TPID,
and the inner tag kept unchanged in both directions. Leaving the role
restores the 802.1Q posture, including the reset value of the egress
TPID control.
Nothing selects the provider role yet.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Quinn O'Shea <qoshea@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25927
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The VLAN code still uses raw switch register accessors despite the
regmap already available in the switch private data.
Replace direct register accesses with regmap operations through
priv->map. Pass priv to the VLAN profile, port forwarding, tag status
and PVID callbacks of all four families, updating their declarations
and callers accordingly. Read the profile registers before printing
them in the RTL839x and RTL930x profile dumps.
Use regmap_write_bits() to preserve unconditional masked writes; the
set bits lie within the mask in every case, which keeps sw_w32_mask()
semantics.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Quinn O'Shea <qoshea@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25927
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Backport the upstream Airoha Ethernet LRO implementation for EN7581 and
AN7583.
Use the eight dedicated hardware LRO queues mapped to RX queues 24-31.
Adjust the RX page pool configuration for LRO queues and provide the GSO
metadata required to correctly re-segment forwarded aggregated packets.
Since LRO is configured per QDMA block, expose NETIF_F_LRO only when a
single device uses the QDMA, and update the feature during device
registration and runtime QDMA migration.
Link: https://patch.msgid.link/20260909-airoha-eth-lro-v7-1-e6317be79067@kernel.org
Signed-off-by: Yalei Zang <yalei.zang@airoha.com>
Link: https://github.com/openwrt/openwrt/pull/25901
Signed-off-by: Robert Marko <robimarko@gmail.com>
Describe fixed split-PHY topology with an optional qcom,split-phy property
on the PCIe radio. Read it only for QCN9274 hw2.0 when the OTP board
identifier is zero or erased, before target capability discovery.
Valid OTP remains authoritative. Devices without the property and other
hardware revisions retain their existing behavior. Leave QMI capability
handling and WMI mode selection unchanged. Do not match router identities
inside ath12k.
Include the proposed binding and driver handling together; board selection
is separate. The binding is an RFC for maintainer review.
Source checks covered OTP field values, absent inputs, per-device isolation,
patch refresh and schema validation. LN6001 startup also exercised the
unset-OTP property path in the attended test.
Signed-off-by: Satoshi Ikeuchi <satosan.ikm@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25595
Signed-off-by: Robert Marko <robimarko@gmail.com>
Enable the existing secure WCSS driver and describe the shared IPQ9574
remoteproc, reserved memory and interprocessor communication resources.
Keep the remoteproc node disabled until enabled by a board.
Use SCM/PAS for startup instead of extending the native WCSS driver with
manual clock and reset sequencing. Load q6_fw.mdt and the auxiliary
m3_fw.mdt from the IPQ9574 ath11k-firmware package added in this series.
With board enablement applied separately, secure WCSS startup and ath11k
registration passed on LN6001. An attended iPhone test passed association,
DHCP and four local pings on each of 2.4, 5 and 6 GHz with all three APs
enabled, using that unit's factory calibration.
Signed-off-by: Satoshi Ikeuchi <satosan.ikm@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25595
Signed-off-by: Robert Marko <robimarko@gmail.com>
Move the secure WCSS driver, binding and split-firmware support from
qualcommax to the common kernel patch series. IPQ9574 support is already
provided by this driver.
Split out the unchanged TME-L client header so qualcommbe can compile the
driver without enabling the mailbox controller. Keep the qualcommax-only
follow-up patches in that target; its resulting driver is unchanged.
Describe the existing multi-file loading interface in the common binding
and leave the driver disabled unless selected by a target.
Signed-off-by: Satoshi Ikeuchi <satosan.ikm@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25595
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Xunison Exigo Hub D50 5G is a 5G/LTE router with Wi-Fi 6. It is also
sold as the Zearts D50 5G.
Specifications:
SoC: Qualcomm IPQ5018, dual-core Cortex-A53 @ 1.0 GHz
RAM: 512 MiB
Flash: 128 MiB SPI NAND (ESMT F50D1G41LB)
WLAN: IPQ5018 2.4 GHz, QCN9074 5 GHz (PCIe), both 802.11ax
Ethernet: 1x GbE WAN (IPQ5018 internal GE PHY, gmac0)
3x GbE LAN (QCA8337 switch, SGMII to gmac1)
WWAN: Quectel RM500Q-AE, 5G Sub-6 / LTE Cat 16, on USB 2.0 and
PCIe
Buttons: reset, WPS
LEDs: MESH (green/red), 5G (green/red), 4G, WiFi, Internet, WAN;
power is hardwired
Power: 12 V / 2 A DC
Serial: 115200 8N1, 4-pin header JP1 next to SW4 on the main board,
from pin 1: VCC, TX, RX, GND
Notes:
- WAN is gmac0 wired straight to the internal GE PHY, not a switch
port; its netdev is named wan by the label property.
- The console RX line (gpio20) is pulled up. Left floating with nothing
on the header it causes an interrupt storm and, on some units, a hang
at boot.
- USB is 2.0 only: the controller is limited to the HS PHY and clocks
its pipe from UTMI. The 5 V supply for the port and the modem is
switched by gpio24 (active low).
- MACs follow the stock firmware: LAN uses 0:art 0x0, WAN 0:art 0x6.
The label has no MAC printed, so there is no label-mac-device.
- Wi-Fi calibration data and MAC addresses come from 0:art through
nvmem cells on the Wi-Fi nodes (calibration: IPQ5018 at 0x1000,
QCN9074 at 0x26800). The caldata holds the Qualcomm placeholder MAC,
so the radios take the 0:art 0x0 MAC + 2 and + 3 instead.
- Board data for both radios is submitted separately to
firmware_qca-wireless under the calibration variant
Xunison-Exigo-Hub-D50-5G, both taken from the stock firmware:
bdwlan.b24-brax for the IPQ5018 and qcn9000/bdwlan.ba0 for the
QCN9074. The brax file is the vendor's board variant; on my unit it
outperformed the bdwlan.b24 that the stock firmware loads.
- The modem power line (gpio31) has no consumer and is kept high with a
GPIO hog.
- The Internet LED is lit while the modem's wwan0 is up. The WiFi LED
uses the network trigger in link mode, so it is lit while an AP is up
on either radio; the phyNradio triggers never light it with ath11k on
this board. The 4G and 5G LEDs have no trigger, as nothing in the
kernel reports the modem's access technology.
Modem:
The RM500Q-AE is wired to both USB and PCIe, and its data_interface
setting selects which one carries data. The stock firmware leaves it on
PCIe (data_interface 1,0) and this port uses it there, so no AT command
is needed after installing. It is driven by mhi-pci-generic with MBIM:
data on wwan0, control on /dev/wwan0mbim0 and AT commands on
/dev/wwan0at0. No modem interface is preconfigured; add one with the
"mbim" protocol on /dev/wwan0mbim0.
Installation:
The factory image is a raw UBI image for the U-Boot web recovery.
1. Power the router off, hold the reset button and power it on. Keep
holding until the Internet LED stays lit (about 10 seconds).
2. Set a computer on a LAN port to 192.168.1.2/24 and open
http://192.168.1.254
3. Upload openwrt-qualcommax-ipq50xx-xunison_exigo-hub-d50-5g-squashfs-factory.img
and wait for the router to reboot.
Later upgrades use the sysupgrade image.
The port started from George Moussalem's device support in the 4IceG
OpenWrt tree, with the device tree reworked by Lukasz Szczur (LS3434):
USB, the modem supply and the NAND/sysupgrade layout. Thanks to Hostle
for the flashing work on this board and to Rafał Wabik (4IceG) for the
tree it was developed in.
Link: https://forum.openwrt.org/t/adding-support-for-xunison-exigo-d50-5g-zearts-d50-5g-ipq5018/247016
Co-developed-by: George Moussalem <george.moussalem@outlook.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Co-developed-by: Lukasz Szczur <8sdasfasfas@royaleplaysempire.com>
Signed-off-by: Lukasz Szczur <8sdasfasfas@royaleplaysempire.com>
Co-developed-by: Rafał Wabik <4rafal@gmail.com>
Signed-off-by: Rafał Wabik <4rafal@gmail.com>
Signed-off-by: Steve Meek <stevemeek82@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25890
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add a pending patch that gives the RM500Q-AE its own MHI channel table
with doorbell burst mode disabled on its two hardware data channels.
With burst mode on, the downlink stalls under sustained multi-stream
load when the wwan0 receive work runs on the same CPU as the modem's
interrupt, which is where the default packet steering puts it. Uplink
keeps working, the MBIM control channel later times out, and only a
reboot recovers it. Ringing the channel doorbell by hand restores the
link at once, which points at a lost doorbell-mode handshake.
Tested on a Xunison Exigo Hub D50 5G: without the patch a single
25-second 16-stream download stalled the downlink; with it, about 200
seconds of multi-stream downloads with CPU0 at up to 100% ran with no
stall and no MHI errors.
Link: https://patch.msgid.link/20261013-rm500q-db-burst-v1-1-bb850d54e2c4@gmail.com
Signed-off-by: Steve Meek <stevemeek82@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25890
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport the Airoha Ethernet patches for Linux 6.18. They fix PPE flush
error handling, QDMA retry handling, BQL accounting on the shared TX ring,
DMA mapping of fragmented packets, and maximum receive size configuration.
The series also fixes MIB and ETS/QoS statistics, corrects the module
license, renames the device flags, and adds preliminary TX hardware
configuration changes.
Signed-off-by: Yalei Zang <yalei.zang@airoha.com>
Link: https://github.com/openwrt/openwrt/pull/25861
Signed-off-by: Robert Marko <robimarko@gmail.com>
To reduce code duplication across different AN7583 evaluation boards,
introduce a shared multi-EVB base device tree and utilize Device Tree
Overlays (DTSO) for board-specific configurations.
Signed-off-by: Yalei Zang <yalei.zang@airoha.com>
Link: https://github.com/openwrt/openwrt/pull/24926
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
To reduce code duplication across different AN7581 evaluation boards,
introduce a shared multi-EVB base device tree and utilize Device Tree
Overlays (DTSO) for board-specific configurations.
Signed-off-by: Yalei Zang <yalei.zang@airoha.com>
Link: https://github.com/openwrt/openwrt/pull/24926
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The rtl931x LED setup always selects serial mode. Boards whose port LEDs
are wired for scan mode stay dark with it. The rtl930x driver already
reads the interface mode from "realtek,led-mode"; read it on rtl931x
too.
Without the property the driver selects serial mode, as before. A value
outside 1-3 is reported and also falls back to serial mode. No rtl931x
DTS sets the property yet, so other boards are unchanged.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Kaloyan Naumov <knaumov@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/25576
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
The rtl931x LED setup always selects serial mode. Boards whose port LEDs
are wired for scan mode stay dark with it. The rtl930x driver already
reads the interface mode from "realtek,led-mode"; read it on rtl931x
too.
Without the property the driver selects serial mode, as before. A value
outside 1-3 is reported and also falls back to serial mode. No rtl931x
DTS sets the property yet, so other boards are unchanged.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Kaloyan Naumov <knaumov@gmail.com>
A flower rule with action trap redirects its frames to the CPU port.
Their CPU tag has no trap REASON, only ACL_HIT and the rule's PIE row
in ACL_IDX, so they are passed up as forwarded by hardware: they get
offload_fwd_mark and the bridge keeps them off the other switch ports,
where the hardware did not send them either.
L3 rules sit in PIE rows 640 and above and set ACL_HIT on the frames
they send to the CPU too. Those must keep the mark: they are addressed
to the switch, and the bridge has no FDB entry for an interface with
its own MAC, so it would flood them. Treat a frame as trapped only
when ACL_HIT comes from a row below the L3 rules. Only RTL839x uses
rteth_839x_decode_tag(), so the other families are unchanged.
HPE 1920-48G (RTL8393), h7 behind lan48 and x7 behind lan47 in one
VLAN, a skip_sw trap rule for x7 on lan48: none of 8 pings reach x7
on main, 8 of 8, once each, with this change. Broadcast ARP still
reaches x7 once, also with a mirror rule on it. Pings to an interface
with its own MAC leave nothing on lan47, as on main; a bench build
that took any ACL_HIT as a trap had all 8 flooded there. One change
is visible: a trap rule for such an interface now gets its frames
flooded out of lan47 by the bridge, where main keeps them at the CPU.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Gennaro Cimmino <gcimmino@rayonra.net>
Link: https://github.com/openwrt/openwrt/pull/25919
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The ethernet driver is about to tell a frame that a tc rule sent to the
CPU from one that an L3 rule sent there, and only the PIE row in the
CPU tag tells them apart. Move RTL839X_PIE_L3_FIRST to a new shared
header, include/linux/soc/realtek/otto_common.h, and derive the number
of L3 rows from it. Both values stay as they were, 640 and 512.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Gennaro Cimmino <gcimmino@rayonra.net>
Link: https://github.com/openwrt/openwrt/pull/25919
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
On MDIO-connected MT753x switches .get_stats64 reads the MIB counters
under the MDIO bus mutex although it runs in atomic context, so reading
/proc/net/dev reports "sleeping function called from invalid context".
With CONFIG_DEBUG_ATOMIC_SLEEP=y the sleep inside the RCU read section
can lock up a CPU. The upstream fix polls the counters from a delayed
work and returns cached values. It is in mainline from v7.1-rc3 and not
in 6.18.y.
Tested on a Keenetic KN-1012 (MT7981B, MT7531) with
CONFIG_DEBUG_ATOMIC_SLEEP=y: a loop reading /proc/net/dev locked up a
CPU within a minute without the fix, and ran 41 minutes clean with it
while the counters kept advancing.
Assisted-by: LLM
Signed-off-by: Aleksei Sviridkin <f@lex.la>
Link: https://github.com/openwrt/openwrt/pull/25383
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
This patch adds support for Wavlink WS-WN552K1-C, also available under
other names:
EXTRALINK Dynamite C21, Renkforce RF-WMH-310 (RF-WMH-320).
Hardware specifications:
* SoC: MediaTek MT7621AT, 2C2T, 880 MHz
* RAM: 128 MB DDR3, Nanya NT5CB64M16GP-EK
* Flash: 16 MB SPI NOR flash, GigaDevice GD25Q127CSIG
* 5 GHz WiFi: MediaTek MT7615N (4x4:4) on mini PCIe slot
* 2.4 GHz WiFi: MediaTek MT7603EN (2x2:2) on mini PCIe slot
* Ethernet: 3x 1000Base-T
* LEDs: Power, dual-color WAVLINK logo LED on the top cover
* Buttons: Reset, WPS, Turbo, and touch button on the top cover via
RH6015C touch sensor
* UART: UART1 serial console (57600 8n1) on the J4 header located below
the top heatsink
* USB: 1x USB 2.0
Installation:
Flashing instructions (U-Boot TFTP):
1. Configure a TFTP server on your computer and set its IP address to
192.168.10.100.
2. Rename the OpenWrt sysupgrade image to firmware.bin and place it in
the root directory of the TFTP server.
3. Power off the device and connect an Ethernet cable from one of its
LAN ports to your computer.
4. Press and hold the Reset button.
5. Power on the device.
6. After a few seconds, when the connected LAN port LED stops blinking
rapidly, release the Reset button.
7. Flashing OpenWrt takes less than a minute and the device will reboot
automatically.
8. After reboot, the WAVLINK logo on the top cover indicates the current
OpenWrt status. Wait until the logo turns solid blue.
Revert to the OEM firmware:
U-Boot TFTP:
Follow the flashing instructions above and use the firmware.bin OEM
backup image.
OpenWrt "Flash Firmware" interface:
Upload the firmware.bin OEM backup image and select "Force update"
before continuing.
MAC address layout:
The MAC address shown on the label on the back of the device is assigned
to the 2.4 GHz WiFi adapter.
MAC addresses assigned by the OEM firmware:
* 2.4 GHz: *:XX (label) — factory@0x0004
* 5 GHz: *:XX + 1 — factory@0x8004
* WAN: *:XX - 1 — factory@0xe006
* LAN: *:XX - 2 — factory@0xe000
Signed-off-by: pawel mistrzuu <pawelm@murena.io>
Link: https://github.com/openwrt/openwrt/pull/25196
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
The Fibocom FG621-EA supplies a fresh locally-administered address in its
CDC-NCM descriptor on every power-up, so usb0 changes identity across
reboots. Five consecutive boots on the same unit:
cdc_ncm 1-1:1.0: MAC-Address: d6:c4:81:03:15:77
cdc_ncm 1-1:1.0: MAC-Address: 26:aa:4f:6c:ad:ff
cdc_ncm 1-1:1.0: MAC-Address: 16:46:a8:94:fd:29
cdc_ncm 1-1:1.0: MAC-Address: 46:ad:de:0f:82:d8
cdc_ncm 1-1:1.0: MAC-Address: ea:fa:1a:b7:c9:dc
The kernel reports these as permanent rather than random
(addr_assign_type 0), because they are read from the device instead of
being generated by the host, so nothing downstream compensates for them.
Assign a stable address derived from the factory base instead. Offsets 0,
1 and 4 are already used by the LAN ports and phy0, the WAN port, and
phy1 respectively, so use offset 3.
Tested on hardware (HW rev A1). An LTE data session still passes traffic
in both directions with usb0 pinned: 5/5 ICMP replies at 1400 bytes and a
274 kB HTTP transfer, with downlink byte counts matching an unpinned run
on the same unit (293 kB vs 294 kB). This modem therefore learns the host
MAC from uplink frames rather than filtering to the address it advertised
in its own descriptor.
Note this does not change the address the carrier hands out: with usb0
pinned, the PDP address still differs between sessions, as it is issued
per context activation and does not depend on the host-side MAC of the
USB link.
Signed-off-by: Fredrik Hallin <fredappsdev@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/24975
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
The device tree exports reboot:modem and reset:modem, but without a UCI
switch they cannot be reached from LuCI or enforced at boot. Add them,
following the teltonika,rutm* precedent. The defaults match the output
values already set in the device tree.
Signed-off-by: Fredrik Hallin <fredappsdev@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/24975
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
The device tree declares twelve LEDs but nothing drives them, as the board
has no 01_leds entry at all. Wire up the WAN and mobile indicators.
The mapping was verified against the vendor firmware, which drives GPIO 15
(white:wan) high when the wired WAN is online and GPIO 10 (white:mobile)
high on an LTE connection.
Signed-off-by: Fredrik Hallin <fredappsdev@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/24975
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
Martin Schiller
Quinn O'Shea
Rustam Adilov
Markus Stockhausen
Sander van Deijck
Daniel Golle
Mieczyslaw Nalewaj
Julius Bairaktaris
Yalei Zang
Satoshi Ikeuchi
Steve Meek
Kaloyan Naumov
Jonas Jelonek
Gennaro Cimmino
Aleksei Sviridkin
pawel mistrzuu
Fredrik Hallin