mirror of
https://github.com/openwrt/openwrt.git
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Shiji Yang
9cf794cff1
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.12.91
Remove upstreamed patches:
- airoha/patches-6.12/017-v6.13-net-airoha-Implement-BQL-support.patch[1]
- airoha/patches-6.12/138-v7.1-net-airoha-Add-missing-RX_CPU_IDX-configuration-in-a.patch[2]
- airoha/patches-6.12/149-v7.1-net-airoha-Move-ndesc-initialization-at-end-of-airoh.patch[3]
- generic/backport-6.12/940-v7.1-net-dsa-realtek-rtl8365mb-fix-mode-mask-calculation.patch[5]
Manually rebased patches:
- airoha/patches-6.12/048-01-v6.15-net-airoha-Move-airoha_eth-driver-in-a-dedicated-fol.patch[1]
- ath79/patches-6.12/800-leds-add-reset-controller-based-driver.patch[4]
- bcm27xx/patches-6.12/950-0122-bcmgenet-Better-coalescing-parameter-defaults.patch[6]
We also backported four patches to fix perf tool regression:
- generic/backport-6.12/216-01-revert-perf-cgroup-update-metric-leader-in-evlist__e.patch
- generic/backport-6.12/216-02-revert-perf-tool_pmu-fix-aggregation-on-duration_tim.patch
- generic/backport-6.12/216-03-revert-perf-python-add-parse_events-function.patch
- generic/backport-6.12/216-04-revert-perf-tool_pmu-factor-tool-events-into-their-o.patch
All other patches are automatically refreshed.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.91&id=ca24fcac1daaa5e8a667981d81986a3eb4b9fb04
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.91&id=f00037a99bc2332ef59dc85298b98b20af165904
[3] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.91&id=d36be272adda7f313e39dd118086955d993bf6a7
[4] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.91&id=07d3611389ba7d78b80ea360a42ce32ab2521fbc
[5] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.91&id=3354d6c62fd4baa7b32cbd80cc5a8aa3f2bd0656
[6] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.91&id=b84351dcc359667bc952131c1424b692ec83dce2
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/23444
(cherry picked from commit 8f638f9366)
Link: https://github.com/openwrt/openwrt/pull/23538
[Adapted to patches in 25.12]
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
41 lines
1.8 KiB
Diff
41 lines
1.8 KiB
Diff
From fa478c29cc5c23ff083fe34d2309265fee9acaa9 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Thu, 19 Sep 2024 18:05:00 +0100
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Subject: [PATCH] dmaengine: dw-axi-dmac: Allow client-chosen width
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For devices where transfer lengths are not known upfront, there is a
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danger when the destination is wider than the source that partial words
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can be lost at the end of a transfer. Ideally the controller would be
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able to flush the residue, but it can't - it's not even possible to tell
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that there is any.
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Instead, allow the client driver to avoid the problem by setting a
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smaller width.
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
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+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
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@@ -769,6 +769,18 @@ static int dw_axi_dma_set_hw_desc(struct
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case DMA_DEV_TO_MEM:
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reg_burst_msize = axi_dma_encode_msize(chan->config.src_maxburst);
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reg_width = __ffs(chan->config.src_addr_width);
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+ /*
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+ * For devices where transfer lengths are not known upfront,
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+ * there is a danger when the destination is wider than the
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+ * source that partial words can be lost at the end of a transfer.
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+ * Ideally the controller would be able to flush the residue, but
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+ * it can't - it's not even possible to tell that there is any.
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+ * Instead, allow the client driver to avoid the problem by setting
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+ * a smaller width.
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+ */
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+ if (chan->config.dst_addr_width &&
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+ (chan->config.dst_addr_width < mem_width))
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+ mem_width = chan->config.dst_addr_width;
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device_addr = phys_to_dma(chan->chip->dev, chan->config.src_addr);
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ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
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mem_width << CH_CTL_L_DST_WIDTH_POS |
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