Frequency scaling lets MT7620 reduce the CPU clock after a MIPS
SI_Sleep signal. The clock framework does not observe that change and
continues reporting the boot frequency. This breaks timekeeping, delay
calibration, and timing-sensitive users such as the Jitter RNG.
Remove the MT7620 autosleep callback and its elevated systick rating
from the local timer patch. Clear SLEEP_EN during early MT7620
initialization so the result does not depend on reset state or on what a
bootloader left behind. Use the generic systick compatible in the
MT7620A and MT7620N DTS files.
With CPU frequency scaling removed, the MIPS Count Register is again a
reliable clock source. Systick drops to rating 200 for both the
clocksource and the clockevent, so cevt-r4k (rating 300) takes the
clockevent and the now-reliable MIPS count register (rating ~229 here)
takes the clocksource.
Hardware testing used OpenWrt 25.12.5 with Linux 6.12.94 on an MT7620A
WE826. Before the change, urngd occupied 92 to 100 percent of otherwise
idle CPU for several minutes after each boot. After the change, urngd
initialized without the prolonged load. Ethernet, WireGuard, warm boot,
mixed-load stability, and 30-minute clock drift tests showed no
regression.
The change was rebased onto main with Linux 6.18.44. The complete ramips
patch stack applies cleanly, checkpatch reports no issues, and the
modified timer-ralink and mt7620 objects compile with the OpenWrt MIPS
toolchain.
This revives Shiji Yang's original 2023 patch with current hardware
results and makes the disabled state independent of the bootloader.
Link: https://lists.openwrt.org/pipermail/openwrt-devel/2023-July/041232.html
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Tested-by: Gleb Pesin <dormancygrace@gmail.com>
Signed-off-by: Gleb Pesin <dormancygrace@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/24734
Signed-off-by: Robert Marko <robimarko@gmail.com>
Shiji Yang
8212dc5491