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Each board wires one reset line that resets the AQR113C PHYs as a group: GPIO 71 on SDG-8733/SDG-8734 and GPIO 62 on SDG-8733A. Describe that line as the MDIO bus reset with the same assert and deassert times. Drop the per-PHY reset-gpios. On SDG-8733 the second AQR113C claimed GPIO 62, which is not connected on that board. Signed-off-by: Chad Monroe <chad@monroe.io> Link: https://github.com/openwrt/openwrt/pull/24352 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>