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The nRESET pins of the RTL8224 PHY on the MCX3 are wired to GPIO6 of the SoC, but this was never described in the devicetree. Commitc99a30668d("realtek: add RTL8224 initialization to Realtek driver") introduced support for reinitializing RTL8224 PHYs, and commit084da38a2e("realtek: mdio: activate multiple busses") allowed the MDIO bus provider load the devicetree properties to the bus, including reset descriptors. With both in place, a bus level PHY reset via the hardware pin is now correctly triggered before reinitialization. Add the missing reset-gpios property so the PHY can be reset via the hardware pin. Signed-off-by: Sven Eckelmann <sven@narfation.org> Link: https://github.com/openwrt/openwrt/pull/22966 Signed-off-by: Robert Marko <robimarko@gmail.com>