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qualcommax: qca_ppe: enable TX pause on an XGMAC port

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ppe_xgmac_link_up() masked PPE_XGMAC_TX_FLOW_ENABLE (bit 1) but wrote
PPE_XGMAC_RX_FLOW_ENABLE (bit 0) as the value, so val & mask was always
zero and TX pause never enabled on an XGMAC port regardless of what phylink
negotiated. The receive side beside it is correct and is what makes the
pair the evidence.

Only ports muxed to their XGMAC are affected - the 10G AQR ports on other
boards. Found by inspection; there is no XGMAC port on the bench to run it
on.

Fixes: 142104bb90 ("qualcommax: add PPE driver")
Assisted-by: Claude:claude-opus-5
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/25084
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Julius Bairaktaris authored and Robert Marko committed 2026-09-09 21:00:02 +02:00
1 parent 8990769d1f
commit 00e31226cd
1 file changed
+1 -1
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target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c
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@@ -149,7 +149,7 @@ static void ppe_xgmac_link_up(struct qca_ppe_priv *priv, int port,
regmap_write_bits(priv->regmap, PPE_XGMAC_TX_FLOW_CTRL(xgmac),
PPE_XGMAC_TX_FLOW_ENABLE,
tx_pause ? PPE_XGMAC_RX_FLOW_ENABLE : 0);
tx_pause ? PPE_XGMAC_TX_FLOW_ENABLE : 0);
regmap_write_bits(priv->regmap, PPE_XGMAC_RX_FLOW_CTRL(xgmac),
PPE_XGMAC_RX_FLOW_ENABLE,