openwrt-mirror/openwrt
1
0 Fork 0
mirror of https://github.com/openwrt/openwrt.git synced 2026-10-22 15:18:44 +04:00
Code Issues Packages Projects Releases Wiki Activity

realtek: pcs: rtl930x: limit clock-ready polling to 10G SerDes

Browse Source 
The clock-ready debug readback is used by the SDK's 10G SerDes setup
sequence. Restrict polling to 10G-type SerDes while retaining the
existing exclusion for OFF mode.

This avoids applying the check to the 5G QSGMII SerDes 0 and 1, which can
report clock synchronization failures despite working links.

Assisted-By: ChatGPT (OpenAI GPT-6.1 Sol)
Link: https://github.com/openwrt/openwrt/pull/25882
Signed-off-by: Jonas Jelonek <jonas@jonasjelonek.de>
This commit is contained in:
Jonas Jelonek committed 2026-10-19 09:35:04 +02:00
1 parent 29a7121781
commit 27d97aa507
1 file changed
+2 -1
Download Patch File Download Diff File Expand all files Collapse all files
target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c
+2 -1
View File
@@ -2303,7 +2303,8 @@ static int rtpcs_930x_sds_set_mode(struct rtpcs_serdes *sds, enum rtpcs_sds_mode
if (ret)
return ret;
if (hw_mode != RTPCS_SDS_MODE_OFF && rtpcs_930x_sds_wait_clock_ready(sds))
if (sds->type == RTPCS_SDS_TYPE_10G && hw_mode != RTPCS_SDS_MODE_OFF &&
rtpcs_930x_sds_wait_clock_ready(sds))
dev_err(sds->ctrl->dev, "SerDes %d could not sync clock\n", sds->id);
if (rtpcs_930x_sds_init_state_machine(sds, hw_mode))