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realtek: make Zyxel XMG1915-10E generic for whole family
The XMG1915 is a switch family with multiple variants sharing nearly all hardware (same SoC, PHYs, SFP cages, LEDs) and mainly differing in PoE and minor details. In preparation for adding further variants, move the bulk of the device tree into a shared rtl9302_zyxel_xmg1915.dtsi and reduce the per-device dts to the device identity (compatible, model) plus any variant-specific nodes. For images, factor a Device/zyxel_xmg1915 template holding the shared build settings so per-device definitions only need DEVICE_MODEL. No functional change for XMG1915-10E. Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/23218 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Jonas Jelonek
committed by
Robert Marko
Robert Marko
parent
24aeb5cc09
commit
426b1a97ac
@@ -1,8 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "macros.dtsi"
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#include "rtl930x.dtsi"
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#include "rtl9302_zyxel_xmg1915.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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@@ -11,270 +10,4 @@
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/ {
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compatible = "zyxel,xmg1915-10e", "realtek,rtl9302c-soc";
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model = "Zyxel XMG1915-10E Switch";
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aliases {
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label-mac-device = ðernet0;
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led-boot = &led_pwr_sys_green;
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led-failsafe = &led_pwr_sys_red;
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led-running = &led_pwr_sys_green;
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led-upgrade = &led_pwr_sys_green;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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led_pwr_sys_green: led-0 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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led_pwr_sys_red: led-1 {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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};
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led_set: led_set {
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compatible = "realtek,rtl9300-leds";
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active-low;
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/* Copper */
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led_set0 = <(RTL93XX_LED_SET_100M | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_100M |RTL93XX_LED_SET_1G |
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RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)>;
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/* SFP+ */
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led_set1 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_2P5G |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_2P5G |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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/* PoE and Cloud are 4 leds in total but software managed.
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Assign them to led_set 1 to avoid shifting the others
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incorrectly. */
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realtek,led-set1-force-port-mask = <0x01800000>;
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};
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keys {
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compatible = "gpio-keys";
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mode {
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label = "restore";
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gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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};
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sfp0: sfp-p9 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p10 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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};
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};
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&i2c_mst1 {
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status = "okay";
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/* i2c of the left SFP+ cage seen from the front; port 9 */
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i2c0: i2c@0 {
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reg = <0>;
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};
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/* i2c of the right SFP+ cage seen from the front; port 10 */
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i2c1: i2c@1 {
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reg = <1>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bootbase";
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reg = <0x0 0x80000>;
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read-only;
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x7e000>;
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};
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partition@7e000 {
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label = "u-boot-env2";
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reg = <0x7e000 0x1000>;
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};
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partition@7f000 {
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label = "mrd";
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reg = <0x7f000 0x1000>;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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/* 12 addresses are available */
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macaddr_factory: macaddr@ff8 {
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compatible = "mac-base";
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reg = <0xff8 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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};
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partition@80000 {
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label = "reserved";
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reg = <0x80000 0x1e0000>;
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read-only;
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};
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partition@260000 {
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label = "factory";
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reg = <0x260000 0x1da0000>;
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "loader";
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reg = <0x0 0x10000>;
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};
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partition@10000 {
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label = "firmware";
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reg = <0x10000 0x1d90000>;
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compatible = "openwrt,uimage", "denx,uimage";
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};
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};
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};
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};
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};
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&mdio_bus0 {
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/* External RTL8224 PHY */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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enet-phy-pair-order = <0>;
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enet-phy-pair-polarity = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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compatible = "ethernet-phy-ieee802.3-c45";
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enet-phy-pair-order = <0>;
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enet-phy-pair-polarity = <0>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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enet-phy-pair-order = <1>;
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enet-phy-pair-polarity = <0>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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compatible = "ethernet-phy-ieee802.3-c45";
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enet-phy-pair-order = <1>;
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enet-phy-pair-polarity = <0>;
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};
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};
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&mdio_bus1 {
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/* External RTL8224 PHY */
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phy8: ethernet-phy@4 {
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reg = <4>;
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compatible = "ethernet-phy-ieee802.3-c45";
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enet-phy-pair-order = <0>;
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enet-phy-pair-polarity = <0>;
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};
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phy9: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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enet-phy-pair-order = <0>;
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enet-phy-pair-polarity = <0>;
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};
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phy10: ethernet-phy@6 {
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reg = <6>;
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compatible = "ethernet-phy-ieee802.3-c45";
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enet-phy-pair-order = <1>;
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enet-phy-pair-polarity = <0>;
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};
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phy11: ethernet-phy@7 {
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reg = <7>;
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compatible = "ethernet-phy-ieee802.3-c45";
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enet-phy-pair-order = <1>;
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enet-phy-pair-polarity = <0>;
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};
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};
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ðernet0 {
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nvmem-cells = <&macaddr_factory 0>;
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nvmem-cell-names = "mac-address";
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Copper ports */
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SWITCH_PORT_LED(0, 1, 2, 0, 10g-qxgmii)
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SWITCH_PORT_LED(1, 2, 2, 0, 10g-qxgmii)
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SWITCH_PORT_LED(2, 3, 2, 0, 10g-qxgmii)
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SWITCH_PORT_LED(3, 4, 2, 0, 10g-qxgmii)
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SWITCH_PORT_LED(8, 5, 3, 0, 10g-qxgmii)
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SWITCH_PORT_LED(9, 6, 3, 0, 10g-qxgmii)
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SWITCH_PORT_LED(10, 7, 3, 0, 10g-qxgmii)
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SWITCH_PORT_LED(11, 8, 3, 0, 10g-qxgmii)
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/* SFP cages */
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SWITCH_PORT_SFP(25, 9, 7, 1, 0)
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SWITCH_PORT_SFP(27, 10, 9, 1, 1)
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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@@ -0,0 +1,276 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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aliases {
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label-mac-device = ðernet0;
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led-boot = &led_pwr_sys_green;
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led-failsafe = &led_pwr_sys_red;
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led-running = &led_pwr_sys_green;
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led-upgrade = &led_pwr_sys_green;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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led_pwr_sys_green: led-0 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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led_pwr_sys_red: led-1 {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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};
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led_set: led_set {
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compatible = "realtek,rtl9300-leds";
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active-low;
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/* Copper */
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led_set0 = <(RTL93XX_LED_SET_100M | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_100M |RTL93XX_LED_SET_1G |
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RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)>;
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/* SFP+ */
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led_set1 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_2P5G |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_2P5G |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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/* PoE and Cloud are 4 leds in total but software managed.
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Assign them to led_set 1 to avoid shifting the others
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incorrectly. */
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realtek,led-set1-force-port-mask = <0x01800000>;
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};
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keys {
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compatible = "gpio-keys";
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mode {
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label = "restore";
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gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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};
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sfp0: sfp-p9 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p10 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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};
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};
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&i2c_mst1 {
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status = "okay";
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/* i2c of the left SFP+ cage seen from the front; port 9 */
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i2c0: i2c@0 {
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reg = <0>;
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};
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/* i2c of the right SFP+ cage seen from the front; port 10 */
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i2c1: i2c@1 {
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reg = <1>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bootbase";
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reg = <0x0 0x80000>;
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read-only;
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x7e000>;
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};
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partition@7e000 {
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label = "u-boot-env2";
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reg = <0x7e000 0x1000>;
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};
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partition@7f000 {
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label = "mrd";
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reg = <0x7f000 0x1000>;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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/* 12 addresses are available */
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macaddr_factory: macaddr@ff8 {
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compatible = "mac-base";
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reg = <0xff8 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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};
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partition@80000 {
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label = "reserved";
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reg = <0x80000 0x1e0000>;
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read-only;
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};
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partition@260000 {
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label = "factory";
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reg = <0x260000 0x1da0000>;
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "loader";
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reg = <0x0 0x10000>;
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};
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partition@10000 {
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label = "firmware";
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reg = <0x10000 0x1d90000>;
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compatible = "openwrt,uimage", "denx,uimage";
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};
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};
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};
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};
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};
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&mdio_bus0 {
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/* External RTL8224 PHY */
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phy0: ethernet-phy@0 {
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reg = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
enet-phy-pair-order = <0>;
|
||||
enet-phy-pair-polarity = <0>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
enet-phy-pair-order = <0>;
|
||||
enet-phy-pair-polarity = <0>;
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
enet-phy-pair-order = <1>;
|
||||
enet-phy-pair-polarity = <0>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
enet-phy-pair-order = <1>;
|
||||
enet-phy-pair-polarity = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio_bus1 {
|
||||
/* External RTL8224 PHY */
|
||||
phy8: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
enet-phy-pair-order = <0>;
|
||||
enet-phy-pair-polarity = <0>;
|
||||
};
|
||||
phy9: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
enet-phy-pair-order = <0>;
|
||||
enet-phy-pair-polarity = <0>;
|
||||
};
|
||||
phy10: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
enet-phy-pair-order = <1>;
|
||||
enet-phy-pair-polarity = <0>;
|
||||
};
|
||||
phy11: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
enet-phy-pair-order = <1>;
|
||||
enet-phy-pair-polarity = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
nvmem-cells = <&macaddr_factory 0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Copper ports */
|
||||
SWITCH_PORT_LED(0, 1, 2, 0, 10g-qxgmii)
|
||||
SWITCH_PORT_LED(1, 2, 2, 0, 10g-qxgmii)
|
||||
SWITCH_PORT_LED(2, 3, 2, 0, 10g-qxgmii)
|
||||
SWITCH_PORT_LED(3, 4, 2, 0, 10g-qxgmii)
|
||||
SWITCH_PORT_LED(8, 5, 3, 0, 10g-qxgmii)
|
||||
SWITCH_PORT_LED(9, 6, 3, 0, 10g-qxgmii)
|
||||
SWITCH_PORT_LED(10, 7, 3, 0, 10g-qxgmii)
|
||||
SWITCH_PORT_LED(11, 8, 3, 0, 10g-qxgmii)
|
||||
|
||||
/* SFP cages */
|
||||
SWITCH_PORT_SFP(25, 9, 7, 1, 0)
|
||||
SWITCH_PORT_SFP(27, 10, 9, 1, 1)
|
||||
|
||||
port@28 {
|
||||
ethernet = <ðernet0>;
|
||||
reg = <28>;
|
||||
phy-mode = "internal";
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -226,12 +226,16 @@ define Device/zyxel_xgs1250-12-b1
|
||||
endef
|
||||
TARGET_DEVICES += zyxel_xgs1250-12-b1
|
||||
|
||||
define Device/zyxel_xmg1915-10e
|
||||
define Device/zyxel_xmg1915
|
||||
SOC := rtl9302
|
||||
DEVICE_MODEL := XMG1915-10E
|
||||
FLASH_ADDR := 0xb4270000
|
||||
IMAGE_SIZE := 30336k
|
||||
ZYNFW_ALIGN := 0x10000
|
||||
$(Device/zyxel_zynos)
|
||||
endef
|
||||
|
||||
define Device/zyxel_xmg1915-10e
|
||||
DEVICE_MODEL := XMG1915-10E
|
||||
$(Device/zyxel_xmg1915)
|
||||
endef
|
||||
TARGET_DEVICES += zyxel_xmg1915-10e
|
||||
|
||||
Reference in New Issue
Block a user