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realtek: clk: change to __raw reads and writes

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The clk driver uses the ioread32 and iowrite32 for register access to
switchcore and SoC bases. This works but if at some point the target
wants to enable CONFIG_SWAP_IO_SPACE, the register access breaks as
ioread32/iowrite32 would be operating in little endian as opposed
to the intended native endian.

Fix it by replacing the ioread32/iowrite32 used in register access macros
to a __raw variant which aligns with what upstream use for native endian
access to registers.

Signed-off-by: Rustam Adilov <adilov@tutamail.com>
Link: https://github.com/openwrt/openwrt/pull/23206
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This commit is contained in:
Rustam Adilov
2026-05-03 14:45:17 +05:00
committed by Markus Stockhausen
parent a03e379f5a
commit d93c6d9a49
1 changed files with 4 additions and 4 deletions
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target/linux/realtek/files-6.18/drivers/clk/realtek/clk-rtl83xx.c
+4 -4
View File
@@ -80,11 +80,11 @@
#include "clk-rtl83xx.h"
#define read_sw(reg) ioread32(((void *)RTL_SW_CORE_BASE) + reg)
#define read_soc(reg) ioread32(((void *)RTL_SOC_BASE) + reg)
#define read_sw(reg) __raw_readl(((void *)RTL_SW_CORE_BASE) + reg)
#define read_soc(reg) __raw_readl(((void *)RTL_SOC_BASE) + reg)
#define write_sw(val, reg) iowrite32(val, ((void *)RTL_SW_CORE_BASE) + reg)
#define write_soc(val, reg) iowrite32(val, ((void *)RTL_SOC_BASE) + reg)
#define write_sw(val, reg) __raw_writel(val, ((void *)RTL_SW_CORE_BASE) + reg)
#define write_soc(val, reg) __raw_writel(val, ((void *)RTL_SOC_BASE) + reg)
/*
* some hardware specific definitions