Besides converting some functions to regmap do some minor
refactoring for rteth_931x_init_mac().
- Use dev_err() instead of classic print functions
- Harmonize ALE_INIT error handling. ALE_INIT_2 has the same
logic as the other registers. The reset is finished as soon
as the register is completely zero.
- From testing 100ms poll timeout seems to be sufficient
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23067
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Device support for zbt-z8106ax-s
Specifications:
SoC: MediaTek MT7981B
RAM: 256MiB
Flash: Winbond SPI-NAND 128 MiB
Switch: 1 WAN, 4 LAN (Gigabit) MediaTek MT7531
Buttons: Reset
Power: DC 12V 1A
WiFi: MT7981B 2.4Ghz & 5Ghz
USB 3
M2 slot to hold LTE modem
1 nano SIM slot (user controllable)
Hardware watchdog (confirmed to work)
Router comes in a plastic tower with all antennas internal.
- 4 antennas for LTE 4G/5G communication
- 2 antennas for Wifi 2.4 GHz
- 2 antennas for Wifi 5 GHz
Led Layout:
Power (green, user controllable, default set to OpenWrt Status)
Mobile (green, user controllable)
WLAN 2.4G (green, user controllable)
WLAN 5G (green, user controllable)
WAN (amber, user controllable, set to show eth1)
LAN1 (amber, hardware controlled)
LAN2 (amber, hardware controlled)
LAN3 (amber, hardware controlled)
LAN4 (amber, hardware controlled)
SIM Slot:
Controlled via exported GPIO named SIM.
echo "0" > /sys/class/gpio/sim/value
- turns off sim slot labelled SIM
echo "1" > /sys/class/gpio/sim/value
- turns on sim slot labelled SIM
---
Installation:
A. Through U-Boot menu:
- Prepare your connecting computer to use a static IP in
network 192.168.1.0/24 like
a) 192.168.1.10 netmask 255.255.255.0 (legacy notation)
b) 192.168.1.10/24 (CIDR notation)
- Power down the router and hold in the Reset button.
- While holding in the button power up the router again.
- Hold the button in for 10 seconds and then release.
- Use your browser to go to 192.168.1.1
- If you see a GUI allowing for flashing firmware then you got the right spot.
- Upload the **Factory** image file.
Note: U-Boot GUI it can be used to recover from an incorrect firmware flash.
B. Through OpenWrt Dashboard:
If your router comes with OpenWrt preinstalled (modified by vendor),
you can easily upgrade by going to the dashboard (192.168.1.1) and
then navigate to "System" -> "Backup/Flash firmware"
Flash OpenWRT firmware.
Important: Take care to deselect (untick) option
"keep settings". Settings done by vendor are incompatible with
versions 24.10 or 25.12.
MAC Addresses:
MAC Addresses were found in Factory partition:
offset 0x4 F8:5E:3C:xx:xx:aa --> Router Label -2
offset 0xa F8:5E:3C:xx:xx:bb --> Router Label -1
offset 0x24 F8:5E:3C:xx:xx:cc --> Router Label +1
offset 0x2a F8:5E:3C:xx:xx:yy --> printed on Router Label
Hardware Watchdog:
Device features a GPIO controlled hardware watchdog.
Verfied by removing procd controlled watchdog and
seeing device rebooting.
---
Notes:
The zbt-z8106ax-s could be ordered from vendor with a variety of modems.
Mine came with a 4G LTE modem Quectel EC200A.
Quectel firmware was at EC200AEUHAR01A30M16.
Choices for ordering with 5G LTE were available.
Modem communication is set to ethernet control mode (ECM) by vendor.
Package modemmanager works fine with Quectel EC200A.
You may also decide to use FUjR/Qmodem github repository
to have it manage LTE modem.
Please take note that internal switch port named lan5 isn't
wired to LTE modem in model S as opposed to model T.
Just removing lan5 from DTS did cause unwanted reboots whenever
a cable is plugged into LAN ports 1-4. Disabling port lan5
in DTS however works fine. No unwanted reboots due to
plug/unplug cable into any lan or wan port.
Signed-off-by: Jörg Seitz <github.joeterminal@xoxy.net>
Link: https://github.com/openwrt/openwrt/pull/22912
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Currently, the DesignWare PCIe driver cannot configure interrupts on
SoC that do not support MSIX. All MSI interrupts are handled by CPU0.
Backport MSI affinity support for the PCI dwc driver from linux-next,
so now we can adjust MSI interrupts to other CPU cores.
Tested on HINLINK H28K (RK3528) and OrangePi R2S (Ky X1).
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/21770
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The audio should only be enabled when the sound
node is enabled. This fixes the following error:
an7581-audio 1fbe2200.afe: probe with driver an7581-audio failed with error -2
Fixes: 7b55651 ("airoha: enable I2S sound driver and add nodes for eMMC RFB board")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/22660
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport support for the RTL8157. The RTL8157 is a low-cost chipset
designed for USB to 5Gb Ethernet adapters.
Tested on Sabrent NT-C5GA (RTL8157), Wavlink WL-NWU340G (RTL8157) and
UGREEN CM648 (RTL8156BG) adapters.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/23088
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Rollball command byte needs to be written last. Otherwise the
controller might access the wrong register or write the wrong value.
Fixes: 1fc19bc06e ("realtek: rtl93xx: mdio-smbus support for clause 45 and Rollball SFPs")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/23049
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
At least the XikeStor SKT-2.5G-100M SFP module seems to internally use
MDIO address 0 to access the PHY. This module allows accessing PHY
registers using Rollball protocol on address 0x51, and also provides
read-only C22 access on address 0x56. However, after disabling the
PHYAD0 configuration bit, only 0xffff can be read via both methods
(except for MMD device 30 which can still be accessed).
Since having MDIO address 0 enabled shouldn't do any harm on SFP modules
just leave the configuration bit alone in that case.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/23065
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
After the RTL8261N asserts a reset, the MDIO bus becomes temporarily
unavailable during the chip's reinitialization sequence. Any subsequent
read or write issued before the PHY has stabilized will fail.
Add a 30ms delay after triggering the reset to ensure the chip is reachable
via MDIO before resuming communication.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/23076
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
In the past, all the configuration of SerDes and PHYs on the realtek
switches were done using u-boot (`rtk init`). But since RTL930x switched
to SerDes configuration under Linux, the SoC side is no longer using the
Realtek-proprietary variant of USXGMII. The communication to the RTL8261N
PHYs on those switches broke because of this incompatibility.
Enabling the full initialization on `CONFIG_MACH_REALTEK_RTL` converts also
the PHY side to the standard USXGMII and therefore ensures that both sides
speak the same dialect.
Co-authored-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/23076
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The PHY register patch in question is gated by `CONFIG_MACH_REALTEK_RTL`,
has no documented/expected behavior, and is in practice unreachable:
`phy_patch()` is only called from `rtkphy_config_init()`, which is exits
(too) early for `CONFIG_MACH_REALTEK_RTL` builds.
Remove it as a cleanup step before enabling standard USXGMII configuration
for these PHYs.
Fixes: b77fa45d12 ("kernel: fix rtl8261n driver for realtek")
Co-authored-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/23076
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit adds support for Hasivo S600WP-5GT-2SX-SE switch.
Device specification
--------------------
SoC Type: Realtek RTL9303
RAM: 128MB DDR3 SDRAM
Flash: Fudan FM25Q128A (16 MB)
Ethernet: 5x RTL8221B 10/100/1000/2500Mbps PHY (RJ45)
2x SFP+ 10G (I2C/DOM via bit-banged GPIO)
LEDs: 1x power green (no control)
1x system green (via RTL9303 GPIO)
3x RJ45 LEDs/port (HC595 shift regs on LED SPI)
1x Green (1G link)
1x Green (10M/100M link)
1x Orange (2.5G link)
2x SFP+ LEDs/port (HC595 shift regs on LED SPI)
1x 10G link
1x 1G link
Button: Reset
USB ports: None
Bootloader: Realtek U-Boot 2011.12
PoE: 1x HS104PTI for 802.3af/at/bt PoE (driver
will follow in a separate patch)
Installing OpenWrt
------------------
1. UART RJ45 requires soldering a connector to the empty footprint (RJ1).
(Amphenol RJHSEE380 or similar)
2. Connect to UART 38400@8n1, using Cisco Console Rollover cable (RS232)
3. Enter bootloader by pressing esc key during boot
4. Enter password `Hs2021cfgmg`
5. Type `XXXX` to get into U-Boot
6. Increase baudrate: `setenv baudrate 115200`
7. Use serial transfer (Y modem) via minicom:
`loady 0x84f00000`
Then send the initramfs image via minicom's Y modem upload.
8. `bootm 0x84f00000`
Now you should be in OpenWrt, and can use sysupgrade to install.
Signed-off-by: Carlo Szelinsky <github@szelinsky.de>
Link: https://github.com/openwrt/openwrt/pull/22310
Signed-off-by: Robert Marko <robimarko@gmail.com>
With the recent backport of the common PHY properties infrastructure
(phy-common-props and the phy_get_manual_{rx,tx}_polarity() helpers) to
OpenWrt, the generic `{rx,tx}-polarity` device tree properties are now
usable for the Realtek PCS driver. Switch the driver and all affected
boards from the local vendor-specific `realtek,pnswap-{rx,tx}` booleans
to the common properties.
Add a `config_polarity` SerDes op (implemented by RTL930x and RTL931x;
RTL838x/RTL839x polarity support not yet added) and a generic wrapper
that resolves the requested polarity via phy_get_manual_{rx,tx}_polarity()
and dispatches to the op. Variants without the op silently accept the
default polarity but warn when a non-default polarity is requested,
since that cannot be honored.
Move the polarity programming out of the variant setup_serdes callbacks
into rtpcs_pcs_config, so it runs before setup_serdes. This matches the
ordering used by the vendor SDK, which configures polarity first.
Update all board DTS files that previously used `realtek,pnswap-{rx,tx}`
to the new `{rx,tx}-polarity = <PHY_POL_INVERT>` property, and select
PHY_COMMON_PROPS from Kconfig.
Each SerDes now retains its DT node for later polarity lookup. Use
for_each_child_of_node_scoped for the iterator, and register a
devm_add_action_or_reset for each stored reference so it is released on
unbind or probe failure.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23044
Signed-off-by: Robert Marko <robimarko@gmail.com>
The hardware usually takes care that
- a packet is no larger than the available buffer
- has at least a FCS checksum of 4 bytes
Nevertheless be cautious and improve the existing
packet check. Just in case ...
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22884
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Kite EVB device wrongly select an invalid package for NPU firmware
where the correct one should be the airoha-en7581-npu-firmware one.
Fix the wrong package to restore compilation of the Airoha target.
Fixes: 0cf516751a ("airoha: an7581: generalize eMMC DTS and add Kite variant")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
CONFIG_PAGE_BLOCK_MAX_ORDER was set to 10 as the page size is 4k.
All other kernel symbols are automatically refreshed by
`make kernel_oldconfig CONFIG_TARGET=target` and
`make kernel_oldconfig CONFIG_TARGET=subtarget`.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/22922
Signed-off-by: Nick Hainke <vincent@systemli.org>
This patch adds support for the MikroTik RouterBOARD 960PGS (hEX
PoE/PowerBox Pro) router. The device has a USB 2.0 port and an SFP port for
adding optical fiber connectivity. The ports 2-5 can power other PoE
capable devices with the same voltage as applied to the unit.
Specifications:
- SoC: Qualcomm Atheros QCA9557
- Flash: 16 MB (SPI)
- RAM: 128 MB
- 1x Ethernet SFP: 1000
- 1x Ethernet RJ45: 10/100/1000 port with passive POE in
- 4x Ethernet RJ45: 10/100/1000 ports with 802.3af/at PoE out
- 1x USB 2.0 host port
- 1x reset button
See [1] and [2] for more details.
Flashing:
TFTP boot initramfs image and then perform sysupgrade. Follow common
MikroTik procedure as in https://openwrt.org/toh/mikrotik/common.
Link: https://mikrotik.com/product/RB960PGS [1]
Link: https://mikrotik.com/product/RB960PGS-PB [2]
Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
Signed-off-by: Chester A. Unal <chester.a.unal@arinc9.com>
Unset the SWCONFIG symbol and AR8216_PHY which selects SWCONFIG. Add
kmod-switch-ar8xxx, which enables AR8216_PHY, to DEFAULT_PACKAGES for the
subtarget. With this, swconfig driver will be now compiled as a module, as
kmod-switch-ar8xxx selects kmod-swconfig.
Refresh the config-default file for ath79/mikrotik while at it.
This change makes it possible to disable the swconfig driver for MikroTik
RouterBOARD 960PGS (hEX PoE/PowerBox Pro).
Signed-off-by: Chester A. Unal <chester.a.unal@arinc9.com>
Markus Stockhausen
Jörg Seitz
Tianling Shen
Robert Marko
Chukun Pan
Rye Sears
Andrew LaMarche
Aleksander Jan Bajkowski
Jan Hoffmann
Jonas Jelonek
Sven Eckelmann
Daniel Golle
Carlo Szelinsky
Zoltan HERPAI
Rosen Penev
Christian Marangi
Mieczyslaw Nalewaj
Shiji Yang
Oskari Lemmela
Chester A. Unal