This allows us to use the full size of nand,
which extends ubi size from 64Mb to 122.25Mb.
1. Log in to the device and backup all the partitions,
especially unique "Factory" and "bdata" partitions
from System -> Backup / Flash Firmware -> Save mtdblock contents.
2. Install kmod-mtd-rw to unlock mtd partitions for writing
apk update && apk add kmod-mtd-rw && insmod mtd-rw i_want_a_brick=1
3. Write new OpenWrt (U-Boot Layout) "BL2" and "FIP":
mtd -e BL2 write openwrt-mediatek-filogic-cudy_wr3000h-v1-ubootmod-preloader.bin BL2
mtd -e FIP write openwrt-mediatek-filogic-cudy_wr3000h-v1-ubootmod-bl31-uboot.fip FIP
4. Set static IP on your PC: "192.168.1.254", gateway "192.168.1.1"
5. Serve openwrt-mediatek-filogic-cudy_wr3000h-v1-ubootmod-initramfs-recovery.itb
using TFTP server.
6. Connect Router LAN with PC LAN.
7. Cut off the power and re-engage, wait for TFTP recovery to complete.
8. After OpenWrt initramfs recovery has booted,
clean "/dev/mtd5" ubi partition to utilize maximum of free space:
ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5
ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB
ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB
9. Perform sysupgrade.
Signed-off-by: Dmitry Mostovoy <stavultras@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21943
Signed-off-by: Robert Marko <robimarko@gmail.com>
This allows us to use the full size of nand,
which extends ubi size from 64Mb to 122.25Mb.
1. Log in to the device and backup all the partitions,
especially unique "Factory" and "bdata" partitions
from System -> Backup / Flash Firmware -> Save mtdblock contents.
2. Install kmod-mtd-rw to unlock mtd partitions for writing
apk update && apk add kmod-mtd-rw && insmod mtd-rw i_want_a_brick=1
3. Write new OpenWrt (U-Boot Layout) "BL2" and "FIP":
mtd -e BL2 write openwrt-mediatek-filogic-cudy_wr3000e-v1-ubootmod-preloader.bin BL2
mtd -e FIP write openwrt-mediatek-filogic-cudy_wr3000e-v1-ubootmod-bl31-uboot.fip FIP
4. Set static IP on your PC: "192.168.1.254", gateway "192.168.1.1"
5. Serve openwrt-mediatek-filogic-cudy_wr3000e-v1-ubootmod-initramfs-recovery.itb
using TFTP server.
6. Connect Router LAN with PC LAN.
7. Cut off the power and re-engage, wait for TFTP recovery to complete.
8. After OpenWrt initramfs recovery has booted,
clean "/dev/mtd5" ubi partition to utilize maximum of free space:
ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5
ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB
ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB
9. Perform sysupgrade.
Signed-off-by: Dmitry Mostovoy <stavultras@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21943
Signed-off-by: Robert Marko <robimarko@gmail.com>
This allows us to use the full size of nand,
which extends ubi size from 64Mb to 122.25Mb.
1. Log in to the device and backup all the partitions,
especially unique "Factory" and "bdata" partitions
from System -> Backup / Flash Firmware -> Save mtdblock contents.
2. Install kmod-mtd-rw to unlock mtd partitions for writing
apk update && apk add kmod-mtd-rw && insmod mtd-rw i_want_a_brick=1
3. Write new OpenWrt (U-Boot Layout) "BL2" and "FIP":
mtd -e BL2 write openwrt-mediatek-filogic-cudy_wr3000s-v1-ubootmod-preloader.bin BL2
mtd -e FIP write openwrt-mediatek-filogic-cudy_wr3000s-v1-ubootmod-bl31-uboot.fip FIP
4. Set static IP on your PC: "192.168.1.254", gateway "192.168.1.1"
5. Serve openwrt-mediatek-filogic-cudy_wr3000s-v1-ubootmod-initramfs-recovery.itb
using TFTP server.
6. Connect Router LAN with PC LAN.
7. Cut off the power and re-engage, wait for TFTP recovery to complete.
8. After OpenWrt initramfs recovery has booted,
clean "/dev/mtd5" ubi partition to utilize maximum of free space:
ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5
ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB
ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB
9. Perform sysupgrade.
Signed-off-by: Dmitry Mostovoy <stavultras@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21943
Signed-off-by: Robert Marko <robimarko@gmail.com>
This allows us to use the full size of nand,
which extends ubi size from 64Mb to 122.25Mb.
1. Log in to the device and backup all the partitions,
especially unique "Factory" and "bdata" partitions
from System -> Backup / Flash Firmware -> Save mtdblock contents.
2. Install kmod-mtd-rw to unlock mtd partitions for writing
apk update && apk add kmod-mtd-rw && insmod mtd-rw i_want_a_brick=1
3. Write new OpenWrt (U-Boot Layout) "BL2" and "FIP":
mtd -e BL2 write openwrt-mediatek-filogic-cudy_wr3000p-v1-ubootmod-preloader.bin BL2
mtd -e FIP write openwrt-mediatek-filogic-cudy_wr3000p-v1-ubootmod-bl31-uboot.fip FIP
4. Set static IP on your PC: "192.168.1.254", gateway "192.168.1.1"
5. Serve openwrt-mediatek-filogic-cudy_wr3000p-v1-ubootmod-initramfs-recovery.itb
using TFTP server.
6. Connect Router LAN with PC LAN.
7. Cut off the power and re-engage, wait for TFTP recovery to complete.
8. After OpenWrt initramfs recovery has booted,
clean "/dev/mtd5" ubi partition to utilize maximum of free space:
ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5
ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB
ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB
9. Perform sysupgrade.
Signed-off-by: Dmitry Mostovoy <stavultras@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21943
Signed-off-by: Robert Marko <robimarko@gmail.com>
Check for dev in driver remove gives no additional security. The
remove() function is only called if probe() succeeded. Probing
will always call platform_set_drvdata() in the good case. So
remove() will always find dev data via platform_get_drvdata().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22610
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ethernet driver is only loaded via devicetree and makes use
of of_match_table. In this case the probing function is only
called if a matching compatible is set. So pdev->dev.of_node
can never be NULL.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22610
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Commit d52f7a4ca5 ("realtek: dts: new SWITCH_PORT_LED() macro") introduced
a new macro to simplify switch port definitions and introduces usage of
it for Zyxel XGS1X10-12 devices. However, this change added a DTS syntax
issue because:
> SWITCH_PORT_LED(...);
produces
> port@XX { ... };;
because the macro already includes a trailing semicolon. The DT compiler
doesn't like this so it fails with syntax error. Fix this by dropping the
trailing semicolons after macro usages.
Fixes: d52f7a4ca5 ("realtek: dts: new SWITCH_PORT_LED() macro")
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22614
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL8261BE 10GbE PHY's `reset-deassert-us` was set to 100ms (100000us),
but the **RTL8261N datasheet (Table 108, parameter t7)** specifies a
minimum **SMI-ready time of 150ms** after nRESET release before the MDIO
(SMI) bus can be used.
Note: Essentially, the RTL8261N and RTL8261BE are architecturally identical
chips, so their initialization parameters should be consistent.
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22575
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Previous changes refactored the hardware mode configuration for RTL930x
a lot. Now that this is in a better shape, one issue persists: missing
error propagation. Only parts of this function really propagate an
error, others are silently dropped. While this is a known driver-wide
issue, at least make it good here. Propagate the errors from functions
which apply configuration sequences to the caller.
Single writes are still left out on purpose, they need and will be
addressed later.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Decommission a helper for applying config/patch sequences for even/odd
SerDes. Most of these sequences were squashed due to marginal
difference, sharing a lot of common parts. For the marginal differences,
testing showed that the different values were already present on
even/odd. Since those are no reset/trigger bits but just configuration
values, writing them for both should do no harm.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Config/patch sequences have been reduced and merged by previous changes.
Now that we have a clearer view on them, we can see that there are still
several similarities between the even and odd variants. Some different
writes for even and odd SerDes remain but one can find out they don't
need to be separate. For example, a write to [0x29, 0x09] is missing for
odd SerDes but testing and a SerDes dump from a running configuration
show that the registers still hold the same value and changes do not
affect functionality. Thus, merge them too to get rid of a lot of
even/odd stuff.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Right now, the config sequences for XSGMII and USXGMII have been
stripped down to their essential parts. Still, they have redundancies.
The XSGMII sequences are 99% equal to the generic ANA_10G sequences
(except for a single write which is DFE/LEQ-related and changed during
calibration later anyway), thus we can drop them completely.
The USXGMII sequences contain the same sequences so they can be removed
there too, all being covered by applying the ANA_10G sequence for those
modes too. One different write (register [0x2e, 0x01]) is integrated into
the ANA_10G sequence since testing has shown that the value is either the
default for that register anyway, or set during SDK setup too for 10GR.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Move a few register writes from the ANA_10G patch sequences to the
configuration function. Those write are targeted at digital pages and do
not fully apply for *SGMII modes. To make the ANA_10G sequence really
just deal with analog pages and make it usable for *SGMII modes too,
move out the digital page writes.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
The patch/config sequences we took over from the SDK are partially
redundant, i.e. they share common parts which can be separated per
speed. For example, the config for 10GR contains the one for 2500Base-X
but we have a dedicated one for 2500Base-X. This is a first step to
modularize and reverse-engineer those sequences, and decrease the size
they claim.
The sequences are nearly exclusive ordered by ascending pages. This
suggests that those register/writes do not have a hidden function of
performing inline resets but rather are just configuration values.
Likely, they may be applied in rather arbitrary order. Splitting up the
sequences here assumes this is true and does some minor order changes.
Testing shows no behavioral change. Looking at [1] there are no relevant
reset or trigger bits affected by that. Suspiciously ordered writes have
mostly been kept though.
USXGMII setup needs to be adjusted too due to shared sequence parts.
[1] https://github.com/plappermaul/realtek-doc/blob/82af3a36b7f65dbe2158fef3a9b71e7aab94315e/sources/rtk-dms1250/include/hal/phy/rtl8295_reg_def.h
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
USXGMII configuration is currently only performed via the patching
sequences although there's a dedicated function which configures several
parameters and assigns meaningful names to some register fields. It was
introduced in dca20f91ea ("realtek: add serdes patch for 10G_QXGMII")
but somewhat abandoned later due to a partial revert.
To improve the situation, prioritize usage of the function for USXGMII
variants and remove some parts from the patch sequences which seem to be
exclusive for USXGMII and thus can be covered by this function. Writes
to registers [0x6, 0xE], [0x6, 0x13] and [0x6, 0x14] can be dropped
completely because they are redundant. The bits really affected by
these writes (compared to the default register values aquired from a
dump) are overwritten below again. Testing on real hardware and USXGMII
supports this.
While at it, improve the style a bit and add comments explaining some of
the fields a bit more. Additionally, fix the call situation which
currently is dead code due to early exit. Provide two calls to the
mentioned functions but comment one of them to remain current
functionality. Names and meaning of fields is inferred from [1].
[1] https://github.com/plappermaul/realtek-doc/blob/82af3a36b7f65dbe2158fef3a9b71e7aab94315e/sources/rtk-dms1250/include/hal/phy/rtl8295_reg_def.h
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Handle QSGMII config earlier within the configuration function as a
preparation for subsequent patches in this area. Those will target
splitting up the config sequences and 5G-QSGMII is special there.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Rename the function that currently "applies patches" so that it covers
everything it does (and will do). It doesn't only apply patches but in
general performs configuration of a SerDes for a particular hardware
mode.
While at it, remove a print above that call because it is both placed
wrong and redundant due to what the generic pcs_config prints.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Change how patches are applied to reduce redundancy and make the code
more readable. Define a generic function that applies any patch. Within
the RTL930x patch application, define a local macro that helps to get
rid of repeated even/odd checks. While making the code cleaner, it is
also a preparation for further refactoring here.
This adds a local helper macro intended to be only temporary but keeps
the style of the code clean by avoiding a lot of if-else clauses.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Several devices (including the upcoming DGS-1250) need a fully
featured port definition that includes:
- port number
- label
- led-set
- pcs-handle
- phy-handle
- phy-mode
Provide a new macro for that and make the Zyxel XGS-1210 series
the first consumer of it.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22591
Signed-off-by: Robert Marko <robimarko@gmail.com>
In the blamed commit, the wrong partition name for ART was used.
It was later discovered that the partition table uses "0:ART" instead of
"art" for the ART partition name thus breaking caldata extraction.
So, fix the partition name.
Fixes: ee5999cf78 ("treewide: linksys: use nvmem MAC for hw_mac_addr")
Signed-off-by: Anthony Sepa <protectivedad@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Allow to configure the LM75 alert pin to active-high instead
of its default active-low. This patch is needed for the D-Link
DGS-1250 series where the alert pin steers the fan speed
between low and high.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22589
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
When the link goes down on the other end of a bond, it was noticed that the
switch was still trying to send data over this link.
Problem here is that net_lag_port_dev_txable() uses
bond_is_active_slave_dev() to look the state up. But this is actually
showing if a link is a NOT a backup - not if the link should be really be
TX enabled or not.
As a DSA driver, it is important to consume the DSA information.
dp->lag_tx_enabled must therefore be used for DSA .port_lag_change events.
This variable contains two information from the
struct netdev_lag_lower_state_info:
tx_enabled = linfo->link_up && linfo->tx_enabled;
Fixes: 89322b4d69 ("rtl93xx: dsa: Handle lag_change properly")
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/22382
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Specifications
--------------
- SoC : Qualcomm IPQ4019
- RAM : 256 MiB DDR3-1600 (NT5CC128M16IP)
- Flash : 32 MiB SPI NOR
- V1, V2 : GigaDevice GD25Q256C
- V3 : Winbond W25Q256FV, Micron N25Q128A11
- V320 : EON EN25QH256, XMC XM25QH256BK (with patch included)
- WLAN : IPQ4019 On-chip
- 2.4 GHz : 2x2 MIMO 802.11b/g/n
- 5 GHz : 2x2 MIMO 802.11n/ac
- Ethernet : QCA8072 10/100/1000BASE-T 1x WAN; 1x LAN
- UART : 3v3 115200n, use pins under heatsink
- Buttons : 1x Reset
- LEDs : 1x Combined RGB LED
- V1 : Driven by LP5521 channels (Channel 0, 1, 2?)
- V3, V320 : Driven by GPIO Pins (Pin 28, 32, 35 Active Low)
- Bluetooth :
- V1, V2, V3 : CSR8811
- V320 : AC6368A/B
- Power : DC 12V @ 1.2A
- FCC ID :
- V1 : TE7M5
- V3 : TE7M5V3
- V320 : TE7M5V32, 2AXJ4M5V3, 2BCGWM5V3
- TFTP ID :
- Client : 192.168.0.66
- Router : 192.168.0.11
MAC Addresses
-------------
Label : OPAQUE partition @ 0x0008
LAN : Label
WAN : Label + 1
WLAN 2G : Label + 2
WLAN 5G : Label + 3
Installation
------------
1. Install TFTP server software
2. Rename the factory image to 'M5v1_tp_recovery.bin' and copy it into
the TFTP folder
3. Connect an interface configured to 192.168.0.66/24 to the LAN port
- Note: The LAN port is the ethernet port that is furthest away from
the power plug
4. Press the 'reset' button down before powering up the device, holding
for at least 10 seconds
5. Router should download the factory image, install it, and then reboot
6. Router will start up with address 192.168.1.1
Known Issues
------------
- Some devices (including some V1 and V2 devices) may have flash chips
that are not detected, supported by, or have broken SFDP support
Signed-off-by: Bee Cadorna <r3usrlnd@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17537
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL93xx based D-Link DGS-1250 series is currently being
prepared for OpenWrt support. These devices have some extras
that are not yet supported by the existing configuration.
Add the following items to the kernel configuration:
- CONFIG_SENSORS_GPIO_FAN: The devices have a simple gpio
controlled fan (0/1 aka off/on).
- CONFIG_I2C_GPIO_SHARED: The busses of the SFP+ slots are
not controlled by the built-in SOC I2C controller. Instead
they are realized by shared SCL bit banged GPIOs.
- CONFIG_EEPROM_AT24: The MAC address and other device data
is storend in an Atmel EEPROM.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22543
Signed-off-by: Robert Marko <robimarko@gmail.com>
The i2c-shared-gpio driver is designed to emulate up to four
i2c busses with distinct sda lines and a a shared scl line.
For some reason the check for the number of allowed busses
is one off and the driver can only allocate three busses.
Fix that.
Fixes: acd7ecc9ed ("realtek: add new i2c-gpio-shared driver")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22543
Signed-off-by: Robert Marko <robimarko@gmail.com>
Due to the last refactorings it has become clear that the following
code is wrong.
static void rteth_tx_timeout()
{
...
rteth_838x_hw_en_rxtx(ctrl);
A generic function must not call a device specific function directly.
Make hw_en_rxtx() a config member and call that instead of the
functions directly.
With this change another optimization can take place. hw_init()
currently calls device specific hw_en_rxtx() functions at the start
of the function. This is wrong. Initialize the hardware first before
activating the network rx/tx. Take out the multiple calls and place
the rx/tx setup just before the hw_init() call.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22421
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL93xx sets up the ring counters twice. One location is
inside rteth_93xx_hw_en_rxtx() and the other one is inside
rteth_93xx_hw_reset(). There are slight differences (e.g.
the ring size that is set or how the counters are cleared).
It is currently unclear where to place it best. For now
align this to RTL83xx and remove the coding from function
rteth_93xx_hw_en_rxtx(). Provide a complete & proper setup
in rteth_93xx_hw_reset().
Looking at the different old implementations one can see
that one initialized the ring counters with offset "-2".
This headroom is not needed. The old comment " Some SoCs
have issues with missing underflow protection" was only
regarding the way the counters are being resetted and not
how large they are setup.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22421
Signed-off-by: Robert Marko <robimarko@gmail.com>
Dmitry Mostovoy
Markus Stockhausen
Jonas Jelonek
Rosen Penev
Maxim Anisimov
Anthony Sepa
Sven Eckelmann
Damien Dejean
Yanase Yuki
Zhi-Jun You
Nick Hainke
Bee Cadorna