Backport two upstream commits that replace memset() on coherent DMA
descriptor rings with explicit WRITE_ONCE() status word stores.
On 32-bit PowerPC platforms like apm821xx, coherent DMA memory may be
mapped uncached. The optimized memset() path can use dcbz there, which
triggers alignment warnings and spams the kernel log.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23776
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Move apm821xx to the 6.18 kernel after testing it as the testing kernel.
There are ethernet performance improvements in the 6.18 kernel for
whatever reason. There's also work on getting rid of dmesg slop at
runtime.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23777
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Add a temperature/fan sensor (hwmon) driver for the Hasivo / Horaco
management MCU as a second child of the hasivo MCU MFD (alongside the
watchdog). It exposes the CPU and system temperatures and a 3-state fan
control (auto / force-on / force-off), read/written through the parent's
shared syscon regmap.
The register protocol was reverse-engineered from the stock 'imi' firmware
and verified on hardware. The fan-status register (0xFB) reflects the MCU's
effective drive state, not actual rotation (a blocked fan still reads
force-on), so no fanN_alarm is exposed. pwm1 echoes the commanded state so
a write reads back consistently, and falls back to the live drive state in
automatic mode. The register map is shared across boards.
Signed-off-by: Carlo Szelinsky <github@szelinsky.de>
Link: https://github.com/openwrt/openwrt/pull/23762
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The watchdog and the temperature/fan hwmon are the same management MCU at
a single I2C address (0x6f). Linux binds one driver per I2C client, so the
watchdog cannot keep owning the address directly if the hwmon is to live
on the same chip. Convert it from a standalone i2c_driver into a
platform_driver child of the hasivo MCU MFD that reaches the chip through
the parent's shared regmap (syscon), and depend on kmod-mfd-hasivo-stc8.
Signed-off-by: Carlo Szelinsky <github@szelinsky.de>
Link: https://github.com/openwrt/openwrt/pull/23762
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Make use of scoped_guard macro to ease lock and error handling in
pcs_config by having a dedicated scope and no need for gotos.
While being here, replace -ENOTSUPP with preferred -EOPNOTSUPP and drop
{ } brackets for single statement block.
Link: https://github.com/openwrt/openwrt/pull/23759
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Add the mandatory activate/deactivate bring-up hooks to rtpcs_sds_ops
and let rtpcs_pcs_config() drive the full sequence around the variant
configuration:
deactivate -> setup_serdes -> activate -> post_config
The per-variant calls that were open-coded at the start and end of the
setup_serdes() functions are removed in favour of these indirections.
RTL839X never powered the SerDes down/up, so it gets no-op stubs to
satisfy the contract for now. Execution order is preserved for all
variants.
Link: https://github.com/openwrt/openwrt/pull/23759
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Some variants need finalization that must run only after the SerDes is
powered up: RTL838X performs a one-shot switch queue reset on first
start, RTL930X runs RX calibration and the TX config. So far this lived
at the tail of the variant setup_serdes() functions.
Add an optional post_config hook to rtpcs_sds_ops and call it from
rtpcs_pcs_config() right after setup_serdes(), then relocate the
RTL838X and RTL930X tail work into it. As activate() still runs at the
end of setup_serdes() here, the execution order is unchanged.
Link: https://github.com/openwrt/openwrt/pull/23759
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
In RTL930x setup, tx config was called at then end of the procedure
after configuration and calibration ran. This is still a leftover from
the old code located in DSA/PHY. However, applying TX configuration like
amplification factors, etc. doesn't make sense after calibration, it
should run before. Moreover the call was commented with "leave loopback
mode" which is just wrong and doesn't describe what the function does.
Fix this misery.
Testing on device with different interface modes shows no difference so
far, especially no negative effects.
Link: https://github.com/openwrt/openwrt/pull/23759
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Currently the "WiFi" LED indicator light is triggered only by activity on the 5 GHz PHY.
Change it to be triggered by WLAN activity on either Wi-Fi PHY, matching stock behaviour, by using
`kmod-ledtrig-network` added in 2aa1185fb0 ('leds: add "network" LED trigger (lan/wan/wlan)').
Signed-off-by: Ryan Leung <untilscour@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/23682
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
The second WLAN MAC address in the "Factory" partition at 0x0a is not the same as the
WLAN 5GHz BSSID observed when using the manufacturer's stock firmware, which is derived from
the 2.4GHz/label MAC address by setting bits 26 and 7 (Locally Administered).
While at it, also fix alphabetical ordering of some other device names.
Fixes: 1748ce8295 ("mediatek: add support for WAVLINK WL-WN536AX6 Rev a")
Signed-off-by: Ryan Leung <untilscour@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/23682
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Currently the WAN MAC address is read from the first (LAN) MAC address in the "HW" partition and
then incremented by 1 instead of being read directly from the second MAC address.
Change to reading the two MAC addresses (LAN/WAN) directly from "Factory" partition.
Fixes: 1748ce8295 ("mediatek: add support for WAVLINK WL-WN536AX6 Rev a")
Signed-off-by: Ryan Leung <untilscour@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/23682
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Enable nmbm bad block management with up to 8 MiB reserved. The manufacturer's stock device tree
contains the property `compatible = "generic,nmbm";` in node `nmbm_spim_nand` and
manufacturer's stock bootlog contains "nmbm nmbm_spim_nand: NMBM has been successfully attached"
Fixes: 1748ce8295 ("mediatek: add support for WAVLINK WL-WN536AX6 Rev a")
Signed-off-by: Ryan Leung <untilscour@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/23682
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
The board contains a TI TMP75 temperature sensor located near the ethernet
PHYs, attached to the thermal mass of the back case, close to main SoC.
Configure `gsbi2` for i2c mode and include `kmod-hwmon-lm75` package.
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
Link: https://github.com/openwrt/openwrt/pull/23740
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
In previous versions of OpenWrt, ethernet was partially working,
sometimes depending on initialization state left by bootloader.
Since the switch to NSS drivers, it is completely broken.
- swap GMAC to PHY address mapping
- use rgmii internal delay
- drop `fixed-link` rates
- add pinctrl settings for rgmii0
- declare reset GPIO 51 (used for both PHYs)
- disable hibernation
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
Link: https://github.com/openwrt/openwrt/pull/23740
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
OpenWrt has recently added the "network" LED trigger to support routers
that have a single WLAN LED for multiple phys.
This patch replaces the temporary workaround used during initial
support, where the LED was triggered only by activity on a single phy.
With this change, the WLAN LED on the ipTIME AX3000SE now correctly
indicates activity on both `phy0` and `phy1`.
Signed-off-by: Donghyun Ko <nyankosoftware@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23723
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Update to 2.5.3 and use the official tarball.
Changelog: https://github.com/ppp-project/ppp/releases/tag/v2.5.3
Removed upstreamed:
- 000-pppd-session-fixed-building-with-gcc-15.patch
- 001-pppdump-fixed-building-with-gcc-15.patch
- 501-fix-memcpy-fortify.patch
- 502-remove_mru.patch
Manually rebased:
- 500-add-pptp-plugin.patch
Add a pending patch to relax the check to avoid breaking existing
configurations.
Signed-off-by: Qingfang Deng <dqfext@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23540
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Published sources archives may contain a mixture of MTIMEs, so taking the time
of the first file found varies based on filesystem order. To fix this, sort all
MTIMEs and take the latest.
Since piping into a file directly creates that file, we also need to
specifically tell `find` to ignore `version.date`.
Furthermore, move this prior to the ./src copy step, since for some packages,
the OpenWrt build system ships extra ./src files, which would introduce the
wrong timestamps again.
Fix: e36c2946b7 build: derive PKG_SOURCE_DATE_EPOCH from the unpacked source tree
Link: https://github.com/openwrt/openwrt/pull/23756
Signed-off-by: Paul Spooren <mail@aparcar.org>
The firmware-version gate in mxl862xx_phylink_get_caps() leaves
config->supported_interfaces empty for the CPU/SerDes ports (9, 13) when
the switch runs firmware older than 1.0.84. phylink rejects an empty
supported_interfaces bitmap, so the switch fails to probe at all:
mxl862xx mdio-bus:10: switch ready after 2480ms, firmware 1.0.70 (build 70)
mxl862xx mdio-bus:10: phylink: error: empty supported_interfaces
error creating PHYLINK: -22
mxl862xx mdio-bus:10: probe with driver mxl862xx failed with error -22
This regresses boards still shipping the older vendor firmware (e.g. the
BananaPi BPi-R4 Pro 8X, which ships 1.0.70) where all LAN ports disappear.
Ungate only the CPU/SerDes ports (9, 13) so the switch probes and the user
can update the firmware; ports 10..12 and 14..16 stay gated as they are
genuinely unsupported by the old firmware.
Tested on a BPi-R4 Pro 8X with switch firmware 1.0.70 (kernel 6.18); the
6.12 patch receives the identical change for parity.
Fixes: 028dc3f57a ("generic: 6.18: update MxL862xx DSA switch driver")
Fixes: 5b69e6a4a6 ("generic: 6.12: update MxL862xx DSA switch driver")
Signed-off-by: Aliaksandr Babrykovich <abobrikovich@gmail.com>
[refreshed patches]
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The u-boot build for mediatek ARM SoCs doesn't require pylibfdt. We
can use pre-build kernel DTC to save some build time.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Commit 9091c9f8cb ("ath79: mikrotik: compile SWCONFIG and AR8216_PHY
as modules") caused the hybrid PHY/MDIO ar8xxx driver to be built as a
module instead of built-in. On at least MikroTik RouterBOARD 951G-2HnD,
this prevents the kernel from binding the correct PHY driver at boot
because the ar8xxx driver is not yet available when the MDIO bus is
probed:
- before:
ag71xx-legacy 19000000.eth: invalid MAC address, using random address
switch0: Atheros AR8327 rev. 4 switch registered on mdio.0
ag71xx-legacy 19000000.eth: connected to PHY at mdio.0:00 [uid=004dd034, driver=Atheros AR8216/AR8236/AR8316]
eth0: Atheros AG71xx at 0xb9000000, irq 4, mode: rgmii
- after:
ag71xx-legacy 19000000.eth: invalid MAC address, using random address
ag71xx-legacy 19000000.eth: connected to PHY at mdio.0:00 [uid=004dd034, driver=Generic PHY]
eth0: Atheros AG71xx at 0xb9000000, irq 4, mode: rgmii
As the PHY is already bound to the fallback "Generic PHY" driver when
the ar8xxx module is loaded, the switch remains non-functional and the
router has no network connectivity.
Fix by also compiling the MAC driver (ag71xx-legacy) as a module,
deferring switch initialization until control is transferred to
userspace during boot. The configured module autoload priorities
(ar8xxx: 43, ag71xx-legacy: 50) ensure that the ar8xxx driver is loaded
before ag71xx-legacy.
Fixes: https://github.com/openwrt/openwrt/issues/23739
Fixes: 9091c9f8cb ("ath79: mikrotik: compile SWCONFIG and AR8216_PHY as modules")
Suggested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Michał Kępień <openwrt@kempniu.pl>
Link: https://github.com/openwrt/openwrt/pull/23748
Signed-off-by: Robert Marko <robimarko@gmail.com>
Sometimes redundancy is so obvious that one likely misses it. Trying to
bring all SerDes setup into a unified shape, one thinks twice if
something is really needed or not.
For the RTL838x case, the single writes for take/release reset were still
an outlier. Looking closer at them one can see that the same bits are all
covered already in deactivate/activate. So before, they have been put
into the desired state but those outlier writes mess with them again.
[0, 3, 0x7146/0x7106] just deals with the SOFT_RST bit that is already
covered by rtpcs_838x_sds_reset.
[0, 0, 0xc00] touches multiple bits, amongst the EN_RX/EN_TX bits
already covered in deactivate/active. Moreover, it potentially forces
other bits into a state causing broken functionality, e.g.
INV_HSI/INV_HSO which deal with the polarity. This has no effect right
no right now but might be a latent issue in the future.
Also move the reset call down to the end of the function, doing a
soft/RX reset after every configuration is done. This is likely what the
SDK also intended, and mirrors the 839x behavior.
Link: https://github.com/openwrt/openwrt/pull/23746
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Reduce the per-SerDes patching to a per-mode patching since they share a
lot of similarities, especially for QSGMII.
For fiber patching, the differences are bigger. This takes an approach
to merge the sequences completely despite applying some settings which
weren't applied before on one of the SerDes. Testing and SerDes dumps
showed no or minimal differences, and no practical effect on
functionality. A look at the SerDes register documentation we have shows
reordering the writes isn't problematic because most of the bits aren't
any trigger bits.
With all its users gone, we can now drop also the workaround SDS macro.
Link: https://github.com/openwrt/openwrt/pull/23741
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Rosen Penev
David Bauer
Carlo Szelinsky
Jonas Jelonek
Ryan Leung
Qingfang Deng
Seo Suchan
Sebastian Schaper
Donghyun Ko
Shiji Yang
Josef Schlehofer
Markus Stockhausen
John Audia
Paul Spooren
Aliaksandr Babrykovich
Michał Kępień